Fundamentals of CMOS Analog

Integrated Circuit
Chen Xiaofei
 简 介

◼ 副教授，博士，博士后
◼ 东湖高新技术开发区3551人才 译
◼ IMEC和CPES访问学者
◼ NSFC评审专家
◼ 20余年模拟IC设计经验 著
◼ 委托设计并量产芯片20余款

研究方向：信号链模拟前端，高精度ADC，DC-DC Converter

研
究
基
阵列型ROIC 高精度ADC CDC/HALL 电源管理与转换 光通信LDD PA/LNA
础

VLSI, OEI 2
xfchen@hust.edu.cn 13545865907
VLSI, OEI
3

招生宣传海报

最具特色的专业课！
选修课中的必修课！

VLSI, OEI 3
 课程网站 1

➢ http://oei.hust.edu.cn 热点链接“学院课程中心”
http://115.156.150.106/bbs/forum.php?mod=forumdispla
y&fid=2。需要此论坛账号的同学，私信邹老师
(6089289)你的学号。

CMOS I VLSI, OEI 4

 课程网站2

➢ https://mooc1.chaoxing.com
➢ 课件视频
➢ 课后作业：提交、参考答案
➢ 课后作业视频讲解
➢ 课件和教材pdf
➢ 随堂测试

VLSI, OEI 5
5
 EDA云平台：eSchema和eSpice

➢ eSchema和eSpice是武汉九同方公司提供的基于云的
全定制IC设计云平台（http://www.eda9cube.com）

帐号密码：
学号
#abcd1234

九同方华科 IC交流QQ群：387593733
CMOS I VLSI, OEI 6
 赛课结合
➢ 每年上半年，结合《模拟集成电路课程设计》，参加“全
国大学生集成电路设计大赛”。
➢ 热烈欢迎同学们参与上述比赛！
➢ http://oei.hust.edu.cn/info/1216/5365.htm

CMOS I VLSI, OEI 7

 赛课结合——保研加分

➢ 规则解释：
➢ 全国总决赛特等奖（3分）
➢ 全国总决赛一等奖（3分）
➢ 全国总决赛二等奖（2分）
➢ 全国总决赛三等奖（1分）

CMOS I VLSI, OEI 8

VLSI, OEI
9

我院近8年参加全国大学生集成电路设计大赛情况

大赛时间 参赛队数 获奖队伍数 获奖比例（%） 最高奖项

2022年 71 40 56 全国一等奖2项
2021年 49 28 57 全国二等奖2项
全国一等奖1项
2020年 37 17 46
获“艾为杯”
2019年 28 11 39 全国一等奖1项
全国特等奖1项
2018年 28 22 79
全国一等奖2项
2017年 27 15 56 全国一等奖1项
2016年 22 6 27 全国一等奖1项
2015年 18 6 33 全国二等奖2项
2014年 20 2 10 全国一等奖1项

VLSI, OEI 9
 Information
➢ Required textbook
— Razavi《Design of Analog CMOS Integrated Circuits》

CMOS I VLSI, OEI 10

 Information

➢ Recommended texture
book
– Analysis and Design of
Analog Integrated
Circuits, 4th Edition,
Gray, Hurst, Lewis and
Meyer, Wiley, 2001.
– The electronic version
can be download from
our ftp server
– ftp://202.117.48.63

CMOS I VLSI, OEI 11

 Information
➢ Reference
Rincon Mora, Philip Allen, Sansen

CMOS I VLSI, OEI 12

 Simulation Reference
◼ Hspice Handbook
◼ 《深入浅出学习CMOS
模拟集成电路》

CMOS I VLSI, OEI 13

 Assignments
➢ Assignments
— Lecture 40 hours
➢ Course Grade Composition
– Textbook Homework 10 ％
– Supplement/Simulation homework 10 ％
– Simulation Number of Times 10 ％
– Final Exam 70 ％
➢ Important note:
– Your can ask any question before the exam, but never get to
me after the exam.

CMOS I VLSI, OEI 14

 Question ？
➢ BBS
➢ Phone： 13545865907
➢ QQ群： 387593733
➢ 光电信息大楼，C760

CMOS I VLSI, OEI 15

 TA Information

CMOS I VLSI, OEI 16

 Circuit Simulation

➢ Primary tools:
– HSpice/Awaves
– eSpice/eSim/eSchema http://www.eda9cube.com
➢ Course Technology
– 0.35/0.18μm CMOS
➢ Caution
– Spice is nothing but a "calculator" that lets you evaluate
and test your ideas
– There is no need to simulate anything unless you already
know the (approximate) answer!
CMOS I VLSI, OEI 17
 Course Topics
➢ Introduction to Analog Design
➢ CMOS technology and device models
➢ Single-stage amplifiers
➢ Differential pairs
➢ Current sources and mirrors, active loads
➢ Frequency Response of Amplifiers
➢ Feedback
➢ Operational Amplifier
➢ Stability and Frequency Compensation
CMOS I VLSI, OEI 18
 Lecture 1
Introduction to Analog Design
Chen Xiaofei
 Overview
➢ Reading
– Chapter 1 (p1-8)
➢ Introduction
– In this first lecture, we will introduce “Why CMOS
Analog Integrated Circuit?” and “General Concepts
in Analog Design.”

CMOS I VLSI, OEI 20

 History of IC

CMOS I VLSI, OEI 21

 Modern Semiconductor Industry
➢ The Goal of Semiconductor industry:
– Providing Chips (or Integrated Circuits, IC) based on a
silicon wafer
Package: End product
of IC industry

PCB

Chip (IC): with area

Wafer: up to tens of mm2. An
Diameter up to IC may contain IC
12 inch (30cm) millions of transistor. Industry

CMOS I VLSI, OEI 22

 Wafer Example

On a 300mm wafer, blown up to the size of

the Netherlands, 1nm equals 1mm
CMOS I VLSI, OEI 23
 Chips have many forms and functions

Gyroscope
MRAM (Magnetic
( UC Irvine)
Freefloating sensors RAM)
(Holst Centre)
Camera pill with
camera, transmitter 40Watt Energy
and computer Harddisk Harvester
read/write head (IMEC)
( TFH Berlin)
Accelerometer DNA analysis
( IC Mechanics) (Affymetrix)

QuadCore 32 Gbit memory

Microprocessor (Intel)
Micromirrors for Accelerometer in
(AMD) Lab on a Chip (LOC)
beamers (TI) the iPhone (Apple)
for
counting red blood cells

CMOS I VLSI, OEI 24

 IC production flow
Idea：Production Definition（function, cost, ….）

System design：architecture design (analog/digital partition)

Analog circuit Design： Digital circuit design：

Schematic design RTL coding and simulation
Circuit simulation Synthesis
Layout design Place and Route
Layout verification Physical Verification

Mixed-signal Integration: systematic verification

Tapeout (Foundry) Package and Testing

CMOS I VLSI, OEI 25
 Business Mode of IC Industry
➢ Unique Business Mode:
– Separation of Design and Fabrication, Why?
– Huge cost of IC production line
• 65nm 12 inch CMOS line: >$3 billion
– Very few companies construct their own line
• Intel, SAMSUNG, AMD, TI… we call them “IDM”.
(Integrated Device Manufacturer )
– Others are “Fabless”
– Famous Foundries:
• TSMC/ UMC/ SMIC/ X-FAB……

CMOS I VLSI, OEI 26

 What you can do in IC industry

➢ System engineer
– audio and video signal processing, communication…
➢ IC design
– Analog IC design : ADC/DAC/PLL/Power/….
– Digital IC design:
• Front end: RTL coding
• Backend: Synthesis, place and route, timing
analysis
➢ Foundry
– Device modeling, processing development
➢ EDA Tool: Cadence/Synopsys/Mentor
➢ IC Package and IC testing
CMOS I VLSI, OEI 27
 Differences between Analog and Digital (1)

➢ Signal representation
– Digital
• Information is recorded both in discrete time and
discrete amplitude
• Only have two status: supply voltage (“1”) or
ground (“0”).
• Often use multi-bit bus to express a signal
– Analog
• Information is recorded both in continuous time and
continuous amplitude
• The value at any time is important
• Single-ended or differential
CMOS I VLSI, OEI 28
Differences between Analog and Digital (2)

CMOS I VLSI, OEI 29

 Differences between A/D : Design methodology
– Digital
• Circuit is described with hardware description language
(HDL)
• Basic building block is standard cells (INV, NOR.. )
• Layout is obtained by software (automated)
• Tools play very important role in the design flow
– Analog
• Circuit is described with schematic or netlist
• Basic devices are transistors, capacitors and resistors,
Higher-level extraction is amplifier, filter, comparator…
• Layout is designed manually. “Art of layout design”
• Wisdom and experience of human predominate the design

CMOS I VLSI, OEI 30

 A full_adder example

CMOS I VLSI, OEI 31

 Full adder used in a digital circuit

Layout of a full adder Poly Layer

Metal 1

➢ The layout is obtained by a auto-place and route software

CMOS I VLSI, OEI 32
 An Operational Amplifier Example

➢ The size of each transistor is designed elaborately to

meat the performance requirement
CMOS I VLSI, OEI 33
 Die photo of the OP

CMOS I VLSI, OEI 34

IC industry is driven mainly by digital CMOS technology

➢ Digital circuit: Fully benefited From IC device scaling

– Cost/function decreased by 29% each year
– CPU, memory, DSP
➢ Analog circuit: not fully benefited
– Device scaling mandates drop in supply voltage
– Device matching difficulties
– Cost/function almost constant of increase
➢ More and more signal processing functions are shifted from
analog domain to digital domain
– This is a digital world!

VLSI, OEI 35
 Digital System Exist Today
– Digital Mobil Phone;
– Digital Film;
– Digital TV;
– Digital Power Amplifier;
– Digital filter;
– Digital ……

CMOS I VLSI, OEI 36

 Comparisons of analog/digital products

➢ The 1st-generation pure • iphone 4s

analog mobile phone

VLSI, OEI 37
 Will analog circuit disappear in the future?

➢ Definitely No! Why?

➢ Currently, ASIC flow can only synthesize circuits with “medium
frequency” (below 500MHz)
– Standard cells and I/Os are designed in transistor level
– Memory cell designed and simulated by “analog” method
➢ To improve the performances of the current digital circuit, many
“analog” problems need to be solved (increase speed, reduce power
dissipation)
– Charge sharing
– Interconnect parasitic
– ……

VLSI, OEI 38
 Example：digital signals on PCB

➢ High speed digital

signals are distorted
by parasitic RC
➢ Received signal is “0”
or “1”?
➢ Analog circuits are
need to assist signal
receiving
– LVDS

VLSI, OEI 39
 The truth of why analog will always exist

➢ Every thing in IC is analog!

➢ Signals in real world are analog. Interface circuits must be used to convert
them into digital
– For most cases, analog paths are critical paths

VLSI, OEI 40
 Example 1: A RF transceiver for mobile phone

Analog Digital

VLSI, OEI 41
 Chip photo

Analog digital
VLSI, OEI 42
 Cell Phone
➢ RF
➢ Power Management
➢ Analog Baseband
➢ Filters and ADC/DAC
➢ ……

CMOS I VLSI, OEI 43

Filters and ADC/DAC in a mobile phone

VLSI, OEI 44
 Example 2: Optical Receivers

CMOS I VLSI, OEI 45

 Example 3: Sensors

CMOS I VLSI, OEI 46

MEMS Accelerometer

VLSI, OEI 47
 Biochemical sensors
Nanoscaled Acoustic Wave
IDE Sensors Sensors

• DNA • antibody/antigen
• antibody/antigen • immunosensing
• immunosensing • liquid identification

CMOS Integrated
Multiparameter
Sensors

• Bloodgas sensor
• pCO2, pO2, pH
Microphysiometer
• HTDS
• Calorimetric (D heat)

CMOS I VLSI, OEI 48

 Wireless Body Area Network

CMOS I VLSI, OEI 49

 Hearing-aid

CMOS I VLSI, OEI 50

 Intelligence Vehicles

CMOS I VLSI, OEI 51

Some Semi-conductor enabled functions of a typical car

Body & Convenience

Xenon Light, Seat Position,
Powertrain Climate Control, Dashboard
Engine Control Climate Control
Transmission Control
Battery Management Airbag Night Vision Park Distance
Control
Steering
Transmission
Hybrid Dashboard
Engine Blindspot
Cooling Detection Suspension
FAN TPMS
Battery Mirror Door Brake
Light Management
Central Lock ABS ESP
Adaptive
Cruise Control

Safety Chassis
Airbag, ABS Brakes, Active Suspension,
Adaptive Cruise Control Power Steering

CMOS I VLSI, OEI 52

Nico Kelling (IFJ AIM MC)
Ubiquitous + Healthcare = U-Healthcare

CMOS I VLSI, OEI 53

 Why analog design？(summary)

➢ Interface between analog signal and digital signal （ADC）

➢ Amplifying and processing for natural signals (Amplifier & Filter)
➢ Design in higher speed digital circuits.
(High-speed digital design is in fact analog design.)
➢ Mixed-signal circuits and SOC
➢ More important:
– Salary of a analog engineer is often 1.5 ~ twice of a digital engineer

VLSI, OEI 54
 为什么P50只能支持4G？
➢ 华为P50系列姗姗来迟。遗憾的是，P50系列都仅支持4G
。问题出在5G射频芯片中的核心元器件：滤波器。
➢ 手机射频前端行业最终形成了Skyworks、Qorvo、村田
、博通、高通为代表的龙头厂商。
➢ 射频前端的滤波器，基本被美日厂商垄断。
➢ 体声波滤波器（BAW）成为5G手机首选，目前美国的
博通（Broadcom，AVAGO）一家就占了87%的市场份
额。
➢ 中低端SAW和BAW有国产替代。
VLSI, OEI 55
 Why CMOS Integrated Circuit?

Why CMOS?
➢ Very large scale integration （VLSI） of both high-density digital
circuits (such as DSP and memory) and analog circuits (including
amplifiers, filters, and A/D & D/A converters) for low cost.
➢ Device scaling : new CMOS technologies with smaller feature sizes
(such as 90nm and 65nm) can operate at increasingly high speed
(20GHz), comparable to some bipolar technologies.
➢ Ideal properties of MOS switches for high accuracy sample-data
circuits, such as switched-capacitor filters and A/D & D/A
converters.

CMOS I VLSI, OEI 56

 Bipolar Silicon Technologies
➢ higher frequencies than CMOS with relatively smaller power
consumption.
➢ high power (such as ADSL line drivers) applications.
BiCMOS technologies have most advantages of both
CMOS and bipolar technologies but at the expense of higher
manufacturing cost due to required extra processing steps.

CMOS technologies become mainstream for mixed-

signal integration due to the advantages of low cost, low
power consumption and high integration density.

CMOS I VLSI, OEI 57

 Why CMOS?
– Bipolar for analog
– GaAs for RF
– CMOS for high speed, low area

CMOS I VLSI, OEI 58

 Why Integrated?
➢ Advantages:
– Reduced size
– Improved performance p and functionality
– Easier to hide ”company secrets”
– Reduced cost
– Reduced power consumption
– Less radiated noise
➢ Disadvantages:
– Increased start-up cost
– High power density – Heat
– Time consuming development and production
– Time-to-market

CMOS I VLSI, OEI 59

 SoC

CMOS I VLSI, OEI 60

 Important analog modules
➢ What can we design :
– Power Management: AC-DC, DC-DC, LDO
– RF modules: LNA, Mixer, PA, Synthesizer
– IF modules: filter, VGA
– Interface modules: ADC, DAC
– Clock signal generation: PLL

VLSI, OEI 61
 Why is analog design difficult?

1. Analog circuits deal with multi-dimensional

tradeoff of speed, power, gain, precision, supply,
…
(Digital circuits deal primarily with speed power
tradeoff.)
2. Due to speed and precision requirements, analog
circuits are much more sensitive to noise,
crosstalk, and other interferers.

VLSI, OEI 62
 Why is analog design difficult? (cont.)

3. Analog circuits are much more sensitive to

second-order device effects.
4. High performance analog circuit design can rarely
be automated - typically require hand-crafted
design and layout.
5. Modeling and simulation of analog circuits is still
problematic, requiring experience and intuition.

VLSI, OEI 63
 Why is analog design difficult? (cont.)

6. Economic forces require the development of

analog circuits in mainstream digital processes.
7. Economic forces pushing the integration of
analog and digital functions onto a single
substrate（SOC）.
8. Continuous reduction of feature sizes, the power
dissipation and supply voltages (technology
scaling) further exacerbates analog design
challenges.
VLSI, OEI 64
 Where to go?

➢ Digital assisted analog design

– Mixed signal IC design

VLSI, OEI 65
 The future of IC industry

➢ More Moore?
– Develop transistors with length less than 10nm.
– CPUs, memories, and DSP are beneficial
– Small companies and universities are out
– Only a few companies can afford
➢ More than Moore ?
– Continue to use IC processes with large feature size (0.18um,
0.13um), but integrate more
– Good for analog IC design
– functions on a chip (RF, MEMS, bio, optical… )
– Small companies and universities prefer this

VLSI, OEI 66
 SiP Definition
➢ Stacked die packages
➢ Multichip Packages
➢ Stacked Packages
➢ TSV

CMOS I VLSI, OEI 67

 Drivers for SiP
➢ Greater functionality in a smaller area is the driver for consumer and
portable products
➢ High performance is the main driver for computer, telecommunications,
and military aerospace
➢ Some applications such as medical driven by both
➢ Applications, such as network systems, driven by the need to decrease
motherboard layer counts and complexity

CMOS I VLSI, OEI 68

 What will you learn in this course

➢ Learn basic knowledge for CMOS analog IC design, including but not
limited to:
– Chapter 2: Basic MOS Device Physics
– Chapter 3: Single-Stage Amplifier
– Chapter 4: Differential Amplifier
– Chapter 5: Passive and Active Current Mirrors
– Chapter 6: Frequency Response of Amplifier
– Chapter 8: feedback
– Chapter 9: Operational Amplifier
– Chapter 10: Stability and Frequency Compensation

VLSI, OEI 69
 Journals and Conferences for analog researcher

➢ Journals：
– （JSSC） IEEE Journal of Solid-State Circuits
– （TCAS）IEEE Transaction on Circuit and System I ,II
– IET Electronics Letters、IEICE Trans. Electronics
– Analog Integrated Circuits and Signal Processing
– 半导体学报
➢ Conferences：
– ISSCC
– International Symposium on Circuits and Systems (ISCAS)

VLSI, OEI 70
 Appendix: Notations

Definition Quantity Subscript Example

Bias(dc Value of the signal) Uppercase Uppercase ID

Signal(ac Value of the signal) Lowercase Lowercase id
Bias+Signal Lowercase Uppercase iD
(Total instantaneous of the
signal)
Complex variable, phasor,
Uppercase Lowercase Idm
or RMS value of the signal

Chenxiaofei VLSI, OEI 71

71
 Notation for Signals

Notation for Signals

Chenxiaofei VLSI, OEI 72

72
 Homework 1
➢ 了解集成电路发展历史。
➢ 了解集成电路设计的大致流程。
➢ 了解EDA。
➢ 看论坛上的文章 http://115.156.150.106/bbs/forum.php

CMOS I VLSI, OEI 73

 Summary of Chap 1

➢ Why CMOS Analog Integrated ?

➢ What Will We learn in this course？

CMOS I VLSI, OEI 74

 为什么P50只能支持4G？
➢ 华为P50系列姗姗来迟。遗憾的是，P50系列都仅支持4G
。问题出在5G射频芯片中的核心元器件：滤波器。
➢ 手机射频前端行业最终形成了Skyworks、Qorvo、村田
、博通、高通为代表的龙头厂商。
➢ 射频前端的滤波器，基本被美日厂商垄断。
➢ 体声波滤波器（BAW）成为5G手机首选，目前美国的
博通（Broadcom，AVAGO）一家就占了87%的市场份
额。
➢ 中低端SAW和BAW有国产替代。
VLSI, OEI 75
Thank You!