Unit-8 - Advanced Microprocessor
Unit-8 - Advanced Microprocessor
(MPI)
GTU # 3160712
Unit-8:
Advanced
Microprocessor
Positive Vibes:MPI is the interesting, easiest and scoring subject.
Subject Overview
Positive Vibes:MPI is the interesting, easiest and scoring subject.
Sr. No. Unit % Weightage
1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 12%
4 Assembly Language Programming Basics 13%
5 8085 Assembly Language Programs 12%
6 Stack & Subroutines 13%
7 I/O Interfacing 20%
8 Advanced Microprocessors 15%
▪ Introduction to 8086
▪ 8086 logical block diagram
▪ 8086 Segmentation
▪ 8086 Pin functions
▪ Minimum and Maximum mode
▪ 80286/80386:
✓ Overview and architecture
✓ Programming model,
✓ Data types and instruction set,
✓ Segments and its types
✓ Segment descriptor
✓ Descriptor table and selectors
Positive Vibes:MPI is the interesting, easiest and scoring subject.
Introduction to 8086
Introduction to 8086
8086 is a 16-bit processor, which implies that Positive Vibes:MPI is the interesting, easiest and scoring subject.
8086 Architecture
Block Diagram
Memory
Interface
6
5 Instruction
4 stream BIU
ES 3 byte
8086 Architecture
CS 2 queue
SS 1
DS
IP Control
15 0
System
15 8 7 0
AX AH AL
BX BH BL Arithmetic logic
CX CH CL unit EU
DX DH DL
SP
BP Operands
SI Flags
DI
8086 Architecture
• In 8086 CPU is divided into two independent functional units: Positive Vibes:MPI is the interesting, easiest and scoring subject.
6
5 Instruction
4 stream BIU
ES 3 byte
CS 2 queue
SS 1
DS Segment Register:
IP
15 0 Four 16-bit Pointer:
Instruction register that provides powerful
memory
Registermanagement mechanism
that holds 16-bit address or offset
ES
of (extra segment),
next code CS (code
byte within codesegment),
segment.
SS (stack segment) , DS (data segment).
Unit 8 – Advanced Microprocessor 11
Task of BIU
1. Fetch instructions from memory. Positive Vibes:MPI is the interesting, easiest and scoring subject.
5. Queuing instructions.
EUContains
has 4 16-bit
general Performs
16-bit various internal operations.
ALU, purpose
that performs
register i.e. AX, BX,
add, subtract, CX, DX decrement,
increment,
each register isshift,
compliment, the combination
AND, OR, XORof etc.
two Control
8-bit register. System
15 8 7 0
AX AH AL
BX BH BL
CX CH CL
Arithmetic logic unit EU
DX DH DL
SP
BP Operands The 16-bit flag
Operand register
register: of 8086
16-bit contains
register used
SI SI (Source Index)
Flags
and DI9(Destination
active flags (6 conditional & 3 hold
control
DI Index) are used for string by the
related control register to the
Stackpointer:
Base pointer:used
It always
for points
flags), to
other
operands
indirect thetemporarily.
7top
addressing. flags
of are undefined.
operation
the stack. and
Usedforfor
moving block ofaccess of
sequential
memory
stack from one location to another.
segment.
Unit 8 – Advanced Microprocessor 13
Task of EU (Execution Unit)
1. Decodes the instruction. Positive Vibes:MPI is the interesting, easiest and scoring subject.
6
5 Instruction
4 stream BIU
ES 3 byte
8086 Architecture
CS 2 queue
SS 1
DS
IP Control
15 0
System
15 8 7 0
AX AH AL
BX BH BL Arithmetic logic
CX CH CL unit EU
DX DH DL
SP
BP Operands
SI Flags
DI
GTU Exam Questions
Sr. Questions Marks
Positive Vibes:MPI is the interesting, easiest and scoring subject. Year
1. Draw and explain internal architecture diagram of 8086 microprocessor. 7 S’18
W’19
2. Differentiate 8085 microprocessor with 8086 microprocessor. 4 S’18
3. What are the addressing capacity of 8085 microprocessor and 8086 microprocessor? 3 S’18
2. Data Segment (DS): Contains data used by a program. Data can be accessed from this by an
offset address.
3. Stack Segment (SS): Defines an area of memory used for the stack.
4. Extra Segment (ES): ES an additional data segment.
Segmentation in 8086
Segmentation in 8086
What is Segment? Positive Vibes:MPI is the interesting, easiest and scoring subject.
An area in memory.
What is Segmentation?
The process of dividing memory into segments of various sizes is called Segmentation.
What is the need of segmentation in 8086? Positive Vibes:MPI is the interesting, easiest and scoring subject.
1 MB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
64KB
With 20 address lines, the memory that can be addressed is 220 bytes.
220 = 1,048,576 bytes
1 MB = 1111 1111 1111 1111 1111
= FFFFF H
64
FFFF H
SEG-1 KB
0000 H
SEG-2
256 KB
SEG-3
SEG-4
Segment Registers are used to hold the upper 16-bit of the starting address for each of the
segment.
The 16-bit address is starting address of the segment from where the BIU is currently fetching
instruction code bytes.
The BIU always inserts zero(0) for the LSB(Least Significant Bit) to generate 20-bit address.
Segmentation in 8086
Example
Segmentation in 8086: Example
Example: Base address DS=2222 H Positive Vibes:MPI is the interesting, easiest and scoring subject.
22220 H
PA = 2222 H: 008F H
OFFSET=008F H
BYTE-N 222AF H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U U U U OF DF IF TF SF ZF U AF U PF U CF
Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from lower
nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e. carry given by D3 bit to D4
is AF flag. This is not a general-purpose flag, it is used internally by the processor to perform
Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the
result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity
Flag is reset.
Zero Flag (ZF): It is set(1), if the result of arithmetic or logical operation is zero else it is
reset(0).
Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the
result of operation is negative, sign flag is set(1).
bus.
AD0-AD7 carry lower order byte of data and AD8-AD15
carry higher order byte of data.
When ALE=1, then Address bus gets enabled, else Data
bus will get enabled.
status bus.
During T1, they carry higher order address.
In the remaining clock cycles, they carry status
signals.
S5 gives the status of Interrupt Flag (IF)
S6 goes low, when 8086 controls the shared system
bus.
S3 and S4 indicates the segment register.
S4 S3 Register
0 0 ES
0 1 SS
1 0 CS
1 1 DS
signal.
BHE signal is used to indicate the transfer of data over
higher order data bus (D8- D15).
8-bit I/O devices use this signal.
S7 is reserved for future development.
operation of processor.
8086 clock frequency: 5MHz-10MHz
S2 S1 S0 Indication
0 0 0 Interrupt acknowledgement
0 0 1 Read I/O
0 1 0 Write I/O
0 1 1 HALT
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive
DT/R
Data Transmit/Receive signal.
When high, data is transmitted out else when low, data is
received in.
WR
Active low output signal.
Used to write data in memory or output signal,
depending on status of M/IO signal.
HLDA
Active high Hold Acknowledgement output signal.
It is issued by 8086 after receiving HOLD signal.
1. Explain the following pins of the 8086 microprocessor: TEST , LOCK , MN/MX. 3 W’17
80286
80286
The Intel 80286 had a 24-bit address bus and was able to address up to Positive Vibes:MPI is the interesting, easiest and scoring subject.
80286 Architecture
ADDRESS UNIT BUS UNIT 80286 Architecture
A0-A23 80286 contains 4
ADDRESS BHE
PHYSICAL
Positive Vibes:MPI
M/IO separate processing units
is the interesting, easiest and scoring subject.
LATCHES AND DRIVERS
ADDRESS 1. Bus Unit (BU)
ADDER
PROCESSOR PEACK
2. Instruction Unit (IU)
SEGMENT PREFETCHER EXTENSION PEREQ
BASES INTERFACE
3. Address Unit (AU)
READY,
SEGMENT HOLD 4. Execution Unit (EU)
LIMIT SEGMENT BUS CONTROL
SIZE S1,S0,
CHECKER COD/INTA
OFFSET
ADDER DATA TRANSCEIVERS LOCK,HLDA
D15-D0
6-BYTE
PREFETCH
QUEUE
ALU
RESET
REGIS CLK
TERS control 3 DECODED
INSTRUCTION VSS
INSTRUCTION
DECODER VCC
QUEUE
CAP
EXECUTION UNIT INSTRUCTION UNIT
ERROR
BUSY
INTR
NMI
80286 Architecture: Bus Unit (BU)
Components: Positive Vibes:MPI is the interesting, easiest and scoring subject.
1. Segment Bases
2. Segment Limit Checker
3. Segment Size
4. Offset address
5. Physical address adder
Functions:
It computes physical address
that will be sent out to the memory
or I/O by Bus Unit (BU).
80286 operate in two different modes
1. Real address mode
2. Protected Virtual Address Mode.
Unit 8 – Advanced Microprocessor 64
ADDRESS UNIT BUS UNIT 80286 Architecture
A0-A23 80286 contains 4
ADDRESS BHE
PHYSICAL
Positive Vibes:MPI
M/IO separate processing units
is the interesting, easiest and scoring subject.
LATCHES AND DRIVERS
ADDRESS 1. Bus Unit (BU)
ADDER
PROCESSOR PEACK
2. Instruction Unit (IU)
SEGMENT PREFETCHER EXTENSION PEREQ
BASES INTERFACE
3. Address Unit (AU)
READY,
SEGMENT HOLD 4. Execution Unit (EU)
LIMIT SEGMENT BUS CONTROL
SIZE S1,S0,
CHECKER COD/INTA
OFFSET
ADDER DATA TRANSCEIVERS LOCK,HLDA
D15-D0
6-BYTE
PREFETCH
QUEUE
ALU
RESET
REGIS CLK
TERS control 3 DECODED
INSTRUCTION VSS
INSTRUCTION
DECODER VCC
QUEUE
CAP
EXECUTION UNIT INSTRUCTION UNIT
ERROR
BUSY
INTR
NMI
Positive Vibes:MPI is the interesting, easiest and scoring subject.
Flag Register
MSW
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U NT IOPL OF DF IF TF SF ZF U AF U PF U CF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TS EM MP PE
Task Switch
EMulateMonitor
processor extension
Processor flag
extension
TS is automatically
If SET, EMulate
If SET,SET
thiswhenever
coprocessor
flag allowsabittask
WAIT switch
is set to cause all
instruction to generate
operation Used
is performed.
coprocessor to
opcodesindicate whether
to generate a processor
a Coprocessor extension
a processor extension
(co-processor) is not
present present
in the exception.
system or not.
Not Available fault.
Protected Mode Enable
PE=1; Places 80286 in protected mode
PE=0; It can be only RESET by resetting CPU
Address Unit computes the address with segment base and offset like 8086.
Maximum physical space allowed in this mode is 1MB.
When 80286 get RESET, it always starts execution in real mode.
Task of 80286 in Real Mode
Initializes Instruction Pointer(IP) and other registers of 80286.
Initializes the peripheral.
Enable Interrupts.
Set up descriptor table.
Prepares for entering in PVAM (Protected Virtual Address Mode).
20-BIT PHYSICAL
MEMORY ADDRESS
OFFSET=008F H
BYTE-N 222AF H
memory address.
Virtual memory can be many times larger than physical memory.
Only programs that are currently required brought from the secondary storage such as a hard
disk to the physical memory (RAM) for execution.
This is desirable as a microprocessor is supposed to store large programs and data can’t be
accommodated in the physical memory space.
CPU
POINTER
SELECTOR OFFSET
SEGMENT
MEMORY
OPERAND
PHYSICAL
ADDRESS
ADDER
SEGMENT
DESCRIPTOR
SEGMENT TABLE
DESCRIPTOR
SEGMENT BASE 24-bit
ADDRESS
Applications
(Lowest Privilege
Level) 01
OS Service
00
Kernel
Level
(highest)
10
OS
Extension
PVAM : Selector
PVAM : Selector
TI-Table Indicator Positive Vibes:MPI is the interesting, easiest and scoring subject.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Selector TI RPL
00 Kernel Level
Bit 3-15 points to the
Entry of Descriptor Table 01 OS Services
10 OS Extension
11 Application Level
Descriptor Table
GDT & LDT
What is Descriptor Table?
Definition Positive Vibes:MPI is the interesting, easiest and scoring subject.
15 8 7 0
7 INTEL RESERVED 8
3 BASE 15-0 4
1 LIMIT 15-0 2
7 6 5 4 3 2 1 0
P DPL S E ED/C R/W A
Read : Code
Expansion Segment
Direction: Executable
Data Segment {when E=0}
R=0Segment
Code Segment execute Accessed
only,
E=0: Data TYPE
Segment
ED=0 expands upward (Data segment)
ED=1
Sets the not readable
Segment expands
Descriptor downward
Privilege Level A=0
E=1:(Stack
(DPL) Segment
Code not
Segment
Segment)
necessary accessed
for
P=0: Descriptor is undefined, noA=1 mapping to
Segment has been accessed
R=1
protection Code Segment both
physical memory exists.
executable & readable
P=1: Segment is mapped
S=0:Conforming:
System into Segment
Code physical {when E=1}
descriptor(GDT)
memory.
S=1:C=0 Ignore DPL
Application Descriptor(LDT)
Write : Data Segment
C=1 Code segment will only be executed when
W=0 Data segment not writable
CPL > DPL
W=1 Data segment writable
80386
80386: Introduction
80386 is 32-bit microprocessor. Positive Vibes:MPI is the interesting, easiest and scoring subject.
80386 Architecture
80386 Architecture
Execution Unit Segment Unit Paging Unit
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Segment Page
Register File Descriptor Descriptor
Barrel Shifter Cache Cache
ALU Segment Unit Page Unit
Instruction Unit
Segment Unit
Upon enabling the paging mechanism, the 80386 translates these linear Page
Descriptor
addresses into physical addresses. Cache
If paging is not enabled, the physical address is identical to the linear
Page Unit
address and no translation is required.
Segment Page
Register File Descriptor Descriptor
Barrel Shifter Cache Cache
ALU Segment Unit Page Unit
Instruction Unit
EAX AX ACCUMULATOR CS
EBX BX BASE INDEX SS
ECX CX COUNT DS
EDX DX DATA ES Data
ESP SP STACK POINTER FS Segment
EBP BP BASE POINTER GS
ESI SI SOURCE INDEX 15 0
EDI DI DESTINITION INDEX
31 0
EIP IP
EFLAGS FLAGS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U NT IOPL OF DF IF TF SF ZF U AF U PF U CF
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VM RF
Resume Flag
Virtual
• It is used in Mode Enable
conjunction with the debug register breakpoints.
• When RF isWhen VM=1;
set(1), 386 will
it causes anyswitch
debug from
fault Protected to virtual
to be ignored on themode
next instruction.
• The RF flag temporarily disables debug exceptions so that an instruction can be
restarted.
• RF is then automatically reset at the successful completion of every instruction.
Unit 8 – Advanced Microprocessor 110
Operating Modes of 80386
1. Real Address Mode Positive Vibes:MPI is the interesting, easiest and scoring subject.
In real address mode, 80386 works as a fast 8086 with 32-bit registers and data types.
Real-address mode is in effect after a signal on the RESET pin.
Even if the system is going to be used in protected mode, the start-up program will execute in
real mode temporarily while initializing for protected mode.
The addressing techniques, memory size, interrupt handling in this mode of 80386 are similar
to the real addressing mode of 80286.
In real address mode, the default operand size is 16-bit but 32-bit operands and addressing
modes may be used with the help of override prefixed instructions.
Maximum physical memory = 1MB.
Virtual addresses are represented with a selector component and an offset component.
The selector component is used to index a descriptor in a descriptor table.
The descriptor contains the 32-bit physical base address for the segment.
The offset part of the virtual address is added to the base address to produce the actual
physical address.
The offset part of a virtual address can be 16-bit or 32-bit, so segment can be as large as 4GB.
Hence the virtual memory size is 64TB.
Limitation of segmentation of memory: If we need only a part of memory, even then we have to
swap the whole segment content. This will increase the time for execution.
In virtual mode, 8086 can address 1MB of physical memory that may be anywhere in the
4Gbytes address space of the protected mode of 80386.
In this mode, instead of segments, 4KB of fixed page length are used.
Paged Mode
Selector
Segmentation Linear Address Paging Physical Address
Offset
Mechanism Mechanism
Each page table is of 4KB in size and contain maximum 1024 pages.
31 12 11 10 9 8 7 6 5 4 3 2 1 0
U R
Page Frame Address
Reserved 0 0 D A 0 0 / / P
(A31-A12) S W
A linear address refers indirectly to a physical address by specifying a page table, a page within
that table, and an offset for that page.
31 22 21 12 11 0
DIRECTORY TABLE OFFSET
USER MEMORY
80386
+ Memory
31 PAGE TABLE 0
31 DIRECTORY 0 +
CONTROL
+
REGISTERS
CR3
80386:Page Translation Mechanism
80386:Page Translation Mechanism
CR3: Enables processor to translate linear addresses into physical addresses by locating the
Positive Vibes:MPI is the interesting, easiest and scoring subject.
N-bit Processor (data bus) 8-bit 16-bit 16-bit 32-bit 32-bit 64-bit
Address bus 16-bit 20-bit 24-bit 32-bit 32-bit 32-bit
Addressable Memory 64KB 1MB 16MB 4GB 4GB 4GB
Introduced in Year 1976 1978 1982 1985 1989 1993
Support Virtual Memory NO NO YES YES YES YES
Support Segmentation NO YES YES YES YES YES
Supports Paging NO NO NO YES YES YES
Operating Modes 1 2 3 3 3 3
Support Cache Memory NO NO NO NO YES YES
Contains on-chip FPU NO NO NO NO YES YES
Supports Instruction Queue NO YES YES YES YES YES
The 8088 and 8086 Microprocessors, Triebel & Singh, Pearson Education
Mobile Application: 8085 and 8086 Microprocessor Opcodes app from Play Store:
http://tiny.cc/aopcodes
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