Microprocessor and Interfacing

(MPI)
GTU # 3160712

Unit-3:
8085
Microprocessor Positive Vibes:MPI is the interesting, easiest and scoring subject.
Subject Overview

Sr. No. Unit % Weightage

1 Introduction to Microprocessor 8%
2 Microprocessor Architecture and Operations 7%
3 8085 Microprocessor 12%
4 Assembly Language Programming Basics 13%
5 8085 Assembly Language Programs 12%
6 Stack & Subroutines 13%
7 I/O Interfacing 20%
8 Advanced Microprocessors 15%

Unit 3 – 8085 Microprocessor 2

 Topics
Loopingto be covered

▪ Introduction to 8085
▪ 8085 Programming Model
▪ Bus Organization of 8085
▪ 8085 pin diagram
▪ 8085 Architecture/Block Diagram
▪ T-States, Machine and Instruction Cycle
▪ Demultiplexing Address and Data Bus AD0-
AD7
▪ Timing Diagram
▪ Memory Interfacing
▪ Generating Control Signals
Introduction to 8085
Introduction to 8085
 8085 is pronounced as "eighty-eighty-five" microprocessor.
 It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology.

Unit 3 – 8085 Microprocessor 5

Introduction to 8085
 8 bit General purpose microprocessor (i.e. 8 bit data bus).
 It is a single chip N MOS device with 40 pins.
 It has multiplexed address and data bus.(AD0 - AD7).
 It works on 5-Volt DC power supply.
 The maximum clock frequency is 3MHz while minimum frequency is 500kHz.
 It provides 16 address lines, therefore capable of addressing 216= 64K of memory.
 It supports external interrupt request.
 It has two 16 bit registers named program counters (PC) and stack pointer (SP).

Unit 3 – 8085 Microprocessor 6

Introduction to 8085
 It generates 8 bit I/O address so it can access 28 = 256 input ports.
 It provides 5 hardware interrupts:
1. TRAP
2. RST 5.5
3. RST 6.5
4. RST 7.5
5. INTR
 It provides accumulator, 5 flag register, 6 general purpose registers and 2 special purpose
registers (SP,PC).

Unit 3 – 8085 Microprocessor 7

8085 Programming Model
8085 Programming Model

General Purpose Registers

Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

16
8

Bidirectional Unidirectional

Unit 3 – 8085 Microprocessor 9

General Purpose Registers
 6 general purpose registers to store 8-bit data B, C, D, E, H & L.
 Can be combined as fixed register pairs – BC, DE, HL to perform 16 bit operations.
 Used to store or copy data using data copy instructions.

B (8) C (8)

D (8) E (8)

H (8) L (8)

Unit 3 – 8085 Microprocessor 10

8085 Programming Model

Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

16
8

Unidirectional
Bidirectional

Unit 3 – 8085 Microprocessor 11

Accumulator
 8 - bit register, identified as A
 Part of ALU
 Used to store 8-bit data to perform
arithmetic & logical operations.
 Result of operation is stored in
Accumulator.

Unit 3 – 8085 Microprocessor 12

8085 Programming Model

Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

16
8

Bidirectional Unidirectional

Unit 3 – 8085 Microprocessor 13

Flag Register
D7 D6 D5 D4 D3 D2 D1 D0
S Z  AC  P  CY
:Undefined
P -Parity Flag
S -Sign Flag Set (1) if result has even no. of 1’s &
Set (1) if 7th bit of result is 1; Reset(0) if result has odd no. of 1’s
otherwise reset (0) CY -Carry Flag
1 0 0 1 0 0 1 1 Set (1) if arithmetic
AC -Auxiliary
P=1
Carry Flag
1 0 1 0 1 0 1 0 Set (1) when carry bit is operation results in
S = 1Z -Zero Flag carry;
Set (1) when result is zero; generated by 3rd bit &
otherwise reset(0) passed to bit 4th bit. otherwise reset(0)
1 1 1
1 0 1 0 1 0 1 0 1 0 1 0
-1 0 1 0 1 1 1 + 0 1 1 0 1 0 0 1
0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 0 1 1
Z=1 + 0 1 1 0 1 0 0 1 CY = 1
1 0 0 1 0 0 1 1
AC = 1
Unit 3 – 8085 Microprocessor 14
Flag Register
 ALU has 5 Flag Register that set/reset
after an operation according to data
conditions of the result in accumulator
& other registers.
 Helpful in decision making process of
microprocessor.
 Conditions are tested through software
instructions.
For e.g.
JC (Jump On Carry) is implemented to
change the sequence of program when
CY(Carry Flag) is set(1).

Unit 3 – 8085 Microprocessor 15

8085 Programming Model

Accumulator A (8) Flag Register

B (8) C (8)

D (8) E (8)

H (8) L (8)

Stack Pointer (SP) (16)

Program Counter (PC) (16)

Data Bus Address Bus

16
8

Bidirectional Unidirectional

Unit 3 – 8085 Microprocessor 16

Stack Pointer & Program Counter
Stack Pointer(SP)
 Used as memory pointer.
 Points to the memory location in R/W memory,
called Stack.
 Beginning of stack is defined by loading a 16-bit
address in the stack pointer.
Program Counter(PC)
 Microprocessor uses PC register to sequence
the execution of instructions.
 Its function is to point to memory address from
which next byte is to be fetched. GTU Que: Explain 8085 Programming Model and flag
register.[7m] (W’18,W’19)
 When a byte is being fetched, PC is incremented
by 1 to point next memory location.

Unit 3 – 8085 Microprocessor 17

Bus Organization of 8085
System bus

CPU Memory Input/Output

Control Bus

Address Bus

Data Bus

System Bus

Unit 3 – 8085 Microprocessor 19

Bus Organization of 8085
A15
Address Bus
A0

Memory Input

8085 MPU Output

D7
Data Bus
D0

Control Bus

Unit 3 – 8085 Microprocessor 20

Address bus
 Group of 16 unidirectional lines generally identified as A0 to A15.
i.e. bits flow from microprocessor to peripheral devices.
 16 address lines are capable of addressing 65536 memory locations. So, 8085 has 64K
memory locations.

Unit 3 – 8085 Microprocessor 21

Bus Organization of 8085
A15
Address Bus
A0

Memory Input

8085 MPU Output Real

World

D7
Data Bus
D0

Control Bus

Unit 3 – 8085 Microprocessor 22

Data bus
 Group of 8 lines identified as D0 to D7.
 They are bidirectional i.e. data flow in both
directions between microprocessor, memory &
peripheral.
 8 data lines enable microprocessor to
manipulate data ranging from 00 H to FF H
(28=256 numbers).
 Largest number appear on data bus is 1111
1111 => (255)10.
 As Data bus is of 8-bit, 8085 is known as 8-bit
Microprocessor.

Unit 3 – 8085 Microprocessor 23

Bus Organization of 8085
A15
Address Bus
A0

Memory Input

8085 MPU Output

D7
Data Bus
D0

Control Bus

Unit 3 – 8085 Microprocessor 24

Control bus
 It comprises of various single lines that carry synchronization, timing & control signals.
 These signals are used to identify a device type with which MPU intends to communicate.
 Some control signals are Read, Write and Opcode fetch etc.

Unit 3 – 8085 Microprocessor 25

8085 pin diagram
 • 8-bit general purpose
microprocessor.
Positive Vibes:MPI is the interesting, easiest and scoring subject.

• Capable of addressing 64K

of memory.
8085 pin diagram

• It has 40 pins.
• Requires +5V single power
supply.

Unit 3 – 8085 Microprocessor 27

8085 pin diagram
Signals are classified into 6 groups:
1. Address bus
2. Multiplexed address/data bus
3. Control & status signals
4. Power supply & frequency signals
5. Externally initiated signals
6. Serial I/O ports

Unit 3 – 8085 Microprocessor 28

8085 pin diagram: Address Bus
 16 signal lines are used as address bus.
 However these lines are split into two segments:
A15 - A8 and AD7 - AD0
 A15 - A8 are unidirectional and used to carry high-
order address of 16-bit address.
 AD7 - AD0 are used for dual purpose.

Unit 3 – 8085 Microprocessor 29

8085 pin diagram: Multiplexed Address/Data Bus
 Signal lines AD7-AD0 are bidirectional and serve
dual purpose.
 They are used as low-order address bus as well as
data bus.
 The low-order address bus can be separate from
these signals by using a latch (ALE).

Unit 3 – 8085 Microprocessor 30

8085 pin diagram: Control & Status Signals
To identify nature of operation
 Two Control Signals
1. RD(Read)
2. WR(Write)
 Three Status Signals
1. S1
2. S0
3. IO/M
 To indicate beginning of operation
1. ALE(Address Latch Enable)
ALE  1, then Address bus
ALE  0, then Data bus

Unit 3 – 8085 Microprocessor 31

8085 pin diagram: Control & Status Signals
ALE: Pin 30
 This is positive going pulse generated every time
the 8085 begins an operation (machine cycle).
 It indicates that the bits on AD7-AD0 are address
bits.
 This signal is used primarily to latch the low-
address from multiplexed bus & generate a
separate set of address lines A7-A0.

Unit 3 – 8085 Microprocessor 32

8085 pin diagram: Control & Status Signals
RD(Read): Pin 32
 This is a read control signal (active low)
 This signal indicates that the selected I/O or
Memory device is to be read & data is available on
data bus.

Unit 3 – 8085 Microprocessor 33

8085 pin diagram: Control & Status Signals
WR (Write): Pin 31
 This is a write control signal (active low)
 This signal indicates that the selected I/O or Memory
device is to be write & data is available on data bus.

Unit 3 – 8085 Microprocessor 34

8085 pin diagram: Control & Status Signals
IO/M: Pin 34
 This is a status signal used to differentiate I/O and
memory operation.
 When signal is
high → I/O operation
low → Memory operation
 This signal is combined with RD and WR to generate
I/O & memory control signals.

Unit 3 – 8085 Microprocessor 35

8085 pin diagram: Control & Status Signals
S1 (Pin 33) & S0 (Pin 29)
 These status signals can identify various
operations.

S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
1 1 OPCODE FETCH

Unit 3 – 8085 Microprocessor 36

8085 pin diagram

I0/M RD WR Operation
0 0 0 HLT
0 0 1 MEMR
0 1 0 MEMW
0 1 1 Opcode
Fetch
1 0 0 HLT
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP

Unit 3 – 8085 Microprocessor 37

8085 Pin Diagram: Power Supply & Frequency Signal
 Vcc → Pin 40, +5V Supply.
 Vss → Pin 20, Ground Reference

Unit 3 – 8085 Microprocessor 38

8085 Pin Diagram: Power Supply & Frequency Signal
 X1, X2 → Pin 1 & 2, Crystal Oscillator is connected
at these two pins.
 The frequency is internally divided by two;
therefore, to operate a system at 3MHz, the crystal
should have a frequency of 6MHz.

Unit 3 – 8085 Microprocessor 39

8085 Pin Diagram: Power Supply & Frequency Signal
 CLK (OUT) → Clock output
 Pin 37: This signal is used as system clock for
other I/O devices for synchronization with
Microprocessor.

Unit 3 – 8085 Microprocessor 40

8085 Pin Diagram: Externally Initiated Signals
 INTR(Input) → Interrupt Request
It is used for general purpose interrupt.
 INTA(Output) → Interrupt Acknowledge.

Unit 3 – 8085 Microprocessor 41

8085 Pin Diagram: Externally Initiated Signals
 RST7.5, RST6.5, RST5.5 (Input) → Restart
Interrupts.
 These are vector interrupts that transfer the
program control to specific memory locations.
 RST7.5, RST6.5, RST5.5 have higher priorities than
INTR interrupt.
 Among these 3 interrupts, the priority order (higher
to lower) is RST7.5, RST6.5, RST5.5 respectively.

Unit 3 – 8085 Microprocessor 42

8085 Pin Diagram: Externally Initiated Signals
 TRAP(Input) → This is a non maskable interrupt &
has the highest priority.

Unit 3 – 8085 Microprocessor 43

8085 Pin Diagram: Externally Initiated Signals
 HOLD(Input) → This signal indicates that a
peripheral such as DMA Controller is requesting the
use of address & data buses.
 HLDA(Output) → Hold Acknowledge. This signal
acknowledges the HOLD request.

Unit 3 – 8085 Microprocessor 44

8085 Pin Diagram: Externally Initiated Signals
 READY(Input) → This signal is used to delay the
microprocessor read or write cycles until low-
responding peripheral is ready to send or accept
data.
 When the signal goes low, the microprocessor
waits for an integral no. of clock cycles until READY
signal goes high.

Unit 3 – 8085 Microprocessor 45

8085 Pin Diagram: Externally Initiated Signals
 RESET IN (Input) → When the signal on this pin
goes low, the Program Counter is set to zero, the
buses are tri-stated & microprocessor is reset.
 RESET OUT (Output) → This signal indicates that
microprocessor is being reset. The signal is also
used to reset other devices.

Unit 3 – 8085 Microprocessor 46

8085 Pin Diagram: Serial I/O Ports
Two pins for serial transmission
1. SID (Serial Input Data)
2. SOD (Serial Output Data)
 In serial transmission, data bits are sent over a
single line, one bit at a time.

Unit 3 – 8085 Microprocessor 47

 X1 1 40 VCC
Sr. GTU Questions Marks Year
X2 2 39 HOLD
1. Draw and Explain the pin diagram of 8085 7 Win-2019 RESET OUT 3 38 HLDA
microprocessor. Positive Vibes:MPI is the interesting, easiest and scoring subject.
SOD 4 37 CLK (OUT)
2. What is the use of ALE pin in 8085? 1 Sum-2019
SID 5 36 RESET IN
3. Explain the following pins of the 8085 3 Win-2017
TRAP 6 35 READY
microprocessor: IO/M , INTR, RESETIN
RST7.5 7 34 IO/M
RST6.5 8 33 S1
RST5.5 9 32 RD
INTR 10 31 WR
8085A
INTA 11 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
AD3 15 26 A13
AD4 16 25 A12
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
VSS 20 21 A8
8085 Microprocessor signals GND
+5 V
Serial 5 1 2 40 20
SID 𝑋2 𝑉𝐶𝐶
I/O SOD 4 𝑋1 𝑉𝑆𝑆 28 Positive Vibes:MPI is the interesting, easiest and scoring subject.
Ports 𝐴15
High-Order Address
Bus
𝐴8
TRAP 6 21
Externally RST 7.5 7
Initiated RST 6.5 8
RST 5.5 9
Signals INTR 10
𝐴𝐷7 19
Multiplexed
READY 35 8085A Address/Data Bus
HOLD 39 𝐴𝐷0
12
External Signal RESET IN 36 30
Acknowledgement 29 ALE
INTA 11 𝑆0
33
38 𝑆1 Control and
HLDA 34
32 IO/M Status Signals
31 RD
WR

3 37
RESET CLK
OUT OUT
8085 Architecture/Block Diagram
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus Positive Vibes:MPI is the interesting, easiest and scoring subject.
8085 Block Diagram

Instruction
Accumulator (8) Temp. Reg. (8) Multiplexer
Reg. (8)
W (8) Z (8)
Temp. Reg. Temp. Reg.
Instruction B (8) C (8)
Decoder and Reg. Reg.
Flag (5) D (8) E (8)

Register Select
Machine
Flip-Flops Reg. Reg.
Cycle
Encoding H (8) L (8)
Reg. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
Power +5 V (ALU) (8) Program Counter (16)
Supply GND
Increment/Decrement
Address Latch (16)
X1 CLK
X2
Timing and Control Reset
GEN
Control Status DMA Address Buffer (8) Data/Address Buffer (8)

CLK RD WR S0 S1 IO/M HLDA RESET OUT

OUT ALE A15 - A8 AD7 – AD0
HOLD RESET IN Address
READY Address/Data
Bus Bus
 INTA RST6.5 TRAP
Used to holdINTR
data (i.e. temporary
RST5.5 RST7.5 SID SOD
• Used to store 8-bit data to perform arithmetic & logical operations.
data) during
• Result ALU operation.
of operation is stored
Interrupt in Accumulator. Serial I/O Control
Control

8-Bit Internal Data Bus Positive Vibes:MPI is the interesting, easiest and scoring subject.

Accumulator (8) Temp. Reg. (8)

Instruction When Instruction is fetched from
Multiplexer
Reg. (8)
memory, it Wis(8)
loaded in the
Z (8)
Instruction Registor
Temp. (IR).Reg.
Reg. Temp.
Instruction B (8)
C (8)
S ZReg.
AC
Reg.
P CY
Decoder and
Flag (5)
InstructionD decoder
(8) Edecodes
(8) the

Register Select
Machine
Flip-Flops Reg. Reg.
Cycle
information present
H (8) Lin(8)the
Encoding
InstructionReg.
register. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
(ALU) (8) Program Counter (16)
Increment/Decrement
Address Latch (16)
X1 CLK
Timing and Control Reset
GEN
• Performs
Control Computing
Status Functions.
DMA Address Buffer (8) Data/Address Buffer (8)
• Accumulator, Temporary Register
CLK RD WR S0 S1 HLDA RESET OUT
OUT
and Flag Registers
ALE
are part of ALU. A15 - A8 AD7 – AD0
HOLD RESET IN Address
READY Address/Data
Bus Bus
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD
A multiplexer pulls out the right group of bits,
Interrupt Control depending onI/O
Serial the instruction.
Control

8-Bit Internal Data Bus Positive Vibes:MPI is the interesting, easiest and scoring subject.

Instruction
Accumulator (8) Temp. Reg. (8) Multiplexer
Reg. (8)
W (8) Z (8)
• • Two
Eachadditional
register can 8-bit register,
hold which holds the
8-bit data. Temp. Reg. Temp. Reg.
• temporary data can
These registers during
workexecution
in pair toofhold
Instructionsome
16- B (8) C (8)
instructions.
bit data and their
Decoder Reg. Reg.
Flag pairing
(5) combination
and is like

Register Select
D (8) E (8)
• They are& used
B-C, D-E internally, so they
H-L. Flip-Flops Machineare not Reg. Reg.
available to the programmer. Cycle H (8) L (8)
It increments the program counter Encoding as Reg. Reg.
instructions
It execute,
is a 16-bit register works increments
Arithmetic like stack, which andis Stack Pointer (16)
16-bit registertheused
decrements stackto store
Logic pointer
Unit theas memory
needed, address
and
always incremented/decremented by 2 during
location
supports ofthe
the16-bit
next(ALU)
instruction
increment
(8) toand
be executed.
decrement
Program Counter (16)
push & pop operations. Increment/Decrement
instructions. Address Latch (16)
X1• The
CLK content stored in the SP and PC is
Timing and Control
loaded
GEN into
Control the Address
Status DMA Buffer and
Reset
Address Buffer Data/Address Buffer
Data/Address Buffer. (8) (8)
The memory
• CLK RD WR and SI/O0 S1chips HLDA
are connected
RESET OUT
A15 - A8 AD7 – AD0
toREADY
OUT these buses that can HOLD
ALE exchange the data.
RESET IN Address Address/Data
Bus Bus
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus Positive Vibes:MPI is the interesting, easiest and scoring subject.

Instruction
Accumulator (8) Temp. Reg. (8) Multiplexer
Reg. (8)
W (8) Z (8)
Temp. Reg. Temp. Reg.
Instruction B (8) C (8)
Decoder and Reg. Reg.
Flag (5) D (8) E (8)

Register Select
Machine
Flip-Flops Reg. Reg.
Cycle
Encoding H (8) L (8)
Reg. Reg.
This unit synchronizes all the microprocessor operations with
Arithmetic
the clock
Stack Pointer (16)
and generates control signal necessary for communication between
Logic Unit
Read/write
Input either
signal
microprocessor
Perform & to/from
(ALU) (8) memory
to synchronize
peripheral.
synchronization with or peripherals.
microprocessor
peripheral Program Counter (16)
Frequency Control Signals Address Latch Enable control signal
device. with peripheral device.
Shows read/write DMA status signal memory or Increment/Decrement
controlto/from I/O.
Address Latch (16)
X1 CLK
Timing and Control Reset Signal to RESET microprocessor and other
X2 GEN
Control Status DMA devices connected
Address Buffer (8) to it. Buffer (8)
Data/Address

CLK RD WR S0 S1 HLDA RESET OUT

OUT ALE A15 - A8 AD7 – AD0
HOLD RESET IN Address
READY Address/Data
Bus Bus
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus Positive Vibes:MPI is the interesting, easiest and scoring subject.

Instruction
Accumulator (8) Temp. Reg. (8) Multiplexer
Reg. (8)
W (8) Z (8)
Temp. Reg. Temp. Reg.
Instruction B (8) C (8)
Decoder and Reg. Reg.
Flag (5) D (8) E (8)

Register Select
Machine
Flip-Flops Reg. Reg.
Cycle
Encoding H (8) L (8)
Reg. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
(ALU) (8) Program Counter (16)
Increment/Decrement
Address Latch (16)
X1 CLK
X2
Timing and Control Reset
GEN
Control Status DMA Address Buffer (8) Data/Address Buffer (8)

CLK RD WR S0 S1 HLDA RESET OUT

OUT ALE A15 - A8 AD7 – AD0
HOLD RESET IN Address
READY Address/Data
Bus Bus
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus Positive Vibes:MPI is the interesting, easiest and scoring subject.

Accumulator (8) Temp. Reg. (8) It Instruction

controls
Reg. (8)
the serial data communication by
Multiplexer
using two instructions: W (8) Z (8)
• It controls the interrupts duringi. a process. Temp. Reg. Temp. Reg.
SID (Serial input data)
B (8) C (8)
• There are 5 interrupt signals inii.8085 microprocessor:
Instruction
SOD (Serial output data)
Reg. Reg.
Decoder and
TRAP, RST 7.5, RST 6.5, RST 5.5, INTR.
Flag (5) D (8) E (8)

Register Select
Machine
Flip-Flops Reg. Reg.
Cycle
Encoding H (8) L (8)
Reg. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
%
(ALU) (8) Program Counter (16)
Increment/Decrement
Address Latch (16)
X1 CLK
X2
Timing and Control Reset
GEN
Control Status DMA Address Buffer (8) Data/Address Buffer (8)

CLK RD WR S0 S1 HLDA RESET OUT

OUT ALE A15 - A8 AD7 – AD0
HOLD RESET IN Address
READY Address/Data
Bus Bus
 INTA RST6.5 TRAP
INTR RST5.5 RST7.5 SID SOD

Interrupt Control Serial I/O Control

8-Bit Internal Data Bus Positive Vibes:MPI is the interesting, easiest and scoring subject.

Instruction
Accumulator (8) Temp. Reg. (8) Multiplexer
Reg. (8)
W (8) Z (8)
Temp. Reg. Temp. Reg.
Instruction B (8) C (8)
Decoder and Reg. Reg.
Flag (5) D (8) E (8)

Register Select
Machine
Flip-Flops Reg. Reg.
Cycle
Encoding H (8) L (8)
Reg. Reg.
Arithmetic Stack Pointer (16)
Logic Unit
Power +5 V (ALU) (8) Program Counter (16)
Supply GND
Increment/Decrement
Address Latch (16)
X1 CLK
X2
Timing and Control Reset
GEN
Control Status DMA Address Buffer (8) Data/Address Buffer (8)

CLK RD WR S0 S1 HLDA RESET OUT

OUT ALE A15 - A8 AD7 – AD0
HOLD RESET IN Address
READY Address/Data
Bus Bus
GTU Exam Questions
Sr. GTU Questions Marks Year
1. Draw and explain the internal block diagram of 8085 microprocessor. 7 Sum-2019
Win-2018
Sum-2018

Unit 3 – 8085 Microprocessor 58

T-States, Machine and
Instruction Cycle
T-States, Machine and Instruction Cycle

T-States Operation performed in one clock period.

Time required by the microprocessor to complete

Machine Cycle an operation.

Time required to complete execution of an

Instruction Cycle instruction.

Unit 3 – 8085 Microprocessor 60

T-States
 “T-States are defined as operation performed in one clock period.”
 These sub-divisions are internal states synchronized with system clock & each T-state is
precisely equal to one clock period.

T-State-1 T-State-2 T-State-3 T-State-4

CLK

Clock Period

Unit 3 – 8085 Microprocessor 61

Machine Cycle
 “Machine Cycle is defined as time required by the microprocessor to complete an operation.“

 This cycle may consist 3 to 6 T-states. m/m Read

 The basic microprocessor operation such as reading a byte from I/O port or writing a byte to
memory.
Opcode Fetch Memory Read I/O Write
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3
CLK

Machine Machine Cycle-2 Machine Cycle-3

Cycle-1

Unit 3 – 8085 Microprocessor 62

Instruction Cycle
 “Instruction Cycle is defined as time required to complete execution of an instruction.”
 In 8085 microprocessor instruction cycle consists of 1 to 6 Machine Cycles or 1 to 6
operations.

Instruction Cycle
T1 T2 T3 T4

CLK

Fetch Cycle Execute Cycle

Unit 3 – 8085 Microprocessor 63

 T-States
Positive Vibes:MPI is the interesting, easiest and scoring subject.

Machine Cycle

Instruction Cycle
Demultiplexing Address and Data
Bus AD0-AD7
 Demultiplexing AD0-AD7
A15 0 A
0 A15
1Positive
14
A Vibes:MPIHigh-Order
is the interesting, easiest and scoring subject.
0 A13

8085 Microprocessor
0 A12 Address Bus
11
0 A
0 A10
A8 0 A9
8
ALE Enable G ALE=1
AD7 0 A7
0 A6 Address Bus
0 A5
0 A4 Low-Order
1 A3
0 A2 Address Bus
1 A1
AD0 1 A0

0 ALE= 0
1 D7 Data Bus
0 D 6
0 D5
1 D4 Data Bus
1 D3
1 D2
1 D1
D0
Demultiplexing AD0-AD7
 The dual-purpose of the AD0-AD7 pins is achieved through multiplexing.
 In simple words, multiplexing allows us to use the pins of a microprocessor for more than one
function.
 Advantage: Since each pin can serve multiple purposes, the total number of pins can be
reduced.
IC 74LS373
 IC 74LS373 is an IC with 20 pins.
 it is a memory unit to hold one bit of data.

IC 74LS373

Unit 3 – 8085 Microprocessor 67

GTU Questions
Sr. GTU Questions Marks Year
1. How will the multiplexed address/data bus (AD0-AD7) of the 8085 4 Win-2017
microprocessor be demultiplexed?

Unit 3 – 8085 Microprocessor 68

Timing Diagram
 Opcode Fetch
T1 T2 T3 T4
Positive Vibes:MPI is the interesting, easiest and scoring subject.
CLK

A15
Timing Diagram: Opcode Fetch

High order memory address Unspecified

A8
AD7 Low order
Opcode
AD0 M/m addr.

ALE

IO/M

RD

Unit 3 – 8085 Microprocessor 70

 Memory read cycle
T1 T2 T3 T4
Positive Vibes:MPI is the interesting, easiest and scoring subject.
CLK
Timing Diagram: Memory Read Cycle

A15
High order memory address
A8
AD7 Low order
Data from memory
AD0 M/m addr. S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
ALE

IO/M
S0 IO/M=0, S1=1 , S0=0

S1
RD

Unit 3 – 8085 Microprocessor 71

 Memory write cycle
T1 T2 T3 T4
Positive Vibes:MPI is the interesting, easiest and scoring subject.
CLK
Timing Diagram: Memory Write Cycle

A15
High order memory address
A8
AD7 Low order Data from
AD0 M/m addr. Microprocessor S1 S0 Mode
0 0 HLT
0 1 WRITE
1 0 READ
ALE

IO/M
S1 IO/M=0, S0=1 , S1=0
S0
WR

Unit 3 – 8085 Microprocessor 72

Memory Interfacing
Memory structure
Block diagram of Memory Device: RAM
N=Number of Register
Data Inputs M=Word Length
E.g.
WR If a memory is having
Input Buffer
CS address lines=13
A10

Internal Decoder
data lines=8
then
Address NXM 1. Number of memory locations =
Input Memory N=213 = 8192
2. Word length M= 8 bit
A0 Therefore, N X M= 8192 X 8
Output Buffer
RD

Data Output

Unit 3 – 8085 Microprocessor 74

Memory structure

No. of A Lines Memory size(bytes) No. of A Lines Memory size(bytes)

1 2 9 512
2 4 10 1024=1k
3 8 11 2048=2k
4 16 12 4096=4k
5 32 13 8192=8k
6 64 14 16384=16k
7 128 15 32768=32k
8 256 16 65536=64k

Unit 3 – 8085 Microprocessor 75

Memory Interfacing
 8085 can access 64K of memory, thus address bus is of 16-bit.
 It is not always necessary to use full 64K address space. The total memory size depends upon
the application.
 Generally EPROM is used as a program memory and RAM is used as data memory.
 When both are used then total 64K address will be shared by both.
 The capacity of program memory and data memory depends on the application.

Unit 3 – 8085 Microprocessor 76

Memory Interfacing
 It is not always necessary to select 1 EPROM and 1 RAM. We can have multiple EPROMs and
multiple RAMs as per the requirement of application.
 We can place EPROM / RAM anywhere in full 64 Kbytes address space.
 Program memory (EPROM) should be located from address 0000H, since reset address of 8085
microprocessor is 0000H.
 It is not always necessary to locate EPROM and RAM in consecutive memory addresses.

Unit 3 – 8085 Microprocessor 77

Memory Interfacing: Example 1
Interface 4kB of EPROM with starting address from 0000H and 2kB of RAM with starting address
followed by EPROM
Step-1: To calculate no. of EPROM and RAM chip required
Total EPROM required = 4kB
Chip size available = 4kB
No. of chips required = 4kB/4kB=1

Total RAM required = 2kB

Chip Size Available = 2kB
No. of Chips required = 2kB/2kB=1

Unit 3 – 8085 Microprocessor 78

Memory Interfacing: Example 1
Step-2: To calculate starting and ending address of EPROM
EPROM Chip-1:
Starting Address = 0000H
Chip Size = 4kB (i.e. address Line=12, m/m = 212 = 4096B = 4k)
Ending Address = 0FFFH
Step-3: To calculate starting and ending address of RAM
RAM Chip-1:
Starting address = Ending address of EPROM +1
= 0FFFH+1
= 1000H
Chip Size = 2kB = 07FFH
Ending address = 1000H+07FFH
= 17FFH

Unit 3 – 8085 Microprocessor 79

Memory Interfacing: Example 1
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
EPROM 0000 H
4k End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address
RAM 1000 H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
2k End
Address
0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1
17FF H
EPROM chip size = 4kB & RAM chip size = 2kB
smaller chip size RAM = 2kB = 211
Thus neglect lower 11 address lines (A0 to A10), and consider A11 to A15 for Decoding.

Unit 3 – 8085 Microprocessor 80

Memory Interfacing: Example 1
A A A A A A A A A A A A A A A A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 H
EPROM
End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

EPROM
• Required Address Lines: A11 to A15.
• Now, EPROM has two Possibilities, either 00000 b or 00001 b.
• Therefore, it requires Y0 and Y1 outputs of decoder.

Unit 3 – 8085 Microprocessor 81

Memory Interfacing: Example 1
A A A A A A A A A A A A A A A A
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 H
EPROM
End
Address
0FFF H 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
Start
Address
1000 H 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
RAM
End
Address
17FF H 0 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1

RAM has 00010 b, hence it requires Y2 output of decoder.

Unit 3 – 8085 Microprocessor 82

 Memory Interfacing: Example 1 Implementation
Step-5:
RD
IO/M Positive Vibes:MPI is the interesting, easiest and scoring subject.

A0 - A10
WR OE
RD

EPROM
D0
-
Y0 00000 D7
To EPROM
A15 Y1
00001
A14
Y2 To RAM D0 – D7 A0 - A10
A13 5:32 00010
Decoder
A12 OE RAM
A11

Unit 3 – 8085 Microprocessor 83

Memory Interfacing: Example 2
Interface 16kB of EPROM with chip size of 8kB and starting address from 0000H and 8kB of RAM
with starting address followed by EPROM.
Step-1: To calculate no. of EPROM and RAM chip required
Total EPROM required =16kB
Chip size available = 8kB
No. of chips required = 16kB/8kB = 2

Total RAM required = 8kB

Chip size available = 8kB
No. of chips required = 8kB/8kB = 1

Unit 3 – 8085 Microprocessor 84

Memory Interfacing: Example 2
Step-2: To calculate starting and ending address of EPROM
EPROM Chip-1:
Starting Address = 0000H
Chip Size = 8kB (i.e. address Line=13, m/m=213 =8192B =8k)
Ending Address = 1FFFH

EPROM Chip-2:
Starting Address =1FFFH + 1 = 2000H
Chip Size = 1FFFH
Ending Address = 2000+1FFFH = 3FFFH

Unit 3 – 8085 Microprocessor 85

Memory Interfacing: Example 2
Step-3: RAM Chip-1:
Starting Address = EPROM ending address + 1
Starting Address = 3FFFH+1 = 4000H
Chip Size = 8kB (i.e. address Line =13, m/m=213 = 8192B =8k)
Chip Size = 1FFFH
Ending Address = 4000h+1FFFH = 5FFFH

Unit 3 – 8085 Microprocessor 86

Memory Interfacing: Example 2
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 H
EPROM1
End
Address 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1FFF H
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2000 H
EPROM2
End
Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM
End
Address 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
5FFF H

Unit 3 – 8085 Microprocessor 87

Memory Interfacing: Example 2
Step-5:Interface Implementation
 EPROM chip size = RAM chip size = 8kB = 213
 Therefore, neglect lower 13 address lines (i.e. A0 to A12) and consider only A13 to A15 for
decoding.
EPROM CHIP-01 000
EPROM CHIP-02 001
RAM CHIP-01 010
Y0 To EPROM Chip-1
Y1 To EPROM Chip-2

A15 Y2 To RAM Chip-1

3:8
A14 Decoder
A13

Y7

Unit 3 – 8085 Microprocessor 88

Memory Interfacing: Example 2
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 H
EPROM1
End
Address 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1FFF H
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2000 H
EPROM2
End
Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM
End
Address 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
5FFF H

Unit 3 – 8085 Microprocessor 89

 Memory Interfacing: Example 2 Implementation
Step-5:
RD
A0 - A12
OE
IO/M Positive Vibes:MPI is the interesting, easiest and scoring subject.

EPROM
CHIP-1
WR D0
RD -
D7

D0 – D7 A0 - A12

Y0 000 To EPROM CHIP-1 OE

EPROM
Y1 001 To EPROM CHIP-2 CHIP-2
A15
Y2 010 To RAM
A14 3:8
Decoder
A13
D0 – D7 A0 - A12

OE RAM
Exercise: Memory Interface Example
1. Draw the interfacing of a 4KB EPROM having a starting address 2000h and two 2KB static
RAMs having starting addresses 4000h and 8000h, respectively, with 8085 microprocessor.
2. Design an 8085 microprocessor system such that it should contain 16KB of EPROM and 4KB
of RAM with starting addresses 0000H and 4000H respectively. Use two 8KB of EPROMs
(2764) and two 2KB of RAMs (6116) for this system.

Unit 3 – 8085 Microprocessor 91

Exercise: Example 1
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2000 H
EPROM1
End
Address 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1
2FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM 1
End
Address 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1
47FF H
Start
Address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8000 H
RAM 2
End
Address 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1
87FF H

Unit 3 – 8085 Microprocessor 92

 Exercise: Example 1
Step-5:
RD
A0 - A12
OE
IO/M Positive Vibes:MPI is the interesting, easiest and scoring subject.

EPROM
CHIP
WR D0
RD -
D7

D0 – D7 A0 - A12

Y0 00100 OE
To EPROM
Y1 RAM-1
00101
A15
Y2 To RAM-1
A14 5:32 01000
A13 Decoder
Y3 To RAM-2
A12 10000
D0 – D7 A0 - A12
A11
OE RAM-2
Exercise: Example 2
Step-4: Memory A A A A A A A A A A A A A A A A
Map 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Start Positive Vibes:MPI is the interesting, easiest and scoring subject.
Address 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0000 H
EPROM1 End
Address 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1FFF H
Start
Address 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
2000 H
EPROM2 End
Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
3FFF H
Start
Address 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4000 H
RAM 1 End
Address 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1
47FF H
Start
Address 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
4800 H
RAM 2 End
Address 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1
4FFF H
 Exercise: Example 2
Step-5: A0 - A10
RD OE

IO/M EPROM-1
D0 Vibes:MPI is the interesting, easiest and scoring subject.
Positive
-
D7
WR
RD A0 - A10
OE

D0 EPROM-2
-
D7

Y0 00011
EPROM-1
Y 00100
1
D0 – D7 A0 - A10

A15 OE
RAM-1
A14 5:32 EPROM-2
Y2 00101
A13 Decoder
A12 Y3 01000 To RAM-1
A11
A0 - A10
Y4 10000 To RAM-2
D0 – D7

OE RAM-2
Generating Control Signals
Generating Control Signals
I0/M RD WR Operation
0 0 0 Invalid
0 0 1 MEMR

IO/M 0
MEMR
RD 0
8085
WR 1

Unit 3 – 8085 Microprocessor 97

Generating Control Signals
I0/M RD WR Operation

0 0 0 Invalid
0 0 1 MEMR
0 1 0 MEMW

IO/M 0
MEMR
RD 1
8085
WR 0 MEMW

Unit 3 – 8085 Microprocessor 98

Generating Control Signals
I0/M RD WR Operation

0 0 0 Invalid
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP

IO/M 0
MEMR
RD 1
8085
WR 1 MEMW

Unit 3 – 8085 Microprocessor 99

Generating Control Signals
I0/M RD WR Operation

0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 0 Invalid

IO/M 1
MEMR
RD 0
8085
WR 0 MEMW

Unit 3 – 8085 Microprocessor 100

Generating Control Signals
I0/M RD WR Operation

0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR

IO/M 1
MEMR
RD 0
8085
WR 1 MEMW

IOR

Unit 3 – 8085 Microprocessor 101

Generating Control Signals
I0/M RD WR Operation

0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
1 1 0 IOW

IO/M 1
MEMR
RD 1
8085
WR 0 MEMW

IOR

IOW

Unit 3 – 8085 Microprocessor 102

Generating Control Signals
I0/M RD WR Operation

0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP
IO/M 1
MEMR
RD 1
8085
WR 1 MEMW

IOR

IOW

Unit 3 – 8085 Microprocessor 103

Generating Control Signals

I0/M RD WR Operation

0 0 0 HLT
0 0 1 MEMR
0 1 0 MEMW
0 1 1 NOP
1 0 0 HLT
1 0 1 IOR
1 1 0 IOW
1 1 1 NOP

Unit 3 – 8085 Microprocessor 104

GTU Exam Questions
Sr. GTU Questions
1. How will the multiplexed address/data bus (AD0-AD7) of the 8085 microprocessor be demultiplexed?
2. Explain the flag register of the 8085 microprocessor with examples.
3. Draw the interfacing of a 4KB EPROM having a starting address 2000h and two 2KB static RAMs having starting
addresses 4000h and 8000h, respectively, with 8085 microprocessor. Use demultiplexed address/data lines and use 3-to-
8 decoder (74LS138).
4. Draw and explain the internal block diagram of 8085 microprocessor.
5. List the sequence of events that occurs when the 8085 MPU reads from memory.
6. Explain 8085 Programming Model and Flag Register.
7. Discuss the programming model of 8085 μP with the help of suitable diagram.
8. Draw and Explain the pin diagram of 8085 microprocessor.

Unit 3 – 8085 Microprocessor 105

References
Book: Microprocessor Architecture, Programming, and Applications with the 8085, Ramesh S.
Gaonkar Pub: Penram International

Unit 3 – 8085 Microprocessor 106

Thank You