1 2 3 4

A A

OPS
OpAmpSupply.SchDoc
V_USB 9V

AUDIO_+SUPPLY_EN
ONS
OpAmpNegativeSupply.SchDoc
MCU
V_USB -9V
MCU.SchDoc
AUDIO_+SUPPLY_EN INVERTING_SUPPLY_SWITCH
INVERTING_SUPPLY_SWITCH
-9V
CDC OUB
CODEC.SchDoc OutputBuffer.SchDoc
PCM3060 DAC DIN PCM3060 DAC DIN PCM3060 VOUT L+ BUFFER INPUT L+
PCM3060 DAC LRCK PCM3060 DAC LRCK PCM3060 VOUT L- BUFFER INPUT L-
B ICN B
PCM3060 DAC BCK PCM3060 DAC BCK
InputConnectors.SchDoc
PCM3060 VOUT R+ BUFFER INPUT R+
POL
D+ D+ PCM3060 DAC SCKI PCM3060 DAC SCKI PCM3060 VOUT R- BUFFER INPUT R-
PowerAmplifier.SchDoc
D- D-
9V 9V
V_USB PCM3060 SCL PCM3060 SCL -9V -9V
PCM3060 SDA PCM3060 SDA
BUFFER OUTPUT L POWER_AMP_INPUT
MCH
PCM3060 RESET PCM3060 RESET
Mechanical.SchDoc OCN
OutputConnectors.SchDoc
3V3 3V3
4V6 POWER_AMP_OUTPUT AUDIO_OUTPUT_LEFT
REG
Regulators.SchDoc POR
PowerAmplifier.SchDoc
V_USB 3V3
9V
4V6 -9V

BUFFER OUTPUT R POWER_AMP_INPUT

C C
POWER_AMP_OUTPUT AUDIO_OUTPUT_RIGHT

This source describes Open Hardware and is licensed under

the CERN-OHL-S v2.

You may redistribute and modify this source and make

products using it under the terms of the CERN-OHL-S v2
(https://ohwr.org/cernohlsv2.txt). This source is distributed
WITHOUT ANY EXPRESS OR IMPLIED WARRANTY,
INCLUDING OF MERCHANTABILITY, SATISFACTORY
QUALITY AND FITNESS FOR A PARTICULAR PURPOSE.

Please see the CERN-OHL-S v2 for applicable conditions.

Source location: https://github.com/ploopyco/

As per CERN-OHL-S v2 section 4, should You produce

hardware based on this source, You must where practicable
D maintain the Source Location visible on the external case of D
the products you make using this source.

Copyright Ploopy Corporation 2022 Title: Gould.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:48 AM Sheet 1 of 12 Canada

1 2 3 4
 1 2 3 4

There's not really a good recommendation for what t o

do with the ADC inputs if you're not going to use them.
The safest bet is probably to have a low-impedance
source driving them to VCOM, but this costs money and
A is therefore stupid if there's a more efficient solutio n A
available.

The abs. max range for these inputs is -0.3V to VCCish,

so we could ground them without damaging the device.
The ADC *should* read as the minimum possible value
in this case, but since we never use it, that should be a The ADC on the PCM3060 is not used in this
moot point. And the signal won't wiggle, so that's application, so it is silly to connect the ADC digital
probably good, too. interface pins. However, the disposition of the pins
must still be considered. To wit:
COU10
CDC.U.10
DOUT: this pin is driven by the PCM3060, so we leave
25 7 3V3 PO3V3
PICDC0U010025 VIN L VDD PICDC0U01007 3V3 it floating.
PICD0C250 PICD0 352 LRCK1/BCK1: Both pins have an internal 50k
COC25
CDC.C.25 COC35
CDC.C.35
pulldown, so we can safely leave these floating.
26
PICDC0U010026
VIN R
PICD0C2501 0805 X5R PICD0 351 0805 X5R
However, we have a 1k resistor available because o f
GND 8 0.1uF 100V 10uF 25V
DGND PICDC0U01008
the I2C pins, so we use that to ground them both.
SCKI1: This is a floating (presumably hi-z) input, so we
ground it to make sure we're not randomly clocking
NL4V6
4V6 24 GND
PO4V6
4V6 PICDC0U010024
VCC the ADC interface.
PICD0C3602 COC36
PICD0 372 COC37
CDC.C.36 CDC.C.37 3
B DOUT PICDC0U01003 B
PICD0C3601 0805 X5R PICD0 371 0805 X5R
LRCK1
4
PICDC0U01004
10uF 25V 0.1uF 100V 5
BCK1 PICDC0U01005
23
PICDC0U010023
AGND1
PICD0Ra1 PICD0Ra102
16 6 COCDC0Ra01A
COCDC0Ra01B
COCDC0Ra01C
COCDC0Ra01D
CDC.Ra.1A CDC.Ra.1B
PICDC0U010016 SGND SCKI1 PICDC0U01006 1206 Quad 1206 Quad
22
PICDC0U010022
AGND2
PICD0C3802 PICD0 392 PICD0Ra18 1k 1% PICD0Ra107 1k 1%
COC38
CDC.C.38 COC39
CDC.C.39
GND PICD0C3801 0805 X5R PICD0 391 0805 X5R GND
10uF 25V 0.1uF 100V GND GND
21 12
Because we're not using the analo g PICDC0U010021 VCOM DIN PICDC0U010012 PCM3060 DAC DAC
POPCM3060 DIN DIN
11
input functionality of the PCM3060, LRCK2 PCM3060 DACDAC
PICDC0U010011POPCM3060 LRCK LRCK
10
the VCOM pin is not used to bias any BCK2 PCM3060 DAC DAC
PICDC0U010010POPCM3060 BCK BCK
external circuitry. The bypass caps
9
mounted here are to stabilize the SCKI2 PICDC0U01009 SCKI SCKI
PCM3060 DACDAC
POPCM3060
POPCM3060 L0 20
value of this voltage, since it is used PCM3060 VOUTVOUT
L+ PICDC0U010020
VOUT L+
internally to the IC.
19
PCM3060 VOUTVOUT
POPCM3060 L- L0 PICDC0U010019
VOUT L-
18 15
PCM3060 VOUTVOUT
POPCM3060 R+ R0 PICDC0U010018
VOUT R+ RST PICDC0U010015
POPCM3060 R\E\S\E\T\
PCM3060 RESET
17 28
C PCM3060 VOUTVOUT
POPCM3060 R- R0 PICDC0U010017 VOUT R- MODE PICDC0U010028 C
27
MS/ADR/IFMD PICDC0U010027
13 1 POPCM3060 SCL
PICDC0U010013 ZEROR MC/SCL/FMT PICDC0U01001 PCM3060 SCL
14 2 GND
PICDC0U010014 ZEROL MD/SDA/DEMP PICDC0U01002 POPCM3060 SDA
PCM3060 SDA
PCM3060

The ZERO flags are outputs that indicat e

PICD0Ra104 PICD0Ra13 Connecting the MODE pin to DGND set s
CDC.Ra.1D CDC.Ra.1C
to external things like mute circuits that the PCM3060 to I2C mode. Connecting
1206 Quad 1206 Quad
there is nothing coming out on the DAC MODE to VDD would set it to SPI mode.
(lots of consecutive zeroes). This
PICD0Ra105 1k 1% PICD0Ra16 1k 1%
NL3V3
3V3
functionality doesn't really serve any In I2C mode, the ADR pin sets the LSB o f
purpose in this application, so we leave the peripheral I2C address. In this case we
these pins floating since they're driven. ground it, so the peripheral address is
b100 0110.

D D

Copyright Ploopy Corporation 2022 Title: CODEC.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:48 AM Sheet 2 of 12 Canada

1 2 3 4
 1 2 3 4

A A

COTP12
ICN.TP.12
COJ2
ICN.J.2
1
GND PIICN0J0201

VBUS
2
PIICN0J0202
PICN0TP120 PIICN0FB0301
COFB3
ICN.FB.3
PIICN0FB0302
POV0USB
V_USB
3 ACML-0805-601-T
CC1 PIICN0J0203

B 4 B
SBU2 PIICN0J0204

5 COFB4
ICN.FB.4
D- PIICN0J0205 PIICN0FB0401 PIICN0FB0402 POD0
D-
6 ACML-0805-601-T
D+ PIICN0J0206
COFB5
7 ICN.FB.5 POD0
D+ PIICN0J0207 PIICN0FB0501 PIICN0FB0502 D+
8 ACML-0805-601-T
D- PIICN0J0208
PICN0TP301
9
CC2 PIICN0J0209

SBU1
10
PIICN0J02010
PICN0TP1
VBUS
11
PIICN0J02011
PICN0R1402 PICN0R152 PICN0R1602 PICN0R172
COR14
ICN.R.14 COR15 COR16
ICN.R.16 COR17
ICN.R.15 ICN.R.17
PICN0Z16 PICN0Z15 PICN0Z14

4
5
12 0805 0805 0805 0805 COTP3
ICN.TP.3
GND PIICN0J02012
PICN0R140 10k 1% PICN0R15 10k 1% PICN0R160 10k 1% PICN0R17 10k 1%
COTP1
ICN.TP.1
SHELL PIICN0J020SHELL

DX07S016JA1R1500 GND GND

To properly identify this device when

COZ1
ICN.Z.1
connecting to a fully functional USB3.0
upstream device, the CC pins must be PICN0Z1 PICN0Z12 PICN0Z13 IP4220CZ6,125

2
C C

3
pulled down with a "5.1k" resistor.
GND
Here, 5k will do to simplify the BoM.

GND

D D

Copyright Ploopy Corporation 2022 Title: InputConnectors.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:49 AM Sheet 3 of 12 Canada

1 2 3 4
 1 2 3 4

A A

Pick and Place Fiducials Spark Gaps -- Case

COFID1
MCH.FID.1 COFID2
MCH.FID.2 Since the case has gaps in it, we expect ESD to worm its way in via
creepage and perhaps other ways. To protect the board from this
eventuality, we place spark gaps along the edges.
IPC-7351 Fiducial 1mm IPC-7351 Fiducial 1mm
B B
COSP1
MCH.SP.1 COSP2 COSP3
MCH.SP.2 MCH.SP.3
COSP4
MCH.SP.4 COSP5
MCH.SP.5 COSP6 MCH.SP.6
COSP7
MCH.SP.7 COSP8 COSP9
MCH.SP.8 MCH.SP.9
COSP10 COSP11
MCH.SP.10 MCH.SP.11 COSP12
MCH.SP.12

PIMCH0SP10 PIMCH0SP401 PIMCH0SP10 PIMCH0SP71 PIMCH0SP21 PIMCH0SP501 PIMCH0SP10 PIMCH0SP801 PIMCH0SP301 PIMCH0SP601 PIMCH0SP120 PIMCH0SP901
COLOGO1
MCH.LOGO.1
GND

Ploopy

Ploopy logo, silkscreen

C C

D D

Copyright Ploopy Corporation 2022 Title: Mechanical.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:49 AM Sheet 4 of 12 Canada

1 2 3 4
 1 2 3 4 5 6

The SCKI nets have to be connected to one of the

GPOUT<n> pins on the RP2040. These are GPIO21,23,24,25.

Only one of the two outputs has to actually send a clock over
to the PCM3060, which can operate from one clock pin.

I2C pins are connected to every GPIO pin! SCL is connected

to odd GPIO pin numbers and SDA is connected to even
ones. Make sure you connect both pins to the SAME I2C port
though (there are 2)!
A A
PIO pins are mappable to all GPIO pins, so it doesn't matter
where the I2S lines are hooked up.

Pins adjacent to I2S lines are grounded for signal integrity,

since these signals go quite quickly. Unused pins are also
grounded and should be set to output LOW to improve This header can be pinched with tweezers or otherwise
grounding. shorted during startup to force the RP2040 into USB
bootloader mode. To do this, short the header while the
board is unpowered, and then plug a USB cable in. If COJ4
MCU.J.4 3V3
successful, the computer the RP2040 is attached to COR9
MCU.R.9 COR10
MCU.R.10
2
should detect a USB mass storage device that you can - PIMCU0J0402 PIMCU0R0901 PIMCU0R0902 PIMCU0R01002 PIMCU0R01001

then drag and drop a new firmware file onto. Very cool! 0805 0805
1 1k 1% 10k 1%
+ PIMCU0J0401
This flash chip holds all of the program memory. The chosen
component is a 16MB chip, but smaller ones from the same
HEADER2
COU11 series could be substituted in to reduce cost (there's about a
GND MCU.U.11
CAD$1 difference to be had).
COU12
MCU.U.12 1 8 3V3
PIMCU0U01101 CS VCC PIMCU0U01108

POPCM3060
PCM3060 SDA SDA 2
PIMCU0U01202
GPIO0 QSPI_SS_N
56
PIMCU0U012056 PIMCU0U011066
CLK
PIMCU0 402 The nCS pin is tied high to ensure that the MCU normally
3 52 COC40
MCU.C.40
POPCM3060
PCM3060 SCL SCLPIMCU0U01203 GPIO1 QSPI_SCLK PIMCU0U012052 boots off whatever is in flash. If you'd rather boot from USB,
4
PIMCU0U01204
GPIO2 QSPI_SD0
53
PIMCU0U012053 5
PIMCU0U01105
DI (IO0)
PIMCU0 401 0805 X5R
ground the nCS pin via the provided header and then reset
5 55 2 0.1uF 100V
This circuit translates the negative PIMCU0U01205
GPIO3 QSPI_SD1 PIMCU0U012055 PIMCU0U01102
DO (IO1) the MCU using the RUN pin.
6 54 3
output voltage of the -9V inverting PIMCU0U01206
GPIO4 QSPI_SD2 PIMCU0U012054 PIMCU0U01103
WP (IO2)
7 51 7 4
charge pump into a positive voltage PIMCU0U01207
GPIO5 QSPI_SD3 PIMCU0U012051 PIMCU0U01107
HOLD or RESET (IO3) GND PIMCU0U01104
8 GND
that the MCU can read. Since the PIMCU0U01208 GPIO6
9 W25Q16JVSSIQ
MCU outputs the PWM signal that PIMCU0U01209
GPIO7 COR11
MCU.R.11
47 POD0
controls the converter, reading this USB_DP PIMCU0U012047 PIMCU0R01101 PIMCU0R01102 D+
11 46 0805
B voltage allows for (in principle) closed PCM3060 DAC BCK DAC BCKPIMCU0U012011
POPCM3060 GPIO8 USB_DM PIMCU0U012046
B
POPCM3060 12
DAC LRCKPIMCU0U012012 22R 1%
loop control over the voltage if PCM3060 DAC LRCK GPIO9
13
necessary, and a safety cut-off in case PIMCU0U012013 GPIO10 COR12
MCU.R.12
14 48 3V3
of overvoltage. PIMCU0U012014
15
GPIO11 USB_VDD PIMCU0U012048
PO3V3
3V3 PIMCU0R01201 PIMCU0R01202
POD0
D-
PCM3060 DAC DIN DAC DINPIMCU0U012015
POPCM3060 GPIO12 0805
16 22R 1%
NL3V3
PIMCU0U012016
GPIO13
3V3 POPCM3060 17 44
PCM3060 RESETR\E\S\E\T\PIMCU0U012017 GPIO14 VREG_VIN PIMCU0U012044
18
PIMCU0U012018 GPIO15
PIMCU0 4102
PIMCU0Ra201 COC41
MCU.C.41
COMCU0Ra02A
COMCU0Ra02B
COMCU0Ra02C
COMCU0Ra02D
MCU.Ra.2A 27 PIMCU0U012027 GPIO16 IO VDD
1
PIMCU0U01201
PIMCU0 410 0805 X5R
1206 Quad
POINVERTING0SUPPLY0SWITCH
INVERTING_SUPPLY_SWITCH
28 PIMCU0U012028
GPIO17
PIMCU0 420 1uF 25V
PIMCU0Ra208 10k 1% 29 10 COC42
MCU.C.42
COR27
MCU.R.27 MCU.Ra.2B PIMCU0U012029
GPIO18 IO VDD PIMCU0U012010
PIMCU0 4302 PIMCU0 4201 0805 X5R
PO09V POPCM3060 DAC SCKI 30 GND
-9V PIMCU0R02701 PIMCU0R02702 PIMCU0Ra0207 PIMCU0Ra0202
PCM3060 DAC SCKI PIMCU0U012030
GPIO19 COC43
MCU.C.43 0.1uF 100V
0805 1206 Quad 31
PIMCU0U012031
GPIO20
100k 1% PIMCU0Ra206 10k 1% 32
PIMCU0U012032 GPIO21 IO VDD
22
PIMCU0U012022
PIMCU0 4301 0805 X5R
MCU.Ra.2C
POAUDIO00SUPPLY0EN
AUDIO_+SUPPLY_EN
34
PIMCU0U012034
GPIO22
PIMCU0 402 0.1uF 100V GND
1206 Quad 35 33 COC44
MCU.C.44
PIMCU0U012035 GPIO23 IO VDD PIMCU0U012033
PIMCU0Ra203 10k 1% PIMCU0 4502 PIMCU0 401 0805 X5R GND
36 COC45
MCU.C.45 0.1uF 100V
PIMCU0U012036 GPIO24
PIMCU0Ra204 37
PIMCU0U012037 GPIO25 IO VDD
42
PIMCU0U012042
PIMCU0 4501 0805 X5R
MCU.Ra.2D 0.1uF 100V GND
1206 Quad 38 49
PIMCU0U012038 GPIO26/ADC0 IO VDD PIMCU0U012049
PIMCU0Ra205 10k 1% 39
PIMCU0U012039
GPIO27/ADC1
PIMCU0 4702 GND
40 COC47
MCU.C.47
PIMCU0U012040 GPIO28/ADC2
41
PIMCU0U012041 GPIO29/ADC3 ADC_AVDD
43
PIMCU0U012043
PIMCU0 4802 PIMCU0 4701 0805 X5R
COC48
MCU.C.48 0.1uF 100V
GND PIMCU0 4801 0805 X5R
COC49
MCU.C.49 0603 GND 0.1uF 100V GND
C 18pF 50V 20 C
PIMCU0C04902 PIMCU0C04901 PIMCU0U012020 XIN
PIMCU0Y0104 PIMCU0Y1 COY1
MCU.Y.1
RH100-12.000-16-3030 45 1V1
NL1V1
GND
PIMCU0Y0102 12MHz VREG_VOUT PIMCU0U012045
COC50
MCU.C.50 PIMCU0 5102 The digital core voltage is 1.1V, and it
PIMCU0C05001 PIMCU0C05002 0603 PIMCU0Y103 PIMCU0R01302
COR13
MCU.R.13
PIMCU0R01301 21
PIMCU0U012021
XOUT
COC51
MCU.C.51
is generated by an on-chip linear
18pF 50V 0805
D VDD
23
PIMCU0U012023
PIMCU0 510 0805 X5R
regulator that outputs at
1k 1% PIMCU0 520 1uF 25V
VREG_VOUT.
19 COC52
MCU.C.52
PIMCU0U012019 TESTEN
GND 26
PIMCU0U012026 RUN D VDD
50
PIMCU0U012050
PIMCU0 5201 0805 X5R GND
The regulator requires a 1uF cap for
PIMCU0 5302 0.1uF 100V
stability at VREG_VIN and
GND 24 COC53
MCU.C.53
PIMCU0U012024 SW CLK VREG_VOUT, and 0.1uF caps are
25
PIMCU0U012025
SWD IO GND (PAD)
57
PIMCU0U012057
PIMCU0 5301 0805 X5R GND
added for each digital VDD pin for
3V3 0.1uF 100V
stability.
RP2040
The RUN pin is the RP2040s
PIMCU0R180 GND
COR18
MCU.R.18 GND
external reset pin; pull it low 0805
to reset the part, using the
provided header. PIMCU0R1802 1k 1%
PIMCU0TP501
PIMCU0TP601
PIMCU0TP701 COTP5
MCU.TP.5

COTP6
MCU.TP.6
This header provides access to the
SWD pins, just in case we need to do
D some hardcore debugging and/or D
COTP7
MCU.TP.7
have to rescue the chip.

Copyright Ploopy Corporation 2022 Title: MCU.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl
PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:49 AM Sheet 5 of 12 Canada

1 2 3 4 5 6
 1 2 3 4

A A

COTP13
OCN.TP.13

PIOCN0TP130

GND

B
Headphone Output B
COJ3
OCN.J.3 COTP14
OCN.TP.14
1
PIOCN0J0301
Sleeve/GND
4
PIOCN0J0304
Ring 2/GND
3
PIOCN0J0303
Ring 1/Right Channel PIOCN0TP140 POAUDIO0OUTPUT0RIGHT
AUDIO_OUTPUT_RIGHT

2 Tip/Left Channel POAUDIO0OUTPUT0LEFT

PIOCN0J0302
AUDIO_OUTPUT_LEFT
PIOCN0TP150
SJ-43514-SMT-TR

Since there's a relatively simple way of splitting 3.5mm audio

cables, there's only a single jack here. This makes a few other
things simpler: you could use this amp on other headphones ,
COTP15
OCN.TP.15 PIOCN0D2 PIOCN0D21 COD2
OCN.D.2

1
S23CC12
for instance. It also makes it so that the cables can be plugged
in both ways without having to worry that the wrong channel
will come out of the headphones. Since the output signals are bidirectional, we
need a similarly bi-directional TVS protectio n
And for those of you thinking bUt ThAtS nOt BaLaNcEd Y o U
PIOCN0D23 scheme. This part conveniently provides that

3
nEeD 2 cOnNeCtOrs, I recommend 6.002 for your edification, in a low-capacitance package.
which you can find here:
C https://ocw.mit.edu/courses/6-002-circuits-and-electronics-spr Turns out that a reverse breakdown level of at C
ing-2007/ least 9V is required, but 12V is most common.
GND
Still plenty of headroom, since the OPA1688
abs max is +/- 20V.

D D

Copyright Ploopy Corporation 2022 Title: OutputConnectors.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:49 AM Sheet 6 of 12 Canada

1 2 3 4
 1 2 3 4

A A

Finding small 16V rated electrolytics is kind of tricky.

There is ONE part that packs 220uF into a tiny 6.3mm
dia. x 6mm tall package, and it's listed below.

If you can't find this part, you can opt to use two 150uF
This circuit was prototyped using 20uF of coupling or 100uF caps in this package size instead, since they'r e
Independently, 2x 10uF caps for capacitance (2x 10uF) and 60uF of bypas s common. The R1.006 board was tested using 1x 220uF
input bypass may not be capacitance (6x 10uF). So, we leave these values cap, so this arrangement should work fine.
enough. But this circuit is laid as-is, since they seem to work well.
out beside the boost converter , EEV107M016S9GAA is a good choice.
which has some additional input COTP16
ONS.TP.16
capacitance, so they can share. COC64
ONS.C.64
COC6
ONS.C.6 UCM1C221MCL1GS
COL2
ONS.L.2 PIONS0C0602 PIONS0C0601
220uF
NRS8040T100MJGJ COD3
ONS.D.3 16V
POV0USB
V_USB PIONS0L0201 PIONS0L0202
0805 X5R PIONS0D0301 PIONS0D0302
PIONS0TP160 PO09V
-9V
10uF 25V
PIONS0C802 COC8
PIONS0C102 COC11
COC7
ONS.C.7 SSA210
B
ONS.C.8 ONS.C.11 PIONS0C0702 PIONS0C0701
PIONS0C120 PIONS0C160 PIONS0C170 PIONS0C180 PIONS0C6201 PIONS0C6301 PIONS0C6402 PIONS0C102 B
PIONS0C801 0805 X5R PIONS0C10 0805 X5R COC12
ONS.C.12 COC16
ONS.C.16 ONS.C.17 COC17 COC18
ONS.C.18 ONS.C.62 COC62 COC63
ONS.C.63 COC10
ONS.C.10
10uF 25V 10uF 25V 0805 X5R PIONS0C120 PIONS0C1602 0805 X5R PIONS0C1702 0805 X5R PIONS0C1802 0805 X5R PIONS0C620 0805 X5R PIONS0C6302 0805 X5R
0805 X5R PIONS0C6401 PIONS0C10 UCM1C221MCL1GS
10uF 25V COD4
ONS.D.4 10uF 25V 10uF 25V 10uF 25V 10uF 25V 10uF 25V 10uF 25V 220uF
GND GND PIONS0D0402 PIONS0D0401 16V

SSA210
A massive output capacitance on the negative rail
GND
minimizes voltage ripple in the absence of active
regulation. Since we care less about the actual D C
PIONS0Q10D COQ1 voltage and more about ripple, this works out
ONS.Q.1
POINVERTING0SUPPLY0SWITCH
INVERTING_SUPPLY_SWITCH PIONS0Q010G
CSD16301Q2 nicely.
PIONS0Q10S Lots of 10uF placement slots are provided here, in
In the test version of this circuit, a the hopes that it might be possible to run this
square wave from the RP2040 with a
PIONS0R290 design without adding a massive electrolytic cap.
COR29
ONS.R.29
700ns period (400ns on, 300ns o f f )
0805
generated a set of output voltages
that worked across the required
PIONS0R2901 10k 1%
regulation range. Go with that unles s
a reason not to presents itself.
C C
GND

This circuit is pretty freaking weird. It's kind of an unregulated boost converter grafted onto a charge pump.

The FET/inductor combo produce a square-ish voltage that's some factor larger than V_USB when the FET is pulsed.
The exact voltage is dependent on the timing of the FET activity, but is generally 2-5x V_USB. This waveform get s
fed into an inverting charge pump, which turns it into a negative voltage that's somewhat less than the peak bo o s t
voltage.

Closed loop controllers for this topology are pretty hard to find, particularly right now (as of this writing, pretty much
everything is hard to find reliably). So, we rely on two things: the op amps this circuit powers can run between -8V
and -18V (a very large range) and they have a minimum PSRR of about -55dB. That means we can run this circuit
D pretty much unregulated as long as it produces between -18V and -8V between -35mA (the minimum quiescent D
current of the analog stages of the circuit) and -700mA (the maximum expected current draw at ear-splittingly loud
volumes).

The good news is that it does. The even better news is that we could measure the output voltage on the RP2040
and either achieve closed-loop regulation or at the very least a safety shutdown if a negative overvoltage is Copyright Ploopy Corporation 2022 Title: OpAmpNegativeSupply.SchDoc Ploopy Corporation
detected. :D Details on how this works can be found in the source code running on the RP2040. 137-1140 Burnhamthorpe Road W
Licensed under the CERN-OHL-S v2
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:49 AM Sheet 7 of 12 Canada

1 2 3 4
 1 2 3 4

A A

The datasheet for the LM2735 COTP17

OPS.TP.17
recommends 10uF to 44uF of
input capacitance.
B B
COL1
OPS.L.1
NRS8040T100MJGJ COD5
OPS.D.5
POV0USB
V_USB PIOPS0L0101 PIOPS0L0102 PIOPS0D0502 PIOPS0D0501
PIOS0TP170 PO9V
9V
PIOPS0C 3402 PIOS0C1302 PIOS0C1902 PIOS0C1402 PIOS0C20 PIOS0C210 PIOS0C20 PIOS0C230
COC34
OPS.C.34 COC13
OPS.C.13 COC19
OPS.C.19 COC14
OPS.C.14 SSA210 COC20
OPS.C.20 COC21
OPS.C.21 COC22
OPS.C.22 COC23
OPS.C.23
PIO S0C 3401 0805 X5R PIOS0C130 0805 X5R PIOS0C190 0805 X5R PIOS0C140 0805 X5R PIOS0C201 0805 X5R PIOS0C210 0805 X5R PIOS0C201 0805 X5R PIOS0C2301 0805 X5R
10uF 25V 10uF 25V 10uF 25V 1uF 25V 10uF 25V 10uF 25V 10uF 25V 1uF 25V
PIOPS0R 502 PIOS0R62
GND GND GND GND COR5
OPS.R.5 COR6
OPS.R.6 GND GND GND GND
0805 0805
COU9
OPS.U.9 PIOPS0R 501 100k 1% PIOS0R61 100k 1% PIO S0C 240 COC24
5 1 OPS.C.24
PIOPS0U0905
VIN SW PIOPS0U0901
The output capacitance doesn't have to be
PIOS0R72 PIO S0C 2401 0603
that high, but the calculator spreadsheet
COR7
OPS.R.7 820pF 25V 5% C0G
suggests at least 10uF is worthwhile to reduce
0805
output voltage ripple, and more is better.
GND
2
PIOPS0U0902
PIOS0R701 10k 1%

GND
POAUDIO00SUPPLY0EN 4 3
AUDIO_+SUPPLY_EN PIOPS0U0904 EN FB PIOPS0U0903

C
PIOS0R102 C
COR1
OPS.R.1 LM2735YMF PIOS0R82
0805 COR8
OPS.R.8
PIOS0R1 10k 1% When originally prototyping this circuit, I wanted the
0805
LM2735X, which operates at 1.5MHz. TI didn't have any in
PIOS0R81 10k 1%
stock, so I ordered the Y variant, which operates at 520kHz .
GND
Turns out that one works just fine, and since we've already
GND
tested it, let's just use that one!

Additionally, the negative rail charge pump uses a 10uH

inductor; a smaller one wouldn't work well. The X variant
would want a 3.3uH inductor, so making this circuit using
the Y variant harmonizes the inductor choice between
circuits.

D D

Copyright Ploopy Corporation 2022 Title: OpAmpSupply.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:50 AM Sheet 8 of 12 Canada

1 2 3 4
 1 2 3 4

This sheet contains two op amps that provide signal

gain/amplitude/differential and DC offset matching
between the PCM3060 DAC and the power stage. The
PCM3060 outputs a differential signal with a DC offset
equal to 1/2 of its' analog supply voltage. This
differential, offset signal must be converted to a
PIOUB0C12
COC1
OUB.C.1
single-ended signal witih 0 offset to work with the power
A stage, which is what this circuit does .
GND PIOUB0C1 0603 A
56pF 50V 5% C0G
Note the DC offset of 2.3V on the differential input
PIOUB0R201 COR2
OUB.R.2
0603 COR3
OUB.R.3 9V
voltage (from the DAC). However, at +/- 9V supply PO9V
9V
56k 1% 0805
voltage, the 2.3V DC offset is in no danger of upsetting

2
the apple cart (the allowable max Vcm is V+ - 2V, or 7V),
PIOUB0R20 1k 1% PIOUB0 1502
OUB.Ra.4C COOUB0U015A
COOUB0U015B
OUB.U.15A
so there's no worries to be had. POBUFFER INPUT
BUFFER INPUT R+ R0 PIOUB0Ra0403 PIOUB0Ra0406 PIOUB0R0301 PIOUB0R0302 V+
1206 Quad OPA1688IDRGx COTP4
OUB.TP.4
The original design comes from the PCM3060 datasheet 10k 1%
(page 40, Fig. 34(b)), and appears to be a differential
PIOUB0C20 COC2 PIOUB0U01501
1
+IN A
MFA topology. Analysis is complicated, so simulations
OUB.C.2
OUT A
7
PIOUB0U01507
PIOUB0TP401 POBUFFER OUTPUT
BUFFER OUTPUT R R
were done to optimize the frequency response.
PIOUB0C201 0603 8
PIOUB0U01508 -IN A
820pF 25V 5% C0G
Interestingly, this topology is quite sensitive to changes
in component values, so passive tolerances should be OUB.Ra.4D
minimized where practical. 5% caps have been specified POBUFFER INPUT
BUFFER INPUT R- R0 PIOUB0Ra0404 PIOUB0Ra0405 PIOUB0R0401 PIOUB0R0402
V-
for this purpose. 1206 Quad
10k 1% PIOUB0R230 COR4
OUB.R.4 PIOUB0 1503

3
COR23
OUB.R.23 0805 -9V PO09V
-9V
0603 1k 1%
PIOUB0R2301 56k 1% COC3
OUB.C.3
PIOUB0C0301 PIOUB0C0302

B B
0603
56pF 50V 5% C0G

PIOUB0C42
COC4
OUB.C.4
GND PIOUB0C41 0603
56pF 50V 5% C0G
PIOUB0R2401 COR24
OUB.R.24
0603 COR25
OUB.R.25
56k 1% 0805
PIOUB0R240 1k 1%
COOUB0Ra04A
COOUB0Ra04B
COOUB0Ra04C
COOUB0Ra04D
OUB.Ra.4A OUB.U.15B
C POBUFFER INPUT
BUFFER INPUT L+ L0 PIOUB0Ra0401 PIOUB0Ra0408 PIOUB0R02501 PIOUB0R02502
COTP10 C
1206 Quad OUB.TP.10
10k 1%
PIOUB0C502 PIOUB0U01504
4
+IN B
COC5
OUB.C.5
OUT B
6
PIOUB0U01506
PIOUB0TP10 POBUFFER OUTPUT
BUFFER OUTPUT L L
PIOUB0C501 0603 5
PIOUB0U01505
-IN B
820pF 25V 5% C0G

OUB.Ra.4B
POBUFFER INPUT
BUFFER INPUT L- L0 PIOUB0Ra0402 PIOUB0Ra0407 PIOUB0R02601 PIOUB0R02602

1206 Quad OPA1688IDRGx

10k 1% PIOUB0R280 COR26
OUB.R.26
COR28
OUB.R.28 0805
0603 1k 1%
PIOUB0R2801 56k 1% COC9
OUB.C.9
PIOUB0C0901 PIOUB0C0902
9V
NL9V
PIOUB0C602 0603
COC60
OUB.C.60 56pF 50V 5% C0G
PIOUB0C601 0805 X5R
0.1uF 100V

D D
PIOUB0C6102
GND OUB.C.61
COC61
PIOUB0C610 0805 X5R
0.1uF 100V
NL09V
-9V Copyright Ploopy Corporation 2022 Title: OutputBuffer.SchDoc Ploopy Corporation
Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:50 AM Sheet 9 of 12 Canada

1 2 3 4
 1 2 3 4

POPOWER0AMP0INPUT
POPOWER0AMP0INPUT0POL
POWER_AMP_INPUT_POL

9V PO9V0POL
PO9V 9V
9V_POL

2
PIOL0U42 PIOL0U52
A V+ OPOL0U04BA
CPOL.U.4A V+ OPOL0U05BA
CPOL.U.5A A
OPA1688IDRGx OPA1688IDRGx

1 1
PIPOL0U0401
+IN A COPOL0Ra05A
COPOL0Ra05B
COPOL0Ra05C
COPOL0Ra05D
POL.Ra.5A
PIPOL0U0501
+IN A COPOL0Ra06DCBA
POL.Ra.6A
7 7
OUT A PIPOL0U0407 PIPOL0Ra0501 PIPOL0Ra0508 OUT A PIPOL0U0507 PIPOL0Ra0601 PIPOL0Ra0608
8 1206 Quad 8 1206 Quad
PIPOL0U0408
-IN A PIPOL0U0508
-IN A
1R 5% 1R 5%

V- V-
PIOL0U43 PIOL0U53

3
-9V PO09V0POL
PO09V -9V
-9V_POL

POL.U.4B POL.U.5B

4 4
PIPOL0U0404 +IN B POL.Ra.5B PIPOL0U0504 +IN B POL.Ra.6B
6 6
OUT B PIPOL0U0406 PIPOL0Ra0502 PIPOL0Ra0507
OUT B PIPOL0U0506 PIPOL0Ra0602 PIPOL0Ra0607

5 1206 Quad 5 1206 Quad

PIPOL0U0405 -IN B PIPOL0U0505 -IN B
B 1R 5% 1R 5% B

OPA1688IDRGx OPA1688IDRGx

2 9V 9V

2
PIOL0U62 PIOL0U72
V+ OPOL0U06BA
CPOL.U.6A V+ OPOL0U07BA
CPOL.U.7A
OPA1688IDRGx OPA1688IDRGx

1 1
PIPOL0U0601
+IN A POL.Ra.5C
PIPOL0U0701
+IN A POL.Ra.6C
7 7
OUT A PIPOL0U0607 PIPOL0Ra0503 PIPOL0Ra0506 OUT A PIPOL0U0707 PIPOL0Ra0603 PIPOL0Ra0606 Because we're using a +/- 9V supply to produce a
8 1206 Quad 8 1206 Quad
PIPOL0U0608
-IN A PIPOL0U0708
-IN A signal of +/- 6.1V, we can use OPA1688s as unity-gain
1R 5% 1R 5% buffers. This is because the maximum input voltage
restriction (Vin+ - 2V, or 7V) is not violated. Yay!
V- V-

C
PIOL0U603 PIOL0U703
3

3
-9V -9V C
Each OPA1688 requires bypass caps, but
it'd be a mess to put them into the
schematic more directly, so here they are, Paralleling op amps with ballast resistors is Not
all alonesome in their little corner. Recommended As Best Practice by people who make
POL.U.6B POL.U.7B
op amps. That said, there are at least two examples
Each chip should get a cap to each supply of this working well in the wild: the October 2010
rail, placed as close to the chip as possible. issue of Elektor magazine presents a power amplifier
4 4
We opt here to have caps to ground (as PIPOL0U0604 +IN B POL.Ra.5D PIPOL0U0704 +IN B POL.Ra.6D using a very similar topology, and the Schiit Audio
6 6
opposed to a single cap from +ive to -ive OUT B PIPOL0U0606 PIPOL0Ra0504 PIPOL0Ra0505
OUT B PIPOL0U0706 PIPOL0Ra0604 PIPOL0Ra0605
Magni (Heretical Edition) also uses a similar design.
5 1206 Quad 5 1206 Quad
rail) because all of the return currents flow PIPOL0U0605
-IN B PIPOL0U0705
-IN B So screw the expert opinion?
back to this node. 1R 5% 1R 5%
One thing to note is that sourcing might matter -- a t
the Ploopy Factory, these boards are made from
OPA1688IDRGx OPA1688IDRGx TI-sourced amps that come new from factory and are
assembled sequentially off a contiguous tape, so the
9V
NL9V
inter-part tolerances are probably pretty good. I f
PIOL0C260 PIOL0C270 you're digging in your junk bin for this build, YMMV.
COC26
POL.C.26 COC27
POL.C.27
PIOL0C2601 0805 X5R PIOL0C2701 0805 X5R
0.1uF 100V 0.1uF 100V

D D
POPOWER0AMP0OUTPUT0POL
POPOWER0AMP0OUTPUT
POWER_AMP_OUTPUT_POL
PIOL0C302 PIOL0C3102
GND COC30
POL.C.30 COC31
POL.C.31
PIOL0C301 0805 X5R PIOL0C310 0805 X5R
Copyright Ploopy Corporation 2022 Title: PowerAmplifier.SchDoc Ploopy Corporation
0.1uF 100V 0.1uF 100V
-9V
NL09V Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:50 AM Sheet 10 of 12 Canada

1 2 3 4
 1 2 3 4

POPOWER0AMP0INPUT
POPOWER0AMP0INPUT0POR
POWER_AMP_INPUT_POR

9V PO9V0POR
PO9V 9V
9V_POR

2
PIOR0U42 PIOR0U52
A V+ OPOR0U04BA
CPOR.U.4A V+ OPOR0U05BA
CPOR.U.5A A
OPA1688IDRGx OPA1688IDRGx

1 1
PIPOR0U0401
+IN A COPOR0Ra05A
COPOR0Ra05B
COPOR0Ra05C
COPOR0Ra05D
POR.Ra.5A
PIPOR0U0501
+IN A COPOR0Ra06DCBA
POR.Ra.6A
7 7
OUT A PIPOR0U0407 PIPOR0Ra0501 PIPOR0Ra0508 OUT A PIPOR0U0507 PIPOR0Ra0601 PIPOR0Ra0608
8 1206 Quad 8 1206 Quad
PIPOR0U0408
-IN A PIPOR0U0508
-IN A
1R 5% 1R 5%

V- V-
PIOR0U43 PIOR0U53

3
-9V PO09V0POR
PO09V -9V
-9V_POR

POR.U.4B POR.U.5B

4 4
PIPOR0U0404 +IN B POR.Ra.5B PIPOR0U0504 +IN B POR.Ra.6B
6 6
OUT B PIPOR0U0406 PIPOR0Ra0502 PIPOR0Ra0507
OUT B PIPOR0U0506 PIPOR0Ra0602 PIPOR0Ra0607

5 1206 Quad 5 1206 Quad

PIPOR0U0405 -IN B PIPOR0U0505 -IN B
B 1R 5% 1R 5% B

OPA1688IDRGx OPA1688IDRGx

2 9V 9V

2
PIOR0U62 PIOR0U72
V+ OPOR0U06BA
CPOR.U.6A V+ OPOR0U07BA
CPOR.U.7A
OPA1688IDRGx OPA1688IDRGx

1 1
PIPOR0U0601
+IN A POR.Ra.5C
PIPOR0U0701
+IN A POR.Ra.6C
7 7
OUT A PIPOR0U0607 PIPOR0Ra0503 PIPOR0Ra0506 OUT A PIPOR0U0707 PIPOR0Ra0603 PIPOR0Ra0606 Because we're using a +/- 9V supply to produce a
8 1206 Quad 8 1206 Quad
PIPOR0U0608
-IN A PIPOR0U0708
-IN A signal of +/- 6.1V, we can use OPA1688s as unity-gain
1R 5% 1R 5% buffers. This is because the maximum input voltage
restriction (Vin+ - 2V, or 7V) is not violated. Yay!
V- V-

C
PIOR0U603 PIOR0U703
3

3
-9V -9V C
Each OPA1688 requires bypass caps, but
it'd be a mess to put them into the
schematic more directly, so here they are, Paralleling op amps with ballast resistors is Not
all alonesome in their little corner. Recommended As Best Practice by people who make
POR.U.6B POR.U.7B
op amps. That said, there are at least two examples
Each chip should get a cap to each supply of this working well in the wild: the October 2010
rail, placed as close to the chip as possible. issue of Elektor magazine presents a power amplifier
4 4
We opt here to have caps to ground (as PIPOR0U0604 +IN B POR.Ra.5D PIPOR0U0704 +IN B POR.Ra.6D using a very similar topology, and the Schiit Audio
6 6
opposed to a single cap from +ive to -ive OUT B PIPOR0U0606 PIPOR0Ra0504 PIPOR0Ra0505
OUT B PIPOR0U0706 PIPOR0Ra0604 PIPOR0Ra0605
Magni (Heretical Edition) also uses a similar design.
5 1206 Quad 5 1206 Quad
rail) because all of the return currents flow PIPOR0U0605
-IN B PIPOR0U0705
-IN B So screw the expert opinion?
back to this node. 1R 5% 1R 5%
One thing to note is that sourcing might matter -- a t
the Ploopy Factory, these boards are made from
OPA1688IDRGx OPA1688IDRGx TI-sourced amps that come new from factory and are
assembled sequentially off a contiguous tape, so the
9V
NL9V
inter-part tolerances are probably pretty good. I f
PIOR0C260 PIOR0C270 you're digging in your junk bin for this build, YMMV.
COC26
POR.C.26 COC27
POR.C.27
PIOR0C2601 0805 X5R PIOR0C2701 0805 X5R
0.1uF 100V 0.1uF 100V

D D
POPOWER0AMP0OUTPUT0POR
POPOWER0AMP0OUTPUT
POWER_AMP_OUTPUT_POR
PIOR0C302 PIOR0C3102
GND COC30
POR.C.30 COC31
POR.C.31
PIOR0C301 0805 X5R PIOR0C310 0805 X5R
Copyright Ploopy Corporation 2022 Title: PowerAmplifier.SchDoc Ploopy Corporation
0.1uF 100V 0.1uF 100V
-9V
NL09V Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:50 AM Sheet 11 of 12 Canada

1 2 3 4
 1 2 3 4

A A

COU3
REG.U.3
POV0USB 1 5 PO3V3
V_USB PIREG0U0301 VIN VOUT PIREG0U0305 3V3
PIREG0C5402 PIREG0C502 PIREG0C562
COC54
REG.C.54 COC55
REG.C.55 COC56
REG.C.56
PIREG0C5401 0805 PIREG0C501 0805 PIREG0C561 0805
1uF 25VPIREG0U0302
2 10uF 25V 1uF 25V
GND
GND GND
GND
3 4
PIREG0U0303 EN BYP PIREG0U0304

B PIREG0C1502 B
AP2202K-3.3 COC15
REG.C.15
PIREG0C150 0805
100pF 100V

GND

COU13
REG.U.13
1 5 PO4V6
PIREG0U01301 VIN VOUT PIREG0U01305 4V6
PIREG0C5702 PIREG0C5802
COC57
REG.C.57 COC58
REG.C.58
PIREG0C5701 0805 PIREG0R1902 PIREG0R20 PIREG0R210 PIREG0C5801 0805
1uF 25VPIREG0U01302
2 COR19
REG.R.19 COR20
REG.R.20 COR21
REG.R.21 1uF 25V
GND 0805 0805 0805
PIREG0R190 PIREG0R201
10k 1% 10k 1% 100k 1% PIREG0R210 GND
GND
3 4
C PIREG0U01303 EN ADJ PIREG0U01304
C
AP7330-W5
The actual output voltage setpoint is 4.6095V. This LDO exis t s
PIREG0R20 to give a very clean power rail to the PCM3060. Since we get
COR22
REG.R.22
our power from USB (minimum output 4.75V) and expect
0805
50mV of dropout at the desired load current, we aim for a
PIREG0R201 1k 1% voltage a little lower than that. Additionally, the PCM3060 is
only characterized for operation down to 4.5V, so we pick a
voltage that satisfies these criteria.
GND
For more details on the feedback network and choice o f
voltage, see AP7330-OutputCalculator.xlsx in the
ploopy/headphone repo.

D D

Copyright Ploopy Corporation 2021 Title: Regulators.SchDoc Ploopy Corporation

Licensed under the CERN-OHL-S v2 137-1140 Burnhamthorpe Road W
http://ohwr.org/cernohl PCB: Gould.PrjPCB Version: R1.007 Mississauga ON L5C 0A3
Date: 12/1/2022 Time: 1:44:50 AM Sheet 12 of 12 Canada

1 2 3 4