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Analog IC Design - 250521 - 122515

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13 views49 pages

Analog IC Design - 250521 - 122515

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ec22016
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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VELAMMAL INSTITUTE OF TECHNOLOGY

Velammal Knowledge Park, Panchetti

DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

EVEN SEMESTER LAB RECORD

ACADEMIC YEAR (2023-2024)

REGULATION-2021

NM1002 - ANALOG IC DESIGN

Name of the Student :

Register No. :

Department : Electronics & Communication Engineering

Name of Laboratory : Analog IC Design

Lab Code : NM1002

Year/Semester : III / VI
BONAFIDECERTIFICATE

University Reg.No.

This is to certify that this is a bonafide record work done by

Mr./Miss. studying B.E./B. Tech.,

Department in the

Laboratory for semester.

Staff-in-charge HeadoftheDepartment

Submitted for the University practical examination held on

at Velammal Institute of Technology.

Internal Examiner External Examiner


INDEX

E.NO DATE NAME OF THE EXPERIMENT MARKS/ FACULTY


GRADE SIGNATURE

1 Characteristic of NMOS

2 Design Nmos Transistor

3 Common drain amplifier

4 cmos inverter with nmos


transistor

5 Ring oscillator design with EDA


tool
EXP No: Characteristics of NMOS
Date:

AIM:
To determine the characteristics of NMOS Using LTSpice The transistor
dimension and the model parameters of a NMOS transistor is given as; width
W=100~\mu m, length L=10 µm, transconductance Kp=90\mu A/V2 , threshold
voltage Vto = 0.7 V, channel length modulation parameter
\lambda=0.12~V-1 , body effect coefficient \gamma=0.75VV and the surface
potential parameter |2\phi F|=0.7~V. And to analyze the characteristics of the
NMOS by performing the following simulations.

1) To determine the bias current ID and the small-signal parameters gm,


gmb and gds forthe bias point of VGS = 3 V and VDS = 5 V.

2) To plot the input characteristics ID vs VGS for varying VDS

3) To plot the output characteristics ID vs VDS for varying VGS

4) To plot the variation of drain current ID for channel width


W=100\mu m, 125µm and 150µm with L=20\mu m

5) To plot the variation of drain current ID for channel length L=10\mu


m,20\mu m and25µm, with W=150\mu m

APPARATUS REQUIRED:

 Personal Computer

 Lt spice
DESIGNING:
1) Determine the bias current ID and the small-signal parameters gm, gmb and gds for
the bias point of VGS = 3 V and VDS = 5 V.
2) Plot the input characteristics ID vs VGS for varying VDS(In DC sweep have Vgs as
the first source and Vds as the second source) .dc Vgs 0 5 0.01 Vds 0 5 1
3) Plot the output characteristics ID vs VDS for varying VGS(In DC sweep have Vgs as
the first source and Vds as the second source) .dc Vds 0 5 0.01 Vgs 0 5 1
4) Plot the variation of drain current ID for channel width W=100\mu m,
125µm and 150µm with L=20um2s
.model NMOS TASK 1 NMOS(kp=90u Vto=0.7 + Lambda=0.12 Gamma=0.75 Phi=0.7)
.param L 20u
.step param W 100u 150u 25u .dc Vds 0 5 0.01
5) Plot the variation of drain current ID for channel length L=10\mu m,20\mu m and
25µm, with W=150\mu m.
.model NMOS TASK 1 NMOS(kp=90u Vto=0.7 + Lambda=0.12 Gamma=0.75 Phi=0.7)
.param L 20u
.step param L 10u 25u 5u .dc Vds 0 5 0.01
RESULT:
Thus the characteristics of NMOS Using LT Spice is determined successfully, with the
given model parameters of a NMOS transistor.
Exp no: Design of NMOS Transistor
Date:

AIM :
To design a NMOS Device with W/L ratio 10 and 200nm AMI Semiconductor's C5
Process and analyze its I/V characteristics using EDA Tool
A. To design of Schematic and Simulation of IV curves NMOS Device Using EDA Tool
B. To design of Layout and Simulation of IV curves NMOS Device Using Electric
EDATool

Part A
◆ Explain the concept of NMOS Device in analog circuit design
◆ Learn to create the schematic representation of NMOS Device using the Electric
VLSI EDA Tool.
◆ Implement DRC to ensure the integrity and correctness of the NMOS Device design
◆ Simulate the NMOS Device to analyze its behavior and characteristics under
different input conditions
Part B
◆ Design the layout representation of a NMOS Device using Electric VLSI EDA tool,
co
◆ Perform DRC, ERC and LVS (Layout vs. Schematic) checks to ensure the correctness
and integrity of the NMOS Device layout
◆ Conduct simulation on the layout of the NMOS Device to verify its characteristics
under different input conditions

Software Tools: Electric VLSI EDA Tool- Open Source Equivalent EDA tool to
Cadence
NOTE: PART B: The input and output curves are in opposite due to DRAIN &
GATE were reversed.

APPARATUS REQUIRED:

 Personal computer
 Electrical VLSI
 EDA Tool
DESIGNING:
PART A)
1) a) NMOS SCHEMATIC :

b) OPRATING POINTS ie DC ANALYSIS:


c) SMALL SIGNAL PARAMETERS: LIKE gm,gmb,gds and all parasitic parameters
etc

2) a) INPUT CHARACTERISTICS:
2) b) OUTPUT CHARACTERICTICS: .dc Vds 0 5 0.01 Vgs 0 5 1
PART B
(a) LAYOUT:
(b) DC OPERATING POINTS:

(c) SMALL SIGNAL VLUES AND PARACITIC VALUES:


(d) INPUT CHARACTERITICS:
(e) OUTPUT CHARACTERICS:
(f) 3D VIEW:

RESULT:

Hence, the simulation and layout of NMOS transistor was executed successfully.
Exp No. Common Drain Amplifier
Date.

AIM:

To design a Common drain amplifier with W/L ratio 20 and 300nm AMI Semiconductor's
C5Process and analyze its performance.
A. Design of Schematic and Simulation of Common drain amplifier Using EDA Tool

Part A
◆ Explain the concept of a common-drain amplifier and its importance in analog circuit
design
◆ Design a schematic representation of the common- drain amplifier in the Electric VLSI
EDA tool
◆ Perform the design verification checks such as DRC and ERC to verify the integrity of the
schematic design and identify any potential errors or violations
◆ Simulate the common- drain amplifier schematic to evaluate its performance through
waveform analysis

APPARATUS REQUIRED:

 Personal Computer
 Electrical VLSI
 EDA Tool

DESIGNING:

1. A) SCHEMATIC DIAGRAM:

[Go to File-new library-name as CMOS_INVERTER_NAME THEN PRESS OK and check


Explorer click above name. Then go to new cell select schematic and name as like
CMOS_INVERTER_TASK3 THEN PRESS OK NOW new window open. Now place the
PMOS AND NMOS. For changing dimensions select those components with ctrl+I. Now
name PMOS & NMOS FOR that components go to Tools –Simulation (Spice) or ctrl+I. Now
write a program go to Misc-text place it then go to EDIT –Spice code ctrl+I. OR Go to Edit-
properties- object properties then write the code or program].
B) DC OPERATING POINTS:

C) SMALL SIGNAL VALUES:


D) Transient Analysis:

[.tran 0 5m] Then run go to Tools – simulation(spice) – write spice Deck then first sect vout
and
right click Add Plot Plan then select vin then both will shown or either way u can do it].
E) AC ANALYSIS:

[.ac dec 100 100 10g] Run it get Vout as like bode plot ie Frequency response of
CSAMPLIFIER].
F) DC ANALYSIS:

[.dc vin 0 5 .1]


G) FINAL SCHEMATIC:
B. Design of Layout and Simulation of Common drain amplifier Using Electric
EDA Tool

Part B

◆ Learn the process of creating a layout representation for a common drain


amplifier using the Electric VLSI EDA tool

◆ Perform DRC and ERC to ensure that the layout meets the specified design
rules and to address any potential electrical connectivity concerns

◆ Verify the layout's connectivity and compatibility through Layout vs.


Schematic (LVS) checking

◆ Simulate the layout of the Common drain Amplifier to analyze its


performance and characteristic

2. A) LAYOUT DIAGRAM:

[Go to File-new library-name as CMOS_INVERTER_NAME THEN PRESS OK and check


Explorer
click above name. Then go to new cell select layout and name as like
CMOS_INVERTER_TASK3
THEN PRESS OK NOW new window open. Now place the PMOS AND NMOS. For
changing
dimensions select those components with ctrl+I. Now name PMOS & NMOS FOR that
components go to Tools –Simulation (Spice) or ctrl+I. Now write a program go to Misc-text
place it then go to EDIT –Spice code ctrl+I. OR Go to Edit- properties- object properties then
write the code or program].
B) DC OPERATING POINTS:
C) SMALL SIGNAL VALUES:

D) Transcient Analysis:
[.tran 0 5m] Then run go to Tools – simulation(spice) – write spice Deck then first sect vout
and
right click Add Plot Plan then select vin then both will shown or either way u can do it].
E) AC ANALYSIS:
[.ac dec 100 100 10g] Run it get Vout as like bode plot ie Frequency response of
CSAMPLIFIER].
F) DC ANALYSIS:
[.dc vin 0 5 .1]
G) FINAL LAYOUT:

RESULT:

Thus the schematic and layout of common drain amplifier was executed successfully.
Exp No CMOS Inverter with NMOS Transistor
Date.

AIM:

To design a CMOS inverter with NMOS transistor W/L ratio 6 and PMOS transistor W/L ratio
12 with 300nm AMI Semiconductor's C5 Process and analyze its characteristics using EDA
Tool.
A. Design of Schematic and Simulation of CMOS Inverter Using EDA Tool.

Part A
◆ Explain the concept of CMOS inverter in analog circuit design
◆ Learn to create the schematic representation of a CMOS inverter using the Electric VLSI
EDA Tool, capturing the NMOS and PMOS transistor connections
◆ Implement DRC to ensure the integrity and correctness of the CMOS inverter design
◆ Simulate the CMOS inverter to analyse its behavior and characteristics under different
input conditions

APPARATUS REQUIRED:

 Personal computer
 Electrical VLSI
 EDA Tool

DESIGNING:

1. A) SCHEMATIC DIAGRAM:
[Go to File-new library-name as CMOS_INVERTER_NAME THEN PRESS OK and check
Explorer click above name. Then go to new cell select schematic and name as like
CMOS_INVERTER_TASK4 THEN PRESS OK NOW new window open. Now place the
PMOS AND NMOS. For changing dimensions select those components with ctrl+I. Now
name PMOS & NMOS FOR that components go to Tools –Simulation (Spice) or ctrl+I. Now
write a program go to Misc-text place it then go to EDIT –Spice code ctrl+I. OR Go to Edit-
properties- object properties then write the code or program].
B) DC OPERATING POINTS:

C) SMALL SIGNAL VALUES:


D) TRANSIENT ANALYSIS:
[.tran 1n 100n] Then run go to Tools – simulation(spice) – write spice Deck then first sect
vout and right click Add Plot Plan then select vin then both will shown or either way u can do
it].
B.] Design of Layout and Simulation of CMOS Inverter Using Electric EDA Tool.
Part B
◆ Design the layout representation of a CMOS inverter using Electric VLSI EDA tool,
considering the placement and routing of NMOS and PMOS transistors
◆ Perform DRC, ERC and LVS (Layout vs. Schematic) checks to ensure the correctness and
integrity of the CMOS inverter layout
◆ Conduct simulation on the layout of the CMOS inverter to verify its characteristics under
different input conditions
Software Tools: Electric VLSI EDA Tool- Open Source Equivalent EDA tool to Cadence

2. A) LAYOUT DIAGRAM:
[Go to File-new library-name as CMOS_INVERTER_NAME THEN PRESS OK and check
Explorer click above name. Then go to new cell select layout and name as like
CMOS_INVERTER_TASK4 THEN PRESS OK NOW new window open. Now place the
PMOS AND NMOS. For changing dimensions select those components with ctrl+I. Now
name PMOS & NMOS FOR that components go to Tools –Simulation (Spice) or ctrl+I. Now
write a program go to Misc-text place it then go to EDIT –Spice code ctrl+I. OR Go to Edit-
properties- object properties then write the code or program].
B) DC OPERATING POINTS:
C) SMALL SIGNAL VALUES:

D) TRANSIENT ANALYSIS:
[.tran 1n 100n] Then run go to Tools – simulation(spice) – write spice Deck then first sect
vout and right click Add Plot Plan then select vin then both will shown or either way u can do
it].
RESULT:

Thus the CMOS inverter was designed successfully using EDA tool.
Exp No. Ring oscillator design with EDA tool
Date.

AIM:

To design the Ring Oscillator using 300nm AMI Semiconductor's C5 Process using EDA
Tool.

APPARATUS REQUIRED:

 Personal computer
 Electrical VLSI
 EDA Tool

DESIGNING:
PART-A

Schematic Design and Simulation

Inverter Icon Design:

Ring Oscillator Schematic Design:


Schematic output:
PART-B
Layout Design and Simulation:
Layout Output:
3D VIEW:

Performance of DRC CHECK, WELL CHECK, NCC CHECK:

RESULT:

Thus the ring oscillator was designed successfully with the EDA tool.

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