MUTHAYAMMAL ENGINEERING COLLEGE

(An Autonomous Institution)

(Approved by AICTE, New Delhi, Accredited by NAAC & Affiliated to Anna University) Rasipuram - 637 408, Namakkal Dist., Tam

Department of Electronics and Communication Engineering

23EVC24 CMOS VLSI DESIGN LABORATORY

LAB OBSERVATION

Prepared by,

1. Ms.Venkateshwari , AP/ECE

Syllabus

1. Plot the (i) output characteristics & (ii) transfer characteristics of an n-channel and p-channel MOSFET

2. Design and plot the static (VTC) and dynamic characteristics of a digital CMOS inverter

3. Design and plot the output characteristics of a 3-inverter ring oscillator

4. Design and plot the dynamic characteristics of 2-input NAND, NOR, XOR and XNOR logic gate using CMOS technology

5. Design and plot the characteristics of a Pass Transistor Logic

6. Design and plot the characteristics of a Transmission Gate

7. Design and plot the characteristics of a 4x1 digital multiplexer using pass transistor logic

8. Design and plot the characteristics of a positive and negative latch based on multiplexers

9. Design and plot the characteristics of a master-slave positive and negative edge triggered registers based on multiplexers
10. Draw the layout of an n-channel and p-channel MOSFET and perform the DRC, LVS and RC extraction

TABLE OF CONTENTS
Marks
Signature of the staff
DIAGRAM

Fig. 4: Channel pinchoff for (a) nMOS and (b) pMOS transistor devices.

SYMBOL
Fig. (2): Circuit symbols for nMOS and pMOS respectively

Ex. No:1 PLOT THE (I) OUTPUT CHARACTERISTICS & (II) TRANSFER
DATE: CHARACTERSTICS OF n-CHANNEL AND p-CHANNEL
MOSFET

AIM :
To Plot the (i) output characteristics & (ii) transfer characteristics of an n-channel and p-channel MOSFET.

THEORY:
The metal-oxide-semiconductor field-effect transistor (MOSFET) is a transistor used for amplifying or switching electronic sign
Figure 2 shows symbols commonly used for MOSFETs where the bulk terminal is either labeled (B) or implied (not drawn).
The characteristics of an nMOS transistor can be explained as follows. As the voltage on the top electrode increases further, e
OUTPUT CHARACTERISTICS :

TRANSFER CHARACTERISTICS :

either the non-saturated, linear, or ohmic bias state. The drain and source are effectively short-circuited. This happens when V
But if the nMOS drain voltage increases beyond the limit, so that VGS < VDS + Vtn, then the horizontal electric field becomes s
If the drain voltage riseswhile the gate voltage remains the same, then VGD can go below the threshold voltage in the drain re

Transfer Characteristics
The transfer characteristic relates drain current (ID) response to the input gate-source driving voltage (VGS). Since the gate ter
The transistors are in their non-saturated bias states. As VGS increases for the nMOS transistor in Figure 5a, the threshold volt
RESULT:
Thus the (i) output characteristics & (ii) transfer characteristics of an n-channel and p-channel MOSFET successfully plot

CIRCUIT DIAGRAM :
EX. NO : 2 DESIGN AND PLOT THE STATIC (VTC) AND DYNAMIC
DATE : CHARACTERISTICS OF A DIGITAL CMOS INVERTER

AIM:
To design and plot the static (VTC) and dynamic characteristics of a digital CMOS inverter

SOFTWARE USED:
Mentor graphics

THEORY :

CMOS INVERTER
The NMOS transistor and the PMOS transistor form a typical complementary MOS (CMOS) device. When a low voltage (0 V) is

PROCEDURE:
Step 1: Go to file?new?new library?select TINCY DOC?Tannel EDA?new folder?ok250nm. click ok
Step 2: Select file name ?Add library?library folder?DOC?Tanner EDA?Tools?process?Generic device
Step 3: Same procedure to step 2 to follow up to select?Standard ?Misc?spice?plot?spice source.
Step 4: Go to cell view ?new view?library"file name"and give as cell name ?"CMOS Inverter" & select a view type schematic an
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on CMOS inverter and give connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.

OUTPUT WAVEFORM :
Step 9: Adding a DC voltage source & C-V source from the library and change the value of the DC property to be 3.3V Add puls
Step 10: Simulating the Schematic
* select on menu bar and select run simulation .
* Click ok now design context window are open and need to setup the analysis type, plots and load in the Eldo models.
* In the design context from menuber select simulation ?setup simulation or click on setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the transient analysis with the start time as on
Step 12: To probe the waveform click on the o/p in the selection panel,then select the input port of the schematic window as
Step 13: In the setup simulation window ,click add button then the port will be added to the wave form as shown.
Step 14: To view the simulation result by selecting the plot result from latest run icon from the left icon palatts .This will open

RESULT:
Thus the design and implementation of CMOS inverter is verified successfully.
CIRCUIT DIAGRAM :

OUTPUT CHARACTERISTICS :
EX. NO : 3 DESIGN AND PLOT THE OUTPUT CHARACTERISTICS
DATE : OF 3 - INVERTER RING OSCILLATOR

AIM :
To design and plot the output characteristics of 3 - inverter ring oscillator using mentor graphics.
SOFTWARE REQUIRED :
Mentor Graphics
THEORY :
The NOT gates, or inverters, are attached in a chain; the output of the last inverter is fed back into the first. Because a single in
PROCEDURE :
Step 1: Go to file?new?new library?select TINCY DOC?Tannel EDA?new folder?ok250nm. click ok
Step 2:Select file name ?Add library?library folder?DOC?Tannel EDA?Tools?process?Generic device
Step 3:Same procedure to step 2 to follow up to select?Standard ?Misc?spice?plot?spice source.
Step 4:Go to cell view ?new view?library"file name"and give as cell name ?"3 Inverter Ring Oscillator" & select a view type sch

Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on 3 - inverter ring oscillator and give connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value of the DC property to be 3.3V Add puls
Step 10: Simulating the Schematic
* select on menu bar and select run simulation .
* Click ok now design context window are open and need to setup the analysis type, plots and load in the Eldo models.
* In the design context from menuber select simulation ?setup simulation or click on setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the transient analysis with the start time as on
Step 12: To probe the waveform click on the o/p in the selection panel,then select the input port of the schematic window as
Step 13: In the setup simulation window ,click add button then the port will be added to the wave form as shown.
Step 14: To view the simulation result by selecting the plot result from latest run icon from the left icon palatts .This will open

RESULT :
Thus the 3 - inverter ring oscillator was designed and its output characteristics was plotted successfully.
CIRCUIT DIAGRAM OF 2 INPUT NAND GATE :

CIRCUIT DIAGRAM OF 2 INPUT NOR GATE :

EX. NO : 4 DESIGN AND PLOT THE DYNAMIC CHARACTERISTICS

DATE : OF 2-INPUT NAND, NOR, XOR AND XNOR LOGIC GATE
USING CMOS TECHNOLOGY

AIM :
To Design and plot the dynamic characteristics of 2-input NAND, NOR, XOR and XNOR logic gate using CMOS technology .

SOFTWARE REQUIRED :
Mentor Graphics

THEORY :

CIRCUIT DIAGRAM OF 2 INPUT XOR GATE :

CIRCUIT DIAGRAM OF 2 INPUT NAND GATE :

PROCEDURE :

Step 1: Go to file?new?new library?select TINCY DOC?Tannel EDA?new folder?ok250nm. click ok

Step 2: Select file name ?Add library?library folder?DOC?Tannel EDA?Tools?process?Generic device
Step 3: Same procedure to step 2 to follow up to select?Standard ?Misc?spice?plot?spice source.
Step 4: Go to cell view ?new view?library"file name"and give as cell name ?"2 input NAND, NOR, XOR, XNOR" & select a view t
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on 2 input NAND, NOR, XOR, XNOR and give connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value of the DC property to be 3.3V Add puls
Step 10: Simulating the Schematic
* select on menu bar and select run simulation .
* Click ok now design context window are open and need to setup the analysis type, plots and load in the Eldo models.
* In the design context from menuber select simulation ?setup simulation or click on setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the transient analysis with the start time as on
Step 12: To probe the waveform click on the o/p in the selection panel,then select the input port of the schematic window as
Step 13: In the setup simulation window ,click add button then the port will be added to the wave form as shown.

OUTPUT WAVEFORM : (2 Input NOR Gate)

OUTPUT WAVEFORM : (2 Input XOR Gate)

Step 14: To view the simulation result by selecting the plot result from latest run icon from the left icon palatts .This will open
OUTPUT WAVEFORM : (2 Input XNOR Gate)
RESULT :
Thus the 2-input NAND, NOR, XOR and XNOR logic gate using CMOS technology was designed and its dynamic characteristics w

CIRCUIT DIAGRAM :

TRUTH TABLE :

EX. NO : 5 DESIGN AND PLOT THE CHARACTERISTICS OF A PASS

DATE : TRANSISTOR LOGIC
AIM :
To design and plot the characteristics of a pass transistor logic.

SOFTWARE REQUIRED :
Mentor Graphics

THEORY :
The Pass transistor logic is required to reduce the transistors for implementing logic by using the primary inputs to drive gate t
For Example the implementation of AND function using only NMOS pass transistors. In this gate if the B input is high the left N
The major advantage of pass transistor logic is that fewer transistors are required to implement a given function. To illustrate

PROCEDURE :
Step 1: Go to file?new?new library?select TINCY DOC?Tannel EDA?new folder?ok250nm. click ok
Step 2: Select file name ?Add library?library folder?DOC?Tannel EDA?Tools?process?Generic device
Step 3: Same procedure to step 2 to follow up to select?Standard ?Misc?spice?plot?spice source.
Step 4: Go to cell view ?new view?library"file name"and give as cell name ?"Pass Transistor" & select a view type schematic an
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on pass transistor logic and give connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value of the DC property to be 3.3V Add puls
Step 10: Simulating the Schematic
* select on menu bar and select run simulation .
* Click ok now design context window are open and need to setup the analysis type, plots and load in the Eldo models.
* In the design context from menuber select simulation ?setup simulation or click on setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the transient analysis with the start time as on
Step 12: To probe the waveform click on the o/p in the selection panel,then select the input port of the schematic window as
Step 13: In the setup simulation window , click add button then the port will be added to the wave form as shown.

Step 14: To view the simulation result by selecting the plot result from latest run icon from the left icon palatts .This will open

RESULT :
Thus the pass transistor logic circuit was designed and its characteristics was plotted successfully.
CIRCUIT DIAGRAM :
EX. NO : 6 DESIGN AND PLOT THE CHARACTERISTICS OF A
DATE : TRANSMISSION GATE

AIM :
To design and plot the characteristic of a transmission gate .

SOFTWARE USED :
Mentor Graphics

THEORY :
Transmission gates represent another class of logic circuits, which use Transmission gates as basic building block. A transmissio

PROCEDURE :

Step 1: Go to file?new?new library?select TINCY DOC?Tannel EDA?new folder?ok250nm. click ok

Step 2: Select file name ?Add library?library folder?DOC?Tanner EDA?Tools?process?Generic device
Step 3: Same procedure to step 2 to follow up to select?Standard ?Misc?spice?plot?spice source.
Step 4: Go to cell view ?new view?library"file name"and give as cell name ?"Transmission Gate" & select a view type schemati
Step 5: Select on generic 250nm devices and also select on nmos25 and pmos25
Step 6: Schematic will create and should draw on transmission gate and give connections.
Step 7: Click on MISC and select on GND component and Vdd components.
Step 8: Adding the ports and connecting the devices and save as schematic.
Step 9: Adding a DC voltage source & C-V source from the library and change the value of the DC property to be 3.3V Add puls
Step 10: Simulating the Schematic
* select on menu bar and select run simulation .
* Click ok now design context window are open and need to setup the analysis type, plots and load in the Eldo models.
* In the design context from menuber select simulation ?setup simulation or click on setup simulation in the left icon plalalte.
Step 11: A set up simulation window will pop up is shown .Here I have selected the transient analysis with the start time as on
Step 12: To probe the waveform click on the o/p in the selection panel,then select the input port of the schematic window as
Step 13: In the setup simulation window , click add button then the port will be added to the wave form as shown.
Step 14: To view the simulation result by selecting the plot result from latest run icon from the left icon palatts .This will open

RESULT :
Thus the design of pass transistor was designed and the characteristics was plotted successfully.

CIRCUIT DIAGRAM :

EX. NO : 7 DESIGN AND PLOT THE CHARACTERISTICS OF A 4X1 DIGITAL

DATE : M ULTIPLEXER USING PASS TRANSISTOR LOGIC
AIM :
To Design and plot the characteristics of a 4x1 digital multiplexer using pass transistor logic.

SOFTWARE REQUIRED :
Mentor Graphics
diagram of the structure of an nMOS device before and after channel formation.

ype inversion layer, or inversion region, directly underneath the top plate as indicated in Fig. 1(b). This inversion region is an extremely sh
p-bulk form a pn junction.When this happens the inversion channel is said to be "pinched-off" and the device is in the saturation region. Th

leaves the OFF-state. This is the device threshold voltage (Vtn). Figure 5 shows measured input characteristics for an nMOS and pMOS tra
ivalent resistance at the drain decreases with increasing gate-source voltage. Therefore, the threshold voltage of the given nMOS transisto
e input causes oscillation. A real ring oscillator only requires power to operate; above a certain threshold voltage, oscillations begin sponta
ther advantage of pass transistor logic is the lower capacitance because of reduced number of transistors. As discussed NMOS devices are
nected to C and gate of PMOS is connected to Cbar(invert of C). When control signal C is high i.e. VDD, both transistor are on and provides
sion region is an extremely shallow layer, existing as a charge sheet directly below the gate. In the MOS capacitor, the high density of elec
tage, oscillations begin spontaneously. To increase the frequency of oscillation, two methods may be used. Firstly, the applied voltage ma
As discussed NMOS devices are effective in passing strong '0' but it is poor at pulling a node to VDD. Hence when the pass transistor pulls a
acitor, the high density of electrons in the inversion layer is supplied by the electron-hole generation process within the depletion layer. Th
s within the depletion layer. The positive charge on the gate is balanced by the combination of negative charge in the inversion layer plus n
ge in the inversion layer plus negative ionic acceptor charge in the depletion layer. The voltage at which the surface inversion layer just fo
surface inversion layer just forms plays an extremely important role in field-effect transistors and is called the threshold voltage Vtn. The
he threshold voltage Vtn. The region of output characteristics where VGStn and no current flows is called the cutt-off region. When the ch
e cutt-off region. When the channel forms in the nMOS (pMOS) transistor, a positive (negative) drain voltage with respect to the source cre
with respect to the source creates a horizontal electric field moving the electrons (holes) toward the drain forming a positive (negative) d
orming a positive (negative) drain current coming into the transistor. The positive current convention is used for electron and hole curren
d for electron and hole current, but in both cases electrons are the actual charge carriers. If the channel horizontal electric field is of the sa
zontal electric field is of the same order or smaller than the vertical thin oxide field, then the inversion channel remains almost uniform al