Data Sheet

DesignWare Cores
Hi-Speed USB On-The-Go
Controller Subsystem

Overview
The DesignWare® Cores Hi-Speed USB On-The-Go (HS OTG) Controller Subsystem provides designers high-quality USB IP for the most
demanding USB 2.0 peripherals. Based on Synopsys’ success in building and deploying Hi-Speed USB 2.0 Host, Device and PHY
designs in over 100 design wins, the DesignWare HS OTG Subsystem incorporates all Synopsys learning to date in Reuse Methodology,
Constrained Random Verification, and USB PHY interoperability to deliver flexible, quality IP in Verilog source.

The DesignWare HS OTG Subsystem performs as a standard Hi-Speed, Dual-Role Device (DRD), operating as either a USB 2.0
Hi-Speed compliant peripheral, or Hi-Speed USB 2.0 host. For example, when HS OTG is implemented in a PDA, the PDA can
synchronize with a PC. The PDA can also act as the host printing pictures and documents directly to a USB printer without the aid of
a PC. Additional applications include mobile phones, MP3 players, digital cameras, set-top boxes, scanners and fax machines.

The DesignWare USB HS OTG Subsystem delivers a flexible, low gate count USB controller capable of OTG, host and device functions.

Features HS OTG v2.0 Architecture

■ Hi-Speed OTG, Hi-Speed Host, AHB

and Hi-Speed Device core designed

for low gate count, power sensitive Bus Interface Unit(s) AHB Slave AHB Master

products
Configuration
■ Software flexible for post-silicon Option
Application Interface Unit Host DMA Scheduler
configuration
■ Testbench enables subsystem unit-
testing in the target configuration Packet FIFO Controller Single Tx Single Rx
SPRAM
option for shared FIFO memory to Non-Periodic Non-Periodic
Single Tx Periodic (Host)
(Host & Dev) (Host & Dev)
Synchronizer

minimize RAM area. Multiple Tx Periodic (Dev)

Sink
CSRs

Source
■ Slave only option to eliminate the Buffer
Host Token Gen Buffer
need for DMA
■ Option to include internal DMA
■ Supports single port RAM to Media Access Controller (MAC) UTMI+

minimize area use

PHY Interface Module PHY AHB
■ Supports ULPI or UTMI+ Level 3 PHY Clock Clock
■ Optional support for FS OTG or FS interface ULPI Domain Domain

USB 1.1 TxRx Clock

Generator Wakeup and Power Control (WPC) Power
Control
USB 1.1 FS OTG ULPI PHY UTMI+
TxRx TxRx Level 3 PHY
Highlights The Transaction Layer Interface (TLI) buffers data for the
■ Configuration options to maximize performance controller. The TLI includes:
and minimize CPU interrupts ■ FIFO control logic for buffering data in and out of the
■ Flexible parameters enable easy integration into low subsystem and minimizing configuration, design, and
and high-latency systems verification time
■ Transfer or transaction-based processing of USB data ■ Control and Status registers for reconfiguring the subsys-
based on system requirements tem through firmware for maximum flexibility
■ Configurable data buffering options to fine-tune
performance/area trade-offs The optional DMA Controller provides AHB Master capability,
■ Buffer and descriptor pre-fetching maximizes including the following:
host throughput ■ Interfacing through descriptors for the software
■ Firmware-selectable endpoint configurations enable ■ Reducing CPU interrupts
post-silicon ■ Enhancing throughput on AHB
application changes and the flexibility of one-chip ■ Optional generic interface to a DMA controller for designers
design for multiple applications to use their own DMA
■ Quality IP is tested through extensive Constrained
Random Verification DesignWare HS OTG from the USB IP Industry Leader
■ AMBA™ High-Performance Bus (AHB) interface Synopsys engineers built the DesignWare HS OTG Subsystem
enables rapid integration into ARM-based designs based on expertise gained in delivering Synopsys’ robust USB
■ UTMI+ Level 3 enables rapid integration with 2.0 Host, Device, OTG, and PHY product lines. This extensive
compatible PHYs range and proficiency, along with world-class documentation,
■ Hi-Speed (480 Mbps), Full-Speed (12 Mbps), and provides the definitive source for users to integrate high-perform-
Low-Speed (1.5 Mbps) operation is compliant to the ance, high-quality USB IP into their advanced designs.
USB OTG Supplement
■ Supports all OTG features, including Host Negotiation About DesignWare Cores
Protocol and Session Request Protocol Synopsys’ DesignWare Cores provide system designers
■ Verilog source RTL with silicon-proven, digital and analog connectivity intellectual
property (IP) for some of the world’s most recognized prod-
DesignWare HS OTG ucts including communications processors, routers, switches,
Subsystem Architecture game consoles, digital cameras, computers, and computer
The Synopsys DesignWare HS OTG Subsystem is built peripherals. The DesignWare Cores family includes industry-
on the industry’s most widely used and proven DesignWare leading connectivity IP such as USB 1.1, 2.0, OTG and
USB 2.0 Device Controller. The subsystem includes the HS PHYs, PCI, PCI-X, PCI Express, PCI Express PHY, SATA and
OTG Controller, Transaction Layer Interface, and Bus Interface Ethernet IP standards. Provided as synthesizable RTL source
Unit (BIU). code or in GDS format, these cores enable designers to
create innovative, cost-effective systems-on-chip and embed-
The Controller executes all USB and OTG commands in ded systems. Synopsys provides flexible licensing options for
hardware. This module: the DesignWare Cores. Each core can be licensed individu-
■ Tracks endpoint information in the EP Info block ally, on a fee-per-project basis, or users can opt for the
■ Processes data to and from UTMI+ PHY in the parallel Volume Purchase Agreement, which enables them to license
interface engines all the cores in one simple agreement.
■ HNP an SAP features may be removed during
configuration to save gate count. For more information on DesignWare IP, visit:
■ Manages downstream devices through the Root Hub www.designware.com
■ Saves power by suspending and resuming controller opera-
tion in compliance with the USB specification

700 East Middlefield Road, Mountain View, CA 94043 www.synopsys.com

Synopsys, the Synopsys logo, and DesignWare are registered trademarks of Synopsys, Inc. PCI, PCI-X, and PCI Express are registered trademarks of PCI-SIG. AMBA is a trademark of
ARM Limited in the UK. All other products or service names mentioned herein are trademarks of their respective holders and should be treated as such. Printed in the U.S.A.
©2005 Synopsys, Inc. 08/05.KF.WO.05-13516