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COA Predicted QP 2025 by Deepseek

The document is a predicted question paper for the CST202 course on Computer Organization and Architecture for the May 2025 examination at APJ Abdul Kalam Technological University. It includes a structured format with two parts: Part A consists of ten short answer questions, while Part B requires detailed answers to one question from each of the five modules. Topics covered include memory operations, addressing modes, ALU design, pipeline hazards, and cache mapping techniques.

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376 views5 pages

COA Predicted QP 2025 by Deepseek

The document is a predicted question paper for the CST202 course on Computer Organization and Architecture for the May 2025 examination at APJ Abdul Kalam Technological University. It includes a structured format with two parts: Part A consists of ten short answer questions, while Part B requires detailed answers to one question from each of the five modules. Topics covered include memory operations, addressing modes, ALU design, pipeline hazards, and cache mapping techniques.

Uploaded by

jztfun3
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Predicted CST202 COA (Computer Organization and Architecture)

Question Paper - May 2025


Based on the analysis of previous years' question papers (2021-2024), here's a predicted question paper for May 2025:

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY


B.Tech Degree S4 Examination May 2025

Course Code: CST202


Course Name: Computer Organization and Architecture
Max. Marks: 100
Duration: 3 Hours

PART A

(Answer all questions; each question carries 3 marks)

1.
Explain the role of MAR and MDR registers during memory read operation.

2.
Differentiate between auto-increment and auto-decrement addressing modes with examples.
3.
Illustrate the shift microoperation for logical right shift with an example.

4.
Draw the block diagram of a single-bus processor organization.

5.
Explain divide overflow condition in division algorithms.

6.
Differentiate between structural and data hazards in pipelining.

7.
Draw the block diagram of a PLA-based control unit.

8.
Explain the role of the next address generator in microprogrammed control.

9.
Why does DRAM need refreshing? Explain with the cell structure.

10.
Explain the concept of locality of reference and its importance in cache memory.
PART B

(Answer one full question from each module; each question carries 14 marks)

Module -1
11.
a) Explain the following addressing modes with examples:
i) Indexed addressing
ii) Base register addressing
iii) Relative addressing
b) Illustrate the execution of the instruction MOV [R1], R2 in a single-bus organization, listing all control signals.

12.
a) Compare and contrast big-endian and little-endian byte ordering with examples.
b) Explain the multi-bus organization of a processor with a diagram and show how it improves performance over single-bus organization.

Module -2
13.
a) Design a 4-bit ALU that can perform AND, OR, XOR, and addition operations. Draw the logic diagram and function table.
b) Explain the purpose of status flags (Z, C, V, S) in a processor with examples.

14.
a) Design a combinational shifter circuit that can perform logical left, logical right, arithmetic right, and no-shift operations.
b) Explain processor organization using accumulator register with a diagram.

Module -3
15.
a) Explain Booth's multiplication algorithm with a flowchart and multiply (-6) × (+4) using this algorithm.
b) Explain the different types of pipeline hazards and their resolution techniques.

16.
a) Design a 4×4 array multiplier and explain its working.
b) Explain the concepts of pipeline speedup, efficiency, and throughput with formulas.

Module -4
17.
a) Compare hardwired and microprogrammed control units.
b) Explain the working of a microprogram sequencer with a diagram.

18.
a) Explain the one flip-flop per state method of designing a hardwired control unit.
b) Differentiate between horizontal and vertical microinstructions.
Module -5
19.
a) Explain the three cache mapping techniques with diagrams.
b) Explain the interrupt handling process in a processor.

20.
a) Compare SRAM and DRAM in terms of structure and characteristics.
b) Explain the different DMA transfer modes with their advantages.

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