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HDL Qns U2 and U3

The document outlines various topics related to Hardware Description Language (HDL) and Verilog, including design flow, program structure, and modeling styles. It includes exercises for designing digital circuits such as adders, multiplexers, and flip-flops, as well as discussions on finite state machines (FSMs) and their types. Additionally, it covers concepts like signal drivers, data types, and the use of initial and always blocks in Verilog.

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acech999
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4 views2 pages

HDL Qns U2 and U3

The document outlines various topics related to Hardware Description Language (HDL) and Verilog, including design flow, program structure, and modeling styles. It includes exercises for designing digital circuits such as adders, multiplexers, and flip-flops, as well as discussions on finite state machines (FSMs) and their types. Additionally, it covers concepts like signal drivers, data types, and the use of initial and always blocks in Verilog.

Uploaded by

acech999
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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UNIT -2

SEC -A

1. Discuss the steps involved in the design flow of HDL


2. Write the structure of HDL program
3. Define Constant in Verilog HDL
4. Enlist the Difference between top-down and bottom-up design methodology
5. Define module in Verilog HDL
6. Elaborate the nets with example in Verilog HDL
7. How vectors can be declared in Verilog HDL?
8. Differentiate between the different types of modeling styles in Verilog HDL
9. Illustrate Transport delay in Verilog HDL
10. List out the various data types in Verilog HDL
11. Discuss the RTL description with example in Verilog HDL
12. Explain the difference between input, output, and inout ports in Verilog.
13. How do you declare a 4-bit wire in Verilog? Provide an example.
14. List the common Verilog operators used in hardware description.
15. Describe the difference between the bitwise AND (&) and logical AND (&&) operators in Verilog.
16. Elaborate gate-level modeling in Verilog, and discuss its applications.
17. What is the purpose of procedural assignments in Verilog?
18. Describe the difference between initial and always blocks in Verilog.
19. Write a simple Verilog code to assign a value to a register inside an always block.
20. Define blocking (=) and non-blocking (<=) assignments in Verilog
21. When would you use non-blocking assignments instead of blocking assignments in sequential logic?
22. How does the behavior of blocking assignments differ from non-blocking assignments in an always block?
23. Explain how assign is used in data flow modeling in Verilog.
24. Write a Verilog code that continuously assigns a value to a wire using the assign statement.

SEC -B

1. Model a Full Adder with Enable input using HDL


2. Model a 3-8 Decoder with Enable input using HDL
3. Design and implement a 4:1 Multiplexer using case statements in Verilog HDL
4. Design and implement a 4-bit Full Adder using structural modelling
5. Discuss various types of signal drivers in detail with example
6. Design a BCD to Excess-3 encoder using HDL
7. Design a 1:4 De-mux using case statement in Verilog HDL
8. Design a 2-bit comparator using Verilog HDL
9. Design a Full-subtractor using Verilog HDL
10. Design a 2- bit Full adder using NAND gates only using Verilog HDL
11. Design a 7-segment decoder using Verilog HDL.
12. Design a Mod-10 counter using looping process statements

SEC – C

1. Design and implement Ring counter using Verilog HDL


2. Design and implement SR-flip flop using HDL
3. Design and implement D-flip flop using HDL
4. Design and implement T-flip flop using HDL
5. Design and implement Ripple counter using HDL using behavioral modelling
6. Design a 8:1 MUX using Gate Level Modeling using Verilog HDL
UNIT-3

SEC – A

1. Define Mealy Machine in FSM with example.


2. Define Moore's Machine in FSM with example.
3. Differentiate between Mealy and Moore's Machine in FSM.
4. Explain how does the output of a Moore machine depend on its states?
5. Design a 2-bit counter using any modelling style in Verilog HDL.
6. Design a basic 2 state Mealy machine using any modelling style in Verilog HDL.
7. Design a basic 2 state Moore's machine using any modelling style in Verilog HDL.
8. Design a 16-bit memory using any modelling style in Verilog HDL.
9. Discuss the difference between using the initial block and the always block for memory initialization in Verilog.
10. Design a clock of 20MHz frequency in Verilog HDL using any modelling style.
11. Design a 2-bit Full Adder in Verilog HDL using any modelling style.
12. Design a Verilog program that performs a bitwise AND operation on two 8-bit inputs.

SEC – B

1. Discuss the conditional assignments with suitable example in Verilog HDL.


2. Define sequential and parallel blocks in behavioral modeling in Verilog HDL.
3. Illustrate the use of initial and always blocks in Verilog HDL with examples.
4. Design a 4:1 Multiplexer using Case statement in Verilog HDL. Also provide the circuit diagram.
5. Design a 4-bit counter in behavioral modeling in Verilog HDL with block diagram.
6. Design a J-K Flip Flop in Verilog HDL with block diagram and truth table.
7. Design a 4:1 Multiplexer using If-Else Statements in Verilog HDL with circuit diagram and truth table.
8. Illustrate the different types of delays with syntax and examples in Verilog HDL.

SEC – C

1. Design a 4-bit up-counter with a clock enable signal. The counter should only increment when the clock enable
(en) signal is high. If the reset signal is high, the counter should reset to zero.
2. Design a 4-bit ALU (Arithmetic Logic Unit) in Verilog that supports addition, subtraction, AND, OR, and XOR
operations with its test bench.
3. Explain how you would write a Verilog module for a 4-bit up-counter using the always block with a clock signal.
Provide the Verilog code and describe the working of the counter in detail.
4. Design a 7-to-1 multiplexer in Verilog. Write the Verilog code and explain how the selection lines control the
output based on the input signals. Provide an example for a given input combination.
5. In Verilog, how does the case statement work in a finite state machine (FSM)? Given a basic 2-state FSM, analyze
the state transitions and provide the Verilog code for it. Discuss the advantages and disadvantages of using case
statements for FSMs in Verilog.
6. Evaluate the differences between structural and behavioral Verilog coding styles. Write a 4-bit AND gate using
both approaches and discuss the advantages and limitations of each style.

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