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23EC3ESHDL

This document outlines the examination details for the HDL Programming course at B.M.S. College of Engineering for the April 2024 semester. It includes instructions for answering questions, a breakdown of units with specific questions related to Verilog programming, and requirements for designing various digital circuits. The exam consists of five questions, with students required to select one from each unit, covering topics such as flip-flops, multipliers, counters, and finite state machines.

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21 views2 pages

23EC3ESHDL

This document outlines the examination details for the HDL Programming course at B.M.S. College of Engineering for the April 2024 semester. It includes instructions for answering questions, a breakdown of units with specific questions related to Verilog programming, and requirements for designing various digital circuits. The exam consists of five questions, with students required to select one from each unit, covering topics such as flip-flops, multipliers, counters, and finite state machines.

Uploaded by

tejaravi1611
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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U.S.N.

B.M.S. College of Engineering, Bengaluru-560019


Autonomous Institute Affiliated to VTU

April 2024 Semester End Main Examinations

Programme: B.E. Semester: III


Branch: Electronics and Communication Engineering Duration: 3 hrs.
Course Code:23EC3ESHDL Max Marks: 100
Course: HDL Programming

Instructions: 1. Answer any FIVE full questions, choosing one full question from each unit.
2. Missing data, if any, may be suitably assumed.

UNIT - I CO PO Marks
Important Note: Completing your answers, compulsorily draw diagonal cross lines on the remaining blank

1 a) Discuss the rules to be followed while connecting the Verilog CO1 PO 5


ports with an example code. 1

b) Discuss the difference between Monitor and Display statements CO 1 PO 1 4


with example.
c) Design a 4-bit T flip-flop based Ripple- Carry counter using top- CO 3 PO 3 11
down design methodology. Also write the test bench to generate
pages. Revealing of identification, appeal to evaluator will be treated as malpractice.

clock and reset inputs.


UNIT - II
2 a) Design a 2x2 unsigned array multiplier using Verilog data flow CO 3 PO 3 8
description. Also write the test bench to test the functionality.
b) Analyze the given Verilog code, Initial value of A=1, B=0, C=0, CO 2 PO 2 8
and G=0. ‘A’ changes from 1 to 0 and ‘B’ changes from 0 to 1 at
time T0. ‘C’ changes from 0 to 1 at T1 . ‘G’ changes from 0 to 1
at T2. Given T0 = 100ns : T1 =200ns : T2 = 300ns. Output ‘Y’
will have changes at T0+Δ1 ,T1+Δ2,T2+Δ3. Find Δ1, Δ2, Δ3 in
terms of ns.

c) Develop a Verilog gate level model for the 4X1 Multiplexer using CO 1 PO 1 4
its gate structure.
UNIT - III
3 a) Design a N-bit Magnitude Comparator using Full-adder, write a
Verilog code for a N- bit Magnitude Comparator Using Generate CO 3 PO 3 10
statement. Draw all the required logic diagrams.
b) Explain the structure of various loop statements in HDL with - - 6
syntax and example code.
c) Develop a Serial-In-Serial-Out shift register using always CO 3 PO 3 4
statement.
OR
4 a) Design an 8-bit counter by using a forever loop, named block, and CO 3 PO 3 10
disabling of named block. The counter starts counting at count =
4 and finishes at count = 68. The count is incremented at positive
edge of clock. The clock has a time period of 10. The counter
counts through the loop only once and then is disabled.
b) Explain the blocking and non-blocking statements used in Verilog - - 6
with example.
c) Develop a JK Flip-flop by applying Verilog case statement on CO 3 PO 3 4
output q.
UNIT - IV
5 a) Analyze the following snippet of Verilog code, write the complete CO 2 PO 2 6
Verilog description and interpreted logic diagram with
combination of multiplexers and gates.

b) With flow diagram, explain the RTL to gate level logic synthesis - - 6
flow.
c) Analyse the below given Verilog snippet, write the synthesed logic CO 2 PO 2 8
diagram and complete code. Assume X is a 2-bit vector.
always @ (X)
begin
Y = 2 * X + 3;
end
UNIT - V
6 a) Design a Verilog Moore FSM with one input X and one output Z. CO 3 PO 3 10
The FSM asserts its output Z when it recognizes the following
input sequence:”1011”. The machine will keep checking for the
proper bit sequence and does not reset to the initial state after it
recognized the string. Also write the test code to test the
functionality of the design.
b) Explain the FPGA Architecture with the help of block diagram - - 10
OR
7 a) Design a Moore-type serial adder using Verilog behavioral CO 3 PO3 10
description.
b) Explain the FPGA design flow with block diagram. - - 10
******

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