ADVANCED

DIGITAL
SYSTEM
DESIGN
Dr. Dipali Borakhade
Assistant professor
St. Vincent Pallotti college of engineering
and technology , Nagpur
 Programming language

 • Can we use C or Java as HDL?

 The main difference between HDL and Software Language is that HDL
describes the behaviour of digital systems while Software Language
provides a set of instructions for the CPU to perform a specific task.

 • A computer programming language

 – Semantics (“meaning”)

 – Syntax (“grammar”)
q A hardware description language (HDL) is a programming
language used to describe the behavior or structure of
digital circuits (ICs).
q HDLs are also used to stimulate the circuit and check its
response.
q Many HDLs are available, but VHDL and Verilog are by far
the most popular.
 Two HDLs used today
– VHDL and Verilog
Bo t h V H D L a nd V erilo g a re o f f ic ia lly endo rs ed IEE E
(Institute of Electrical and Electronics Engineers) standards.
Other HDLs include JHDL (Java HDL), and proprietary
HDLs such as Cypress Semiconductor Corporation's Active-
HDL.
– Syntax and ``appearance'' of the two languages
are very different
– Capabilities and scopes are quite similar
– Both are industrial standards and are supported
by most software tools. Most CAD tools available in
the market support these languages.
 VHDL
– VHDL: VHSIC (Very High Speed Integrated Circuit) HDL
– Initially sponsored by DoD as a hardware documentation
standard in early 80s
– Transferred to IEEE and ratified it as IEEE standard 1176 in
1987 (known as VHDL-87)
– Major modification in ’93 (known as VHDL-93)
– Revised continuously
VHDL Benefits
Public Standard
Supports a variety of design methodologies
1. Behavioral modeling
2. Dataflow or RTL Modeling
3. Structural or gate level modeling
It supports various design methodologies like Top-
down approach and Bottom-up approach.
It provides a flexible design language.
It allows better design management.
It allows detailed implementations.
It supports a multi-level abstraction.
It provides tight coupling to lower levels of design.
A VHDL model (program) consists of two design units:
1.Primary design unit.
2.Secondary design unit.
The primary design unit consists of
•Entity
•Package
•Configuration
The secondary design unit consists of
•Architecture
•Package body
q It describes the inputs and outputs of the circuit.
q It as a black box which you can see from outside only.
q So, by looking at it, you only get the information about
inputs and outputs and not really the inside.
q The entity syntax is keyword “entity”, followed by entity name and the
keyword “is” and “port”.
q Then inside parenthesis there is the por ts declaration. In the
port declaration there are port name followed by colon, then port
direction (in/out in this example) followed by port type.

entity entity_name is
generic (generic_list);
port (port_list);]
end entity entity_name;
Entity and_3 is
Port ( a,b,c : in std_logic;
z: out std_logic);
End and_3;
Entity full_adder is
Port ( A : in std_logic;
B : in std_logic;
Cin : in std_logic;
Sum : out std_logic ;
Cout : out std_logic);
End full_adder;
 Architecture

Stuctural Behavioral Dataflow Mixed

It describes the innards of the circuit. What actually is
happening from those inputs and how it generates the
output. It describes the working/functionality of the circuit.
To model the architecture of an entity, we have several
modeling methods:
1.Dataflow
2.Behavioral
3.Structural
4.Mixed
q In behavioral modeling, we describe the functionality of an entity using
sequential statements. Behavioral modeling is the highest abstraction layer in
VHDL. A process is a primary mechanism of writing architecture in the
behavioral style of modeling.

q In the Dataflow modeling style, we define the flow of signal/information

throughout the entity. Dataflow modeling is an intermediate abstraction layer.
The concurrent statements are the primary mechanism in this style of
modeling.
q In structural modeling, we define the architecture of the entity using the
interconnection of components. Every gate/buffer is also treated as a
component. This is an advantage as you have to write a code block once and can
use it as many times as you want to. But due to the use of components, this
modeling style is at the lowest level of abstraction.

q In mixed modeling, we combine the feature all modeling style, and this comes as
an advantage. We can use all the optimum features from all the modeling styles.
This gives an edge to mixed modeling. Hence, it is also a much more popular
modeling style in developers.
entity half_adder is
port (a, b : in BIT;
sum, carry : out BIT );
end half_adder;

architecture arch_HA of half_adder is

begin
sum <= a xor b;
carry <= a and b;
end arch_HA;
Configuration
An entity can have multiple architectural bodies associated with it. Now, to
create an entity and which uses an architecture body from another entity,
configuration is used.
So, configuration bind an architecture body from an entity to another entity.

The configuration for two purposes:

q To bind architecture from one entity to another, or
q To bind a component from architecture to another entity.
 Package

q In VHDL, packages stores common declarations like functions, procedures,

components, types use them in our other designs too.

q The primary purpose of a package is to collect elements that can be shared

(globally) among two or more design units. It contains some common data types,
constants, and subprogram specifications.

q Packages define global information t hat can be used by several entities

A package may consist of two separate design units :
q a package declaration and
q a package body.

q A package declaration declares all the names of items that will be

seen by the design units that use the package.
q A package body contains the implementation details of the
subprograms declared in the package declaration.
VHDL

1. VHDL is not case sensitive

2. Identifier must start with a letter
3. All statements end with a semi-colon
4. Comments precede with (--)
5. “<= “ - signal assignment
6. “:=“ - variable assignment
7. Variables are like C- type variables.
8. Signals have a one time value set associated to it at any time.
STANDARD LIBRARIES

 Include library ieee; before entity declaration.

 ieee.std_logic_1164; defines a standard for designers to use in describing
interconnection data types used in VHDL modeling.
 ieee.std_logic_arith; provides a set of arithmetic, conversion, comparison
functions for signed, unsigned, std_ulogic, std_logic, std_logic_vector.
 Ieee.std_logic_unsigned; provides a set of unsigned arithmetic, conversion,
and comparison functions for std_logic_vector.
 See all available packages at http://www.cs.umbc.edu/portal/help/VHDL/stdpkg.html
 ARCHITECTURE

 Architecture defines the functionality of the entity.

 It forms the body of the VHDL code.
 An architecture belongs to a specific entity.
 Various constructs are used in the description of the architecture.

architecture architecture_name of entity_name is [declarations ]

begin
concurrent statements
end architecture_name;
 ENTITY
• An entity declaration describes the interface of the component. Avoid using Altera’s primitive names
which can be found at c:/altera/91/quartus/common/help/webhelp/master.htm#

• PORT clause indicates input and output ports.

• An entity can be thought of as a symbol for a component.

 PORT DECLARATION
• PORT declaration establishes the interface of the object to the outside world.
• Three parts of the PORT declaration
• Name
• Any identifier that is not a reserved word.

• Mode
• In, Out, Inout, Buffer

• Data type
• Any declared or predefined datatype.

• Sample PORT declaration syntax:

Library ieee;
Use ieee.std_logic_1164.all;

entity andgate is
port (a : in std_logic;
b : in std_logic;
c : out std_logic );
end andgate;
architecture dataflow of andgate is
Begin
c <= a and b;
end dataflow;
WRITE VHDL CODE FOR HALF ADDER USING DATAFLOW TYPE OF
MODELING

Library ieee;
Use ieee.std_logic_1164.all;

Entity HA is
Port (a,b : in std_logic;
sum, cout :out std_logic);
End HA;

Architecture dataflow of HA is
Begin
Sum<= a xor b ;
Carry <= (a and b) ;
End dataflow;
WRITE VHDL CODE FOR FULL ADDER USING DATAFLOW TYPE OF
MODELING

Library ieee;
Use ieee.std_logic_1164.all;
Entity FA is
Port (a,b,c : in std_logic;
sum, carry :out std_logic);
End FA;
Architecture dataflow of FA is
Begin
Sum<= a xor b xor c ;
Carry <= (a and b) or (a and c) or (b and c); Sum = a xor b xor cin
End dataflow; Carry_out = ab + acin + bcin
WRITE ENTITY FOR 4:1 MULTIPLXER
Library ieee;
Use ieee.std_logic_1164.all;

Entity mux4 is
Port ( I : in std_logic_vector ( 3 DOWNTO 0);
S : in std_logic_vector ( 1 downto 0);
y : out std_logic);
End mux4;
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