Digital System Design

ET6
02T

Dr. Dipali Borakhade

Assistant professor
St. Vincent Pallotti college
of engineering and
technology , Nagpur
 Concurrent vs. Sequential Signal Assignment Statements

Concurrent Signal Assignment Sequential Signal Assignment

1) Ordering of the statement is not important and 1) These are executed serially one after the other. Final
architecture body can contain any number of output depends on order of statements.
statements
2) These are event triggered statements. i.e. whenever 2) These are not event triggered and are executed in
there is an event on signal, the statement is executed. sequence in relation to other sequential statements.

3) The statement that appears outside the process body 3) Signal assignment statement that appears within the
are called concurrent signal assignment statement. process body are called sequential signal assignment
statement
 VHDL Behavior

Sequential Statement
Concurrent Statement
 VHDL Behavior
Sequential Statement
Concurrent Statement
If –else Statement

Case Statement
When –Else Statement
Loop Statement
With –Select Statement
Next Statement
Process Statement Wait Statement

Exit Statement

Assert Statement

Return Statement

Null Statement
 VHDL Behavior continued

q VHDL provides concurrent statements for parallel operations or abstract models

for a circuit in a behavioral manner.
q These statements can be executed by a simulator at the same simulation time.
q The process statement is the primary concurrent statement in VHDL.
q The process contains sequential statements that define the step-by step behavior
of the process and describes the behavior of an architecture.
 Process Statement

q A process statement is concurrent statement itself

q The VHDL process syntax contains:
§ sensitivity list
§ declarative part
§ sequential statement section
q The process statement is very similar to the classical programming language.
The code inside the process statement is executed sequentially. The process
statement is declared in the concurrent section of the architecture, so two
different processes are executed concurrently.
 Process Statement

q Process statement is the primary mechanism

process_label : Process (sensitivity_list) used to model the behavior of an entity.
-- declarative part
begin q The statements appearing within the statement
-- sequential statement part are sequential statements and are
-- sequential statement
-- sequential statement executed sequentially.
end process process_label; q The process label is optional, you can avoid
using the label
 Process Statement

q All processes in an architecture behave concurrently.

q In the process sensitivity list is declared on all the signal to which the
process is sensitive to. In fact the process is evaluated any time a
transaction is scheduled on the signal.
q The final output depends on the order of the statements, unlike
concurrent statements where the order is inconsequential .
 If - else Statement

q An if- elsif- else statement contains at least one Boolean condition (specified after
the if keyword). The remaining conditions are specified with
the elsif clause. The else clause is treated as elsif true then.
q The choice depends on one or more conditions.
q Conditions are evaluated one by one until any of them turns to be true or there are
no more conditions to be checked for.
q When a condition is true then the sequence of statements specified after
the then clause is executed. If no condition is met then the control is passed to the
next statement after the if statement.
 If - else Statement

if condition_1 then
sequential statements
elsif condition2 then
sequential statements
else sequential statements
end if;
Write the VHDL Code for half Adder using
Behavioral type of Modeling
library ieee;
use ieee.std_logic_1164.all;
entity halfadder2 is
port(a, b : in std_logic;
s, c : out std_logic);
end halfadder2;
architecture behavioral of halfadder2 is
begin
p1: process(a,b)
begin
if (a=‘0’ and b=‘0’) then
s <= '0'; c <= '0';
elsif (a=‘0’ and b=‘1’) then
s <= '1'; c <= '0';
elsif (a=‘1’ and b=‘0’) then
s <= '1'; c <= '0';
elsif (a=‘1’ and b=‘1’) then
s <= '0'; c <= '1';
end if;
end process; end behavioral;
Write the VHDL Code for FULL Adder using
Behavioral type of Modeling
 elsif (a=‘0’ and b=‘0’and cin=‘1’) then
s <= '1'; cout <= '0';
elsif (a=‘0’ and b=‘1’ and cin=‘0’) then
library ieee; s <= '1'; cout <= '0';
use ieee.std_logic_1164.all; elsif (a=‘0’ and b=‘1’ and cin=‘1’) then
entity fulladder is s <= '0'; cout <= '1';
port(a, b,cin : in std_logic; elsif (a=‘1’ and b=‘0’ and cin=‘0’) then
s, cout : out std_logic); s <= ‘1'; cout <= ‘0';
end fulladder; elsif (a=‘1’ and b=‘0’ and cin=‘1’) then
architecture behavioral of fulladder is s <= '0'; cout <= '1';
begin elsif (a=‘1’ and b=‘1’ and cin=‘0’) then
process(a,b,cin) s <= '0'; cout <= '1';
begin elsif (a=‘1’ and b=‘1’ and cin=‘1’) then
if (a=‘0’ and b=‘0’ and cin=‘0’) then s <= ‘1'; cout <= '1';
s <= '0'; cout <= '0'; end if;
end process;
end behavioral;
Write the VHDL Code for 4:1 multiplexer
using Behavioral type of Modeling
 architecture bhv of mux_4to1 is
begin
library IEEE; process (S0,S1)
begin
use IEEE.STD_LOGIC_1164.all; if (S0 ='0' and S1 = '0') then
entity mux_4to1 is Z <= A;
elsif (S0 =‘0' and S1 = ‘1') then
port( A,B,C,D : in STD_LOGIC; Z <= B;
S0,S1: in STD_LOGIC; elsif (S0 =‘1' and S1 = ‘0') then
Z <= C;
Z: out STD_LOGIC ); elsif (S0 =‘1' and S1 = ‘1') then
end mux_4to1; Z <= D;
end if;
end process;
end bhv;
 architecture bhv of mux_4to1 is
begin
process (I,S) is
begin
library IEEE;
if (S=“00”) then
use IEEE.STD_LOGIC_1164.all; Z <= I(0);
Elsif (S=“01”) then
entity mux_4to1 is
Z <= I(1);
port( I : in STD_LOGIC_vector(3 downto 0); Elsif (S=“10”) then
Z <= I(2);
S: in STD_LOGIC_vector(1 downto 0);
Else
Z: out STD_LOGIC ); Z<= I(3);
end if;
end mux_4to1;
end process;
end bhv;
Write the VHDL Code for 8:1 multiplexer using
Behavioral type of Modeling

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity mux8to1 is
port( I : in STD_LOGIC_vector(7 downto 0);
S: in STD_LOGIC_vector(2 downto 0);
Z: out STD_LOGIC );
end mux8to1;
architecture bhv of mux8to1 is Elsif (S=“110”) then
begin Z <= I(6);
process (I,S) Elsif (s=“111”) then
begin Z<= I(7);
if S=“000” then end if;
Z <= I(0); end process;
Elsif S=“001” then end bhv;
Z <= I(1);
Elsif S=“010” then
Z <= I(2);
Elsif S=“011” then
Z <= I(3);
Elsif (S=“100”) then
Z <= I(4);
Elsif (S=“101”) then
Z <= I(5);
Write the VHDL Code for 1:8 Demultiplexer
using Behavioral type of Modeling
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Demux8to1 is
port(din : in STD_LOGIC;
S: in STD_LOGIC_vector(2 downto 0);
Z : out STD_LOGIC_vector(7 downto 0));
end Demux8to1;
architecture bhv of Demux8to1 is
begin Elsif (S=“101”) then
process (din,S) Z(5) <= Din;
begin Elsif (S=“110”) then
if (S=“000”) then Z(6) <= Din;
Z(0) <= Din; Else
Elsif (S=“001”) then Z(7) <= Din;
Z(1) <= Din; end if;
Elsif ( S=“010”) then end process;
Z(2) <= Din; end bhv;
Elsif (S=“011” )then
Z(3) <= Din;
Elsif (S=“100”) then
Z(4) <= Din;
 Case Statement
q The case statement selects for execution one of several alternative sequences of
statements; the alternative is chosen based on the value of the associated expression.
q The case statement contains a list of alternatives starting with the when reserved
word, followed by one or more choices and a sequence of statements.
q When all explicitly listed choices do not cover all the others choice must be used
because the choice statements must cover all the alternatives
case expression is
when choice => sequential_statements
when choice => sequential_statements
...
end case;
Case Statement
 Case Statement

All possible choices must be included, unless the others clause is used as the last choice:

case SEL is
when "01" => Z <= A;
when "10" => Z <= B;
when others => Z <= 'X';
end case;
 Write the VHDL Code for 4:1 multiplexer using CASE
Statement

process(i,sel)
library IEEE;
begin
use IEEE.STD_LOGIC_1164.ALL; case sel is
entity multiplexer4_1 is when "00" => Y <= i(0);
port ( i : in std_logic_vector(3 downto 0);
when "01" => Y <= i(1);
when "10" => Y <= i(2);
sel : in std_logic_vector(1 downto 0);
When “11” => Y<= i(3);
Y : out std_logic); when others => Y <= ’x’;
end multiplexer4_1; end case;
architecture Behavioral of multiplexer4_1 is
end process;
end Behavioral;
begin
 Design a component with following input and output
1) Using IF statement
2) using CASE statement

The Component should have following behavior

A(1:0)
Set Q
Q (1:0)
0 0 A XOR B C1

0 1 A OR B B(1:0)

1 0 A NOR B

1 1 A AND B
Set(1:0)
OTHERS “XX”
 1) Using IF statement

library IEEE;
use IEEE.STD_LOGIC_1164.all; elsif (set =“01”) then

entity component_1 is Q <= a or B;

Port ( A,B,Set : in std_logic_vector(1 downto 0); elsif (set =“10”) then

Q : out std_logic_vector(1 downto 0)); Q <= a nor B;

End component_1; elsif (set =“11”) then

architecture Behavioral of component_1 is Q <= a and B;

begin else

Process (a,b,set) Q<=“XX”;

begin End if;

if (set=“00”) then End process;

Q <= a xor B; End behavioral;

 2)Using CASE statement

architecture Behavioral of component_1 is

library IEEE;
begin
use IEEE.STD_LOGIC_1164.all;
Process (a,b,sel)
entity component_1 is
begin
Port ( A,B,Set : in std_logic_vector(1 downto 0);
Case set is
Q : out std_logic_vector(1 downto 0));
When “00” => Q <= A XOR B;
End component_1;
When “01” => Q <= A OR B;
When “10” => Q <= A NOR B;
When “11” => Q <= A AND B;
When others => Q <= “XX”;
End case;
End process;
End behavioral;
Write the VHDL Code for BCD to seven Segment Decoder
using CASE Statement
 When “0001” = > seg <= “0110000”;
library IEEE;
When “0010” = > seg <= “1101101”;
use IEEE.STD_LOGIC_1164.ALL;
When “0011” = > seg <= “1111001”;
entity bcd_7segment is
When “0100” = > seg <= “0110011”;
Port ( BCDin : in STD_LOGIC_VECTOR (3
When “0101” = > seg <= “1011011”;
downto 0);
When “0110” = > seg <= “1011111”;
Seg : out STD_LOGIC_VECTOR (6 downto 0));
When “0111” = > seg <= “1110000”;
end bcd_7segment;
When “1000” = > seg <= “1111111”;
Architecture behave of bcd_7segment is
When “1001” = > seg <= “1111011”;
Begin
When others = > seg <= “XXXXXXX”;
Process (BCDin )
End case;
Begin
End process;
Case BCDin is
End behave;
When “0000” = > seg <= “1111110”;
Design a priority encoder using if statement
 Design a priority encoder using if statement

elsif (D(6) = '1') then Y <= "110";

library IEEE;
elsif (D(5) = '1') then Y <= "101";
use IEEE.STD_LOGIC_1164.all;
elsif (D(4) = '1') then Y <= "100";
entity PRI_EN is
elsif (D(3) = '1') then Y <= "011";
port (D: In std_logic_vector (7 downto 0);
elsif (D(2) = '1') then Y <= "010";
Y: out std_logic_vector (2 downto 0));
elsif (D(1) = '1') then Y <= "001";
end PRI_EN;
elsif (D(0) = '1') then Y <= "000";
architecture behav of PRI_EN is
else
begin
Y <= "XXX";
process (D)
end if ;
begin
end process ;
If (D(7) = '1') then
end behav;
Y <= "111";
Write VHDL code for 3 bit comparator
 Write VHDL code for 3 bit comparator

process (A, B)
library IEEE;
begin
use IEEE.STD_LOGIC_1164.ALL;
G <= '0'; L <= '0'; E <= '0';
use IEEE.STD_LOGIC_ARITH.ALL;
If ( A = B ) then
use IEEE.STD_LOGIC_UNSIGNED.ALL;
E < = ‘ 1 ’;
Elsif ( A < B) then
entity COMPARATOR is
L<=‘1‘;
Port ( A ,B : in STD_LOGIC_VECTOR (2 downto 0);
Elsif ( A> B ) THEN
G,L,E : out STD_LOGIC);
G < = ‘ 1’ ;
end COMPARATORE;
End if;
architecture Behavioral of COMPARATOR is
End process;
begin
End behavioral;
 Write VHDL code for 1 bit ALU

B 1 bit ALU Y

En

OPCODE(1:0)
 Write VHDL code for 1 bit ALU
process (A, B,OPcode)
library IEEE;
Begin
use IEEE.STD_LOGIC_1164.ALL;
If (En = ‘1’) then
use IEEE.STD_LOGIC_ARITH.ALL;
If (OPCODE =“00” ) then
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Y <= A + B;
elsIf (OPCODE =“01”) then
entity ALU is
Y <= A - B;
Port ( A ,B ,En: in STD_LOGIC;
elsIf(OPCODE = “10”) then
Opcode : in STD_LOGIC_vector(1 downto 0);
Y <= A and B;
Y : out STD_LOGIC);
elsIf (OPCODE = “11” )
end ALU;
Y <= A or B;
architecture Behavioral of ALU is
End if;
begin
End if; End process; End
 Write VHDL code for 1 bit ALU
process (A, B,OPcode)
library IEEE;
Begin
use IEEE.STD_LOGIC_1164.ALL;
If (En = ‘1’) then
use IEEE.STD_LOGIC_ARITH.ALL;
Case OPCODE is
use IEEE.STD_LOGIC_UNSIGNED.ALL;
When “00” => Y <= A + B;
When “01” => Y <= A - B;
entity ALU is
When “10” => Y <= A and B;
Port ( A ,B ,En: in STD_LOGIC;
When “11” => Y <= A or B;
Opcode : in STD_LOGIC_vector(1 downto 0);
When others => Y <= “z”
Y : out STD_LOGIC);
End case;
end ALU;
End if;
architecture Behavioral of ALU is
End process;
begin
End behavioral;
Design BCD to Ex- 3 code converter using VHDL
Entity bcdtoex3 is
Port (a,b,c,d : in std_logic;
W,x,y,z : out std_logic);
End bcdtoex3;

Architecture dataflow of bcdtoex3 is

Begin
w <= (A or (b and c) or ( b and d);
X <= ((not b)and c) or ((not b)and d) or (b and (not c) and (not d));
Y <= c xor d;
Z <= not d;
End dataflow;