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Abhishek Sharma Resume

Abhishek Sharma is a software engineer with 5 years of experience in silicon solutions, specializing in cryptography and processor design. He holds a Master's degree in Electrical and Computer Engineering and has worked at Rambus and Intel, focusing on automation, microarchitecture, and hardware design. His skills include programming in Python, C, and C++, along with expertise in algorithms, data structures, and machine learning.

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4 views1 page

Abhishek Sharma Resume

Abhishek Sharma is a software engineer with 5 years of experience in silicon solutions, specializing in cryptography and processor design. He holds a Master's degree in Electrical and Computer Engineering and has worked at Rambus and Intel, focusing on automation, microarchitecture, and hardware design. His skills include programming in Python, C, and C++, along with expertise in algorithms, data structures, and machine learning.

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© © All Rights Reserved
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ABHISHEK SHARMA

San Jose, CA • (217)-721-8013 • abhisheksharma7827@gmail.com• GitHub • LinkedIn

Objective & Summary


Software engineer with 5 years of experience in silicon solutions ranging from cryptography accelerators and security solutions to x86 and
RISC-V processor. Solid understanding of data structures, algorithms, and distributed-system fundamentals. Passionate about applying
problem solving, programming, and scripting skills. Familiar with agile development and project management practices.

Education
Un iv er s it y o f I ll in o i s a t Ur b an a Ch am p ai gn , I ll in oi s Dec 2016
Master of Science in Electrical and Computer Engineering GPA: 3.77/4
In d i an In s ti tu te o f Tec h n o lo g y B o m b a y , India Aug 2014
Bachelor of Technology in Electrical and Computer Engineering with minor in Computer Science GPA: 9.43/10

Skills
• Python, C, C++ • Algorithms • Caches, Memory • Leadership
• Git, SVN • Data Structures • Micro-Architecture • Problem Solving
• Perl, Tcl • Parallel Programming • Computer Architecture • Time Management
• Operating Systems • Discrete Mathematics • Machine Learning • Cross-team Collab.

Work Experience
Ram b u s In c . Nov 2019-Present
De sign E ngi nee r, C ry pto grap hy Re sea rc h and S e c ur ity IP
• Development of elaboration, synthesis, and implementation scripts in Python
• Built infrastructure for running regressions and tools for internal checks using an open-source Python library
• Worked on the microarchitecture and design of Root of Trust (RoT) Security IP using Verilog and Perl
• Design of hardware cores performing cryptographic algorithms
• Devised microarchitecture for debug support in RISC-V processor inside RoT IP

In te l Cor p or at ion Sep 2016-Nov 2019


De sign E ngi nee r, P o w er Manage m ent IP
• Wrote automation script in Perl for improving efficiency in design schematic to description conversion
• Defined and developed micro-architecture of power up sequence for IP subsystem
• Designed and implemented different communication interfaces between IP and System on Chip
De sign E ngi nee r, Xeo n P hi CP U
• Developed features and model for pre-silicon validation team to test and debug architecture
Res ea rc h I nte rn, Inte l La bs May 2015-Aug 2015
• Developed Python tool for reading protocol descriptions and identifying trace signals for post silicon debug

Researc h Experience
Gr ad u a te R es ear ch Th e s is , U IU C Sep 2015-July 2016
Developed a graph-based algorithm to select signals for post-silicon observation in System on Chips (SoC)
• Represented the flow of protocol between different blocks in an SoC as graph
• Nodes represented the state of blocks that perform tasks and send messages to other blocks (edges)
• SoC with multiple protocols executing concurrently was represented by constructing a graph from the protocol graphs
• Constructed graph nodes represent state of SoC (tuple of each block) & edges represent a non-deterministic choice of transition
• The algorithm optimally selects a limited set of messages to be traced over the constructed graph
• Implemented the tool in Python and tested it on OpenSPARC T2 SoC from Oracle
Cach e M od e l l in g, U I UC Apr 2016-May 2016
• Developed a model of directory-based cache coherence protocol
• Used linear temporal logic (LTL) properties and assertions for performing model checking
Un d er gr ad u ate Th es i s , I IT B o m b a y Jan 2014-Apr 2014
• Implemented a Machine Learning based algorithm on Gem5 simulator for incorporating Dynamic Power Scaling in a processor
• Power stats from McPAT (tool) and stats from Gem5 simulator were given to an optimization algorithm
• ML algorithm was trained using power state chosen by the optimization algorithm and hardware stats from Gem5

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