Important Definitions

 At-speed clock: A pair of clock edges applied at the same effective cycle time as the full operating frequency of
the device.
 Capture clock/capture clock edge: The clock used to capture the final value resulting from the second vector at
the tail of the path.
 Capture vector: The circuit state for the second of the two delay test vectors.
 Critical path: A path with little or no timing margin.
 Delay path: A circuit path from a launch node to a capture node through which logic transition is propagated. A
delay path typically starts at either a primary input or a flip-flop output, and ends at either a primary output or a flip-
flop input.
 Detection, robust (of a path delay fault): A path delay fault detected by a pattern providing a robust test for the
fault.
 Detection, non-robust (of a path delay fault): A path delay fault detected by a pattern providing a non-robust
test for the fault.
 False path: A delay path that does not affect the functionality of the circuit, either because it is impossible to
propagate a transition down the path (combinationally false path) or because the design of the circuit does not make
use of transitions down the path (functionally false path).
 Launch clock/launch clock edge: The launch clock is the first clock pulse; the launch clock edge creates the
state transition from the first vector to the second vector.
 Launch vector: The launch vector sets up the initial circuit state of the delay test.
 Off-path input: An input to a combinational gate that must be sensitized to allow a transition to flow along the
circuit delay path.
 On-path input: An input to a combinational gate along the circuit delay path through which a logic transition
will flow. On-path inputs would typically be listed as nodes in the Path Delay definition file.
 Path: A series of combinational gates, where the output of one gate feeds the input of the next stage.
 Path delay fault: A circuit path that fails to transition in the required time period between the launch and capture
clocks.
 Scan clock: The clock applied to shift scan chains. Typically, this clock is applied at a frequency slower than the
functional speed.
 Test, non-robust: A pair of at-speed vectors that test a path delay fault; fault detection is not guaranteed,
because it depends on other delays in the circuit.
 Test, robust: A pair of at-speed vectors that test a path delay fault independent of other delays or delay faults in
the circuit.

1. What is sequential Depth in DFT? How does it improve coverage?

Ans: sequential depth is the number of capture cycles executed before unloading your scan chains.
so if your sequential depth was one, you would have a pattern sequence as follows:

1) set scan_enable, load scan chain, unset scan_enable

2) execute 1 capture clock
3) set scan_enable, unload scan chains.

FastScan performs clock sequential test generation if you specify a non-zero sequential depth.
Clock sequential identification selects scannable cells by cutting sequential loops and limiting sequential depth based
on the -Depth switch. Typically, this method is used to create structured partial scan designs that can use the FastScan
clock sequential ATPG algorithm.
Setting the -Sequential switch to either 0 (the default) or 1 results in patterns with a
maximum sequential depth of one, but FastScan creates clock sequential patterns only if the setting is 1 or higher.
The maximum allowable sequential depth is 255 (a typical depth would range from 2 to 5).
Coverage Improvement:
Testable faults become ATPG_untestable faults because of constraints, or limitations, placed on the ATPG tool (such
as a pin constraint or an insufficient sequential depth).These faults may be possible-detectable, or detectable, if you
remove some constraint, or change some limitation, on the test generator (such as removing a pin constraint or
changing the sequential depth).Also,(while using named capture procedure) gradually add more capture procedures
with higher sequential depth until the test coverage goal is achieved or the pattern count limit is reached.

2. What is robust / non_robust test for path delay faults?

Ans: Non -Robust tests:
A pair of at-speed vectors that test a path delay fault; fault detection is not guaranteed, because it depends on other
delays in the circuit.
Robust Tests:
A pair of at-speed vectors that test a path delay fault independent of other delays or delay faults in the circuit.

3. What are the techniques used to reduce pattern count without losing coverage?

Ans: The number of test patterns that you need to achieve full coverage depends on the design size. Different ATPG
tools offer different compression and pattern ordering techniques to help reduce pattern count.
Fault models beyond stuck-at typically require pattern counts that are much larger than those for stuck-at only.
For Pattern reduction, first step is the chain balancing during Stitching or scan insertion. If your chains are balanced,
Tool needs to insert less dummy patterns for reaching till required flop.
Also we can include compression on the chains where we have constraints on the pins of device. This means if we are
having the compression factor of 2 then your 1 scan chain will get divided into 2 inside the device reducing your
chain length (flops per scan chain).

4. Are the faults on the resets of the flops are detected? if so how are they detected?

Ans: Yes the faults on reset of the flop are detectable. It is detected in the following way
1) Define the reset pin as clock in the tdl
2) Let us assume that the reset of the flop is active low. Keep the reset as 'high' and scan in '1' in to the flop (during
this scan enable is 'high')
3)As we have scan-in '1' the Q of the flop will have '1'
4) Make the scan-enable 'low' and toggle the reset(i.e. make it low). This is allowed because we have declared the
reset as clock.
5) As reset is 'low' the flop need to get reset and whatever the value in the flop will become '0'
6) Then strobe for '0', while shifting-out the contents from the flop.
7) If the output while shifting out is '0', it means the reset pin of the flop is not stuck-at 1. Otherwise it is stuck at '1'.
Note:
1. In test mode all the flops should have a asynchronous reset.
2. The reset pins of all flops should be controllable from Top (Chip) level.
If your design contains a lot of synchronous reset flops. Then since during AC (transdly) testing these reset line faults
are not targeted for AC, Constraining the reset to off state is the best way.

5. If we provide controllability and observability to the ports of area under test, will it improve the test
coverage? If yes, how much %age of improvement can we see?

Ans: yes, we can see an improvement in coverage. Think about the bounding logic that we usually give for macros...
the improvement in coverage will depend on the initial coverage without bound and the no of faults in the design
under test.

6. When both the Transition-delay and path delay target for transition faults, why we should have two
different methods to detect the same?

Ans: Yes both Transition and Path delay will target the transition faults, but they are different in the following ways
1) Transition-delay is related to slow-to-rise or slow-to-fall faults at a particular node. Whereas path-delay is related
to slow-to-rise or slow-to-fall faults of a particular path.
2) The reason for transition-delay at a node is some manufacturing defect at that node (more resistive node). The
reason for path-delay is some manufacturing defect that is distributed throughout the path (more resistive path). Let
me explain this in detail with an example.
Let us assume that in a path there are some 10 nodes, and the transition delay at each node is that much less which
won't create any timing violation in the transition ATPG. But in path-delay these delays at each node might get
accumulated and result in not meeting the timing. So it is must to have path-delay besides Transition-delay.
Transition delay is similar to stuck-at atpg, except that it attempts to detect slow-to-rise and slow-to-fall nodes, rather
than stuck-at-0 and stuck-at-1 nodes. A slow-to-rise fault at a node means that a transition from 0 to 1 on the node
doesn’t produce the correct results at the maximum operating speed of the design. Similarly a slow-to-fall fault means
that a transition from 1 to 0 on a node doesn’t produce the correct results at the maximum speed of the design.
Transition delay fault targets single point defects.
The Path delay fault model is useful for testing and characterizing critical timing paths in the design. Path delay fault
tests exercise critical paths at-speed to detect whether the path is too slow because of manufacturing detects or
variations.
Path delay fault testing targets physical defects that might affect distributed region of a chip. For example, incorrect
field oxide thicknesses could lead to slower signal propagation times, which could cause transitions along a critical
path to arrive too late.
If we attain 100% coverage with transition atpg test then we don’t need to do the path delay test. But this is not the
case in most of our designs. Then how can we GUARANTEE that all the critical paths are targeted by Transition
ATPG
so we give the critical path to the atpg tool and tell it to generate patterns for it this is called path delay.

7. If for a DFT production set we have both PATH Delay and Transition patterns which scheme should be
done first?

Ans: Its always better to do Path_delay first and then the transition delay.
Path_delay- start flop and end flop are given by the user.(i.e) transition through a well-defined path-(More effective)
Transition-Start and end flop is decided by the tool,so trasition may happen through a shorter or longer path-(Less
effective)
1)path delay basically targets for all the critical paths in the design.
2)Generate the path_delay patterns for all the critical paths in the design and write down the faults for the same.
3)Generate the trans delay pattern by loading the faults on the path_delay, such that the faults detected in the
path_delay are not Re-targeted.
4)The major reason to follow the above sequence is in trans-delay we are not sure whether a transition has really
happened through the critical path.
(A)-If we do the transition-ATPG first, we are not sure whether the transition has happened through the critical
path,In such case we may not have pattern which may catch the fault through the critical path,but the fault may be
detected through some other shorter paths which may add the faults to the detected list.
(B)If we run a path_delay after the above step(A) then we may have a pattern for the critical path,but it leads to the
pattern redundancy because we have already a transition pattern for the same fault.

8. What do we mean by fault simulation in DFT terminology?

Ans: Fault simulation consists of simulating a circuit in the presence of faults ( logical faults ).
Comparing the fault simulation results with those of the fault-free simulation of the same circuit simulated with the
same applied test, we can determine the faults detected by that test.
There are several types of fault simulation techniques such as serial fault simulation , parallel fault simulation ,
deductive fault simulation e.t.

9. What is meant by coverage in DFT terminology?

Ans: The term coverage can be broadly classified as:

1. Fault Coverage: This is the total number of detected faults (doing testing) divided by the total number of faults in
the design.
2. Test coverage: This is the total number of detected faults divided by the number of testable faults in the design.
Testable faults are the faults in the design that can be tested and observed by the patterns used during testing.
Please note that, here the word "faults" refers to manufacturing defects, as DFT does not merely target functional
faults, but rather focusses on circuit structure.
Coverage Calculations are used to measure the effectiveness of test patterns and test generation for a given set of
faults.
A Basic AND Gate has six faults
SA1/SA0----Input-A
SA1/SA0----Input-B
SA1/SA0----Output-Y
Total faults for a basic AND gate is 6
Coverage calculation goes on how many faults we are able to detect on the same.
Test Coverage is a percentage detected of all detectable faults and gives the most meaningful measure of test pattern
quality.

10. What is IDDQ Testing? Why is it done?

Ans: IDDQ Testing can detect certain types of circuit faults in CMOS circuits that are difficult or impossible to detect
by other methods.
IDDQ testing, when used with standard functional or scan testing, provides an additional measure of quality
assurance against defective devices.
IDDQ testing refers to the integrated circuit (IC) testing method based upon measurement of steady state power-
supply current. Iddq stands for quiescent Idd, or quiescent power-supply current. Majority of IC’s are manufactured
using complementary metal–oxide–semiconductor (CMOS) technology. In steady state, when all switching transients
are settled-down, a CMOS circuit dissipates almost zero static current. The leakage current
in a defect-free CMOS circuit is negligible (on the order of few nano amperes). However, in case of a defect such as
gate-oxide short or short between two metal lines, a conduction path from power-supply (Vdd) to ground (Gnd) is
formed and subsequently the circuit dissipates significantly high current. This faulty current is a few orders of
magnitude higher than the fault-free leakage current. Thus, by monitoring the power-supply current, one may
distinguish between faulty and fault-free circuits.

Why do IDDQ Testing?

For functional testing, a tester applies a sequence of input data and detects the results in the sequence of output data.
Then, the output sequence is compared against the expected behavior of the device. An advantage of functional
testing is that it exercises the device as it would actually be used in the target application. However, this type of
testing has only a limited ability to tests the integrity of a device's internal nodes.
with functional testing only, an internal defect could slide by undetected.
The methodology for scan testing is all the sequential elements of the device are connected into chains and used as
primary inputs and primary outputs for testing purposes. Using automatic test-pattern generation (ATPG) techniques,
you have the capability to test a much larger number of internal faults than with functional testing alone. The goal of
ATPG is to set all nodes of the circuit to both 0 and 1, and to propagate any defects to nodes where they can be
detected by test equipment.

Using both functional and scan testing you greatly increases your odds at finding an internal defect, but what if the
defect is not controllable or can't be observed? That is where IDDQ testing can help.

11. Can you briefly describe the points to be considered, while re-ordering the scan chain in Physical Design?

Ans: Scan chain reordering needs to respect 3 important Logical constraints.

1. Clock domain timing constraints
2. User specified scan segment positions
3. Minimizing clock domain traversals
each active edge of each clock is considered to be in a separate clock domain. Both edges of a clock and clocks with
different timings may be used to control edge-triggered scan flip flops of a scan chain.
In order to construct functional scan chains, two consecutive scan flip flops A and B (A serially driving B)
1) must be clocked at the same time or
2) B must be clocked before A.
In the first case, we say that A and B have compatible clock domains.
In the second case, we say that A and B have incompatible clock domains.
The precedence relationship between scan flip-flops imposed by clock domain timings is translated at the scan
segment level. Capture and launch times for a scan segment are respectively deduced from the capture time of its first
scan cell (driven by its scan input) and the launch time of its last scan cell (driving its scan output). Therefore, the
precedence relationship between scan segments can be established, and thus respected during scan segments
reordering. User-specified scan segment positions are respected during scan reordering unless they violate clock
domain timing constraints.

The last constraint, minimizing clock domain traversals, takes priority on physical design information because we
want our approach to be minimally intrusive in term of adding synchronization latches. Only scan segments with
compatible clock domains are reordered.

Reordering a set of scan segments with compatible clock domains consists of:
1. identifying and marking the set of clusters containing the scan segments.
2. Determining the entry and exit points between which the scan segments are going to be reordered.
3. Ordering the previously identified clusters between the entry point and exit points.
4. Reordering scan segments within each of the ordered clusters.

12. What is stuck open kind of memory fault?

Ans: Stuck open fault in memory says that a particular memory cell is not accessible. A single physical line in a
circuit may be broken. The resulting unconnected node is not tied to either VCC or Gnd.
13. In my project we have 3 subchips. We have three DFT modes of operation. In each mode all the pins of
particular subchip will be accessible from Top level. During pattern generation I am facing chain blockage at
scan cell 0 for one particular mode. Please help me in debugging the issue.

Ans: There can be many reason for this.

1. The design that you are using might not be Scan Stitched.
2. You might not have declared the Clock
3. The asynchronous reset might not be constrained during shift procedure in your spf file (TETRAMAX) or
procedure file (Fastscan)
4. You might not have given proper constraints to input pins
5. Improper value of some dft mode control signals
For finding the exact issue. you have to analyze the error using the gui/schematic viewer of the tool
case 1 : You will find Q of the flop shorted with the SD of the same flop
case 2 : X at the clock port of the flop
case 3 : X at the reset port
case4 : You might see more than one input of a gate as X ; hence the tool will not know which path to follow
Case5 : you might see more than one input of a gate as X; hence the tool will not know which path to follow
Please check the I/O buffer which is used on the scan out is in output mode. else there will be a blockage at the scan
cell 0. Make sure that all the I/Os on the scan out port are in the output mode and all your scan-in pins in input mode.
Check the two things first,
1. the flop where it is blocked, there clock is coming properly or not
2. Reset for the same flop

14. Why first negative edge flops followed by positive edge flops in the scan chain?

Ans: This is not necessary to always have negative and positive edge triggerred flops in scan chain. Actually we can
have three combinations:
1) All positive
2) All negative
3) Negative followed by positive
but positive followed by negative is not taken. Since at the intersection of positive and negative flop the data will not
be captured. Since at single pulse data launch and capture is not possible. We will require lock up latch.
The rule is there should not be 2 shift during one clock period. So if you put +ve edge flop followed by -ve edge flop,
there is a chance of 2 shift (if the clock skew between 2 clocks is small) in one clock period. But if you put -ve edge
flop then +ve edge flop, then there is no chance of that. because the +ve edge come in the next period. Or if ur design
needs that +ve edge then -ve edge then you a lock up latch (if skew is small)
this depends on the nature of clock involved in your scan design.
Clock nature
1 : RTZ then chain should be : negedge ->posedge
2 : non RTZ thene it shoul be vice-versa
reason is value loaded on first flop shhuld not passed on to next FF in same cycle.

15. How the compression technique factor affects the Number of scan chains? Is number of Clock domains
also a factor?

Clock domains are a factor, yes, but sometimes people will combine clock domains into the same scan chain. That's
not uncommon, and will work if the clock skew is managed, and the tool puts lockup latches in there.
Compression affects the number of scan chains, of course, since more compression generally uses fewer external scan
chains.
The idea in test compression is to compress the amount of test data (both stimulus and response) that is stored on the
tester. This provides two advantages. The first is that it reduces the amount of tester memory that is required. The
second and more important advantage is that it reduces test time because less test data has to be transferred across the
low bandwidth link between the tester and the chip. Test compression is achieved by adding some additional on-chip
hardware before the scan chains to decompress the test stimulus coming from the tester and after
the scan chains to compact the response going to the tester.

16. How to meet coverage goals?

You need to review the untestable faults to determine why they are not getting covered.
The first thing to do is make sure that all the faults that should not be targeted by this test are dropped and not
considered for test coverage.
Then find the logic on your chip with the most untested faults. Pick one of the faults in this area and determine why
you can’t generate a test for it. You can use the interactive debugger to do this. You can manually create a test for this
fault and as you do this figure out what stops you and the ATPG. The interactive debugger might be able to help you
with this using it's analysis features.

17. Why should we force the bidis to Z? Can we not use these ports as scan_in and scan_out of our various
scan chains? If we use them, then how should we constrain them in the load_unload procedure? Will forcing
these ports to Z affect coverage? Will it mean that we cannot put any value on these lines thereby constraining
the tool to choose the other ports only for applying input stimulus?

This is normally done for just the bidis that are scan outputs. By constraining them to 'Z', it tells the tool that the pin is
working in output mode, and therefore it can then trace the scan chain properly (the chains are traced from output to
input).
While shifting you want to prevent conflicts on the non-scan port bidirect pins and to force the correct direction on
any pins that are used as scan ports.
You can force Zs on bidirec pins to prevent conflicts.
You have to add hardware and control signals to force the scan ports in the correct direction while shifting.
You can improve test coverage by adopting the TEI methodoly that LSI logic uses. They have a pin that forces all
bidirects to be off with the pin. The test are applied with strobe, wait and clock cycles (for stuck at tests).
The strobe cycle has all of the bidirects in the same direction as specified by the ATPG and the TEI pin is disabled.
The wait cycle applies Z to all the bidirect inputs and turns TEI on so all the bidirects will be in input mode.
In the clock cycle all bidirects are in input mode and you drive the values that were on the bidir busses from the input
pins and you apply the capture clock.
This prevents bidirect conflicts from affecting test coverage, so your coverage is higher and require fewer vectors.

18. when doing DFT scan insertion which of the following is true or is a better approach?

1. Up to three additional pins are required to implement this type of scan. Only the SCAN ENABLE pin must be
dedicated; the remainder of the pins(scan in, scan out) can be shared with primary inputs and outputs.
2. Up to four additional pins are required to implement this type of scan. Only the TEST MODE pin must be
dedicated; the remainder of the pins(scan en, scan in , scan out) can be shared with primary inputs and outputs.
First you will of course generally use more than one scan chain and often need more than one scan enable (SE) signal,
so your 3 and 4 pin statements don't really hold true. The real question you're asking is if the SE signal(s) must be
dedicated or not or can a TM signal be used so that the SE signal can be shared. The answer is that a TM signal can
indeed be used to share the SE signal(s). This is generally the prefered solution as very often the design requires other
internal test settings which mush be controlled by a dedicated TM signal.

19. Why Full Scan is considered combinational?

Now what I think about is that one can control the sequential part by using the scan path. This is done by clocking in
the needed sequence to set up the state of the machine and then applying the PIs (primary input vectors) to the
combinational inputs.
Thus you one can easily see the response of the machine without having to go through the state machine in its
originally specified way. Thus we become independent of the state machine in some way.
Thus using scan we 'reduce' the sequential machine problem down to a 'combinational' problem.
By definition, Full Scan means that ALL flip-flops in the design are converted into scan flops. When the scan-enable
signal is inactive, the flip-flops accept data from their functional inputs and the circuit behaves in its intended
sequential nature. When the scan-enable signal is active, all flip-flops accept data from their scan input, providing full
control on the values that get loaded into them. In this mode, all sequential depth is removed leaving only a
combinational circuit to test.

20. I have in my design 3 types of flops.

1. CLK domain posedge
2. CLK domain negedge
3. RCO_CLK domain posedge only.
Is it feasible/possible to put them in 1 scan-chain?

Yes, it is possible.
Assuming that CLK is a Return-to-Zero clock (0->1->0 pulse), you would stitch the negedge CLK domain flip-flops
before posedge CLK domain flip-flops, i.e., negedge CLK FFs are closer to scan input, and posedge CLK FFs are
closer to scan output.
RCO_CLK domain can be stitched at either end of the chain. However, if CLK has a significantly larger clock tree
than RCO_CLK clock tree, then it is better to put RCO_CLK domain FFs at the end of the chain. Otherwise, you may
need to skew your clock timing on the ATE.
This means your chain will look like this:
ScanIn -> negedge CLK -> posedge CLK -> RCO_CLK -> ScanOut

21. In transition fault detection process there should be two vectors - for intialization and for transition. I
want to understand when exactly they applied? Doesn't transition propagation vector corrupt initialization
vector? Can you please explain in steps?
Here are the steps followed during transition fault testing( Broadside)
1. Load scan chains
2.Force PI
3.pulse clock
4. Force PI
5.measure PO
6.pulse clock
7. unload/load scan chains
Clearly you see, not possible for the corrupting intialization vector.

22. Why latches (other than lock-up and clock gating) in design are bad for ATPG? We always loose
coverage by putting them on transparent mode by constraining enable signal. How can we increase this
coverage?

I think you answered your own question regarding why we lose coverage,
"putting them on transparent mode by constraining enable signal".
Any logic driving the enable signal will lose some coverage due to this constraint.
If the enable signal is driven by a large cone of logic, you can increase the coverage by adding a "force transparent
on" gate close to the enable of the latch, and add an observe flip-flop just before the added gate, so that most of the
faults in the logic cone can be recovered.
Without modifying the circuitry, recovering fault coverage in ATPG really depends on how these latches are used in
the functional path.

23. How PLL generates two at-speed clocks during launch and capture cycles of LOC at-speed testing? Is
there any circuitry which generates two pulses after scan loading?

Yeah, you have to design that circuitry, but it's design dependent.Many EDA companies now provide solutions for
this. Commercial on-chip solutions for LOS (launch-on-shift) based testing are also available.
I understood that there should be seperate clock control circuitry to select two at-speed clock pulses from free-
running PLLs for transition fault testing. What about stuck-at testing, in this case we need only one pulse from PLLs
to capture response. Will there be any signal to control this behavior of clock control circuitry?
Well, it's not strictly necessary to have on-chip control. You can source the clock from an I/O, just as long as your
ATE can handle the speed you need, and the device can distribute the clock well enough. The advantage of having
on-chip control is that you can use a slow tester.
As far as the stuck-at clock goes, remember, you're using the slow external clock to shift data through the scan chains.
For stuck-at, you can bypass the at-speed clock control and use only the slow external clock. Yes, you'd need a
control signal. You can also, if you want to increase your flexibility, and get better fault coverage, design your clock
control to be able to output 2, 3, or even 4 pulses, to catch faults that only get caught with sequential patterns. I've not
done it myself, but I've read about such designs.
Transition delay and path delay fault models both seek to describe defects which cause slow transitions on gate inputs
or outputs. The difference is that a path delay is more specific - the whole path, from point a to point b is specified.
It's a more stringent case than a transition fault. To detect a transition fault, it is only required that the ATPG
generates a pattern to propagate that fault to a scanned flop. The path selected may not be the worst case path.
Most people in the industry begin with transition faults, because the ATPG can generate patterns with decent
coverage more easily. Then if desired, those patterns are augmented with a much smaller set of path delays that are
determined to be critical (maybe those with the least margin as determined by the timing tool).

24. I need to know how to implement simulation about Bridge faults?I mean is the same way like stuck
simulation (for example to activation the stuck line with the opposite value) If no, then how to do the
simulation?

For bridging fault simulation, there are two things that are different from stuck-at:

1. Bridging fault list

2. Bridging fault behavior
It is impossible to use all pairs of nets/nodes in the gate level netlist as a bridging fault list in practical circuits, so
people typically extract physically adjacent nets (with perhaps some minimum length of adjacency) to be fault sites.
In absence of physical information, some folks tried logical proximity with varied degrees of success.
When two nets are bridged together, and the two nets were driven to different logic levels, the result logic depends
on:
1. The drive strength of the cells driving the 2 bridged nets
2. The bridge resistance
3. The logic threshold of the cells inputs driven by the bridged nets
Some simplistic models that are often used to model the faulty behavior are wired-AND, wired-OR, A-dominate, B-
dominate, or some other combination of these models.

25. what is the difference between sequential and combinational atpg?

Combinational ATPG simulate one clock pulse on the circuit. Sequential ATPG simulate multiple pulses.

26. What is parallel scan chain loading for simulation? Do we force scan in values for parallel loading?
How it works? How it is different from serial loading?
parallel scan chain loading means forcing the scan in port of the flops parallely.
serial loading means Serial shift register. first serially shift in the values into the registers by pulsing the clocks(no of
flops)
When running atpg pattern on to a scan inserted netlist in a commerical testing tools. Is there any I can find out which
atpg pattern is sent into which scan chain of the scan-netlist.
When dealing with test data compression, it's hard to know exactly which chain is being tested at any one time. Some
tools may be able to report which chain(s) are tested for a given pattern, but then the answer may come back that
several chains were being tested at once.
It would be different for straight-ahead scan, because you know exactly what path the data takes as it goes in and
comes out of the scan chains.

27. How does "scan compression logic (XPAND + X-Compact)" work ? Can it generate any arbitrary test
vector ?
Both XPAND and X-Compact techniques are based on combinational logic( XOR gate). It can use test patterns
generated from any atpg tool. XPAND works on Illinois scan idea. The problem is that when there are X's present at
the X-Compact end, test coverage gets reduced.

X-Compact: X-compact is an X-tolerant response compaction technique that has been used in several designs. The
combinational compactor circuit designed using the X-compact technique is called an X-compactor. Figure 6.24
shows an example of an X-compactor with 8 inputs and 5 outputs. It is composed of 4 3-input XOR gates and 11 2-
input XOR gates. The X-compactor can be represented as a binary matrix (matrix with only 0’s and 1’s) with n rows
and k columns; this matrix is called the X-compact matrix. Each row of the X-compact matrix corresponds to a scan
chain and each column corresponds to an X-compactor output. The entry in row i and column j of the

matrix is 1 if and only if the jth X-compactor output depends on the ith scan chain output; otherwise, the matrix entry
is 0. The corresponding X-compact matrix M of the X-compactor shown in Figure 6.24 is:
For a conventional sequential compactor, such as a MISR, there are two sources of aliasing: error masking and error
cancellation. Error masking occurs when one or more errors captured in the compactor during a single cycle
propagate through the feedback path and cancel out with errors in the later cycles. Error cancellation occurs when an
error bit captured in a shift register is shifted and eventually cancelled by another error bit. The error cancellation is a
type of aliasing specific to the multiple-input sequential compactor. Because the X-compactor is a combinational
compactor, it only results in error masking. To handle aliasing, the following theorems provide a basis for
systematically designing X-compactors.
Theorem 6.3
If only a single scan chain produces an error at any scan-out cycle, the X-compactor is guaranteed to produce errors at
the X-compactor outputs at that scan-out cycle, if and only if no row of the X-compact matrix contains all 0’s.
Theorem 6.4
Errors from any one, two, or an odd number of scan chains at the same scan-out cycle are guaranteed to produce
errors at the X-compactor outputs at that scan-out cycle, if every row of the X-compact matrix is nonzero, distinct,
and contains an odd number of 1’s. If all rows of the X-compact matrix are distinct and contain an odd number of 1’s,
then a bitwise XOR of any two rows is nonzero. Also, the bitwise XOR of any odd number of rows is also nonzero.
Hence, errors from any one or any two or any odd number of scan chains at the same scan-out cycle are guaranteed to
produce errors at the compactor outputs at that scan-out cycle. Because all rows of the X-compact matrix of Figure
6.16 are distinct and odd, then by Theorem 6.2 simultaneous errors from any two or odd scan chains at the same scan-
out cycle are guaranteed to be detected. The X-compact technique is nonintrusive and independent of the test patterns
used to test the circuit. Insertion of the X-compactor does not require any major change to the ATPG flow; however,
the X-compactor cannot guarantee that errors other than those described in Theorem 6.3 and Theorem 6.4 are
detectable.

28. What is difference between launch on shift and launch on capture? Advantage and disadvantage of
each?
AC scan test is a 2 pattern test, the first pattern launches a transition at the source flip-flop(s), and the second captures
the transition at the destination flip-flop(s). Hence, we need two clock pulses for each AC test.
There are two ways to achieve this.
In LOS test patterns, scan data is loaded through scan chains. Nodes in a CUT are initialized at the last shift
clock. In order to make transitions and capture the response of a CUT, scan enable signal must go from 1 to 0, and
capture clock is applied subsequently. Because scan enable signal changes between launch and capture clock, which
is applied at system speed, scan enable signal should be designed to operate at system speed. Due to this design
restriction, LOC test patterns are more frequently used.
In LOC test patterns, scan enable signal does not need to operate at system speed. Once scan data is loaded through
scan chains, scan enable signal transitions to 0. Subsequently, launch and capture clock are applied. Launch vector
should be calculated from the response of a CUT at the capture clock because launch and capture clock are
applied while scan enable is low. Due to this restriction, LOC test set suffers from large test set size and low fault
coverage compared to LOS test set. In addition, it requires more ATPG computation and restrictions than LOS test set
whose launch vector is simply shifted in.

In general, to make sure the transition reaches the capture flip-flop in time, the delay between the launch and capture
cycles should be your cycle time (or the actual path delay, for those who run transition tests faster than at-speed).

As you can see, to run LOS at-speed, your scan enable must switch at-speed also. This is usually problematic in
layout, since you need to either treat the scan enable signal as a clock net (require clock tree synthesis with accurate
delay/skews), or pipeline the scan enable signal, which increases the area/complexity of your scan enable.

I have seen publications that claim either LOS gives you higher transition fault coverage than LOC, or vice versa. I
believe this is design dependent, and it depends on the complexity of the logic cone(s) driving the source flip-flop(s).
If the logic cone(s) are simple, it gives ATPG a greater degree of freedom to generate the appropriate 2nd pattern in
LOC. Notice that the 2nd pattern in LOS is always 1 bit shifted from the 1st pattern. On the other hand, if the cone is
complex, it may be hard to generate the appropriate 2nd pattern through the logic, making LOS coverage numbers
more attractive.

29. How to toggle reset to get coverage?

If the reset is asynchronous (and properly bypassed during scan), you can declare the reset pin as a clock during
ATPG, and ATPG will toggle it accordingly to get faults on reset pin.
If the reset is synchronous, you can treat the reset pin as a normal data pin, and ATPG should be able to cover faults
on the reset.

Be careful, however, if you run transition fault ATPG. Reset usually cannot toggle at-speed, so you may not want to
declare the reset as a clock when running transition fault ATPG.
You can also try to run the patterns that toggle the reset as a clock pin at a reduced speed on the tester, if you worry
about transition fault coverage on reset.
30. What is a BUS Primitive and clock_PO pattern?

A bus primitive is just a DFT model of a bus - a net that has more than one driver. It's important that you constrain it
during test.
A clock PO pattern is a pattern that measures a primary output that has connectivity to a clock. So if a clock signal
propagates through combinational logic to a primary output (PO), an ATPG vector can be created to measure the
results of that propagation.

31. Why do we go for toggle fault modeling? I think suck-at model also detects the faults which are detected
by toggle fault model. How tester applies patterns during toggle fault detection?

Toggle faults are used mostly for code coverage metrics (for verification). You are right that stuck-at is a super-set of
that. I myself have never put 'toggle' patterns on a tester.
Toggle coverage is also used to measure the effectiveness of burn-in patterns.
In the old days, where CMOS technology is not as leaky, some folks used toggle patterns for IDDQ testing. However,
pseudo stuck-at faults were proven to be far superior than toggle patterns for IDDQ.

32. Why we lose coverage when we constrain pins?

In general, whenever you constrain any pins of your device, you take away the ability of the ATPG to toggle that pin
and check it (and its effects) in both states. Sometimes when you constrain a pin, it will have negligble effect.
Sometimes it will have far ranging effects on fault coverage.

33. What is the difference between redundant, undetectable and untestable faults? How will a ATPG tool
identify a fault to be redundant or untestable or undetectable? How to analyze redundant faults?

Write the fault list of each fault class separately and save it in a file. Now load back the same for which you want to
analyze like UD,UR,AU..etc. There is a command option in almost all the tools to analyze the fault which will show
the schematic of the fault site.You can use graphical interface options to proceed further. Syntax depends on which
tool you are using.
Ex- analyze fault /path of fault site/ -stuck 0|1
Now you can start analyzing how many ever faults you want. It’s better to have a hierarchical/modular coverage
numbers so that you will know which block is giving lesser coverage and analyze those fault sites accordingly.

34. What do you mean by typical scan frequencies?

Typical scan frequency is the frequency that most of the ATE's use when scanning in the data to the scan flops. it is
typically around 1-10 Mhz.

35. Why is Hold time neglected while calculating Max Frequency?

To calculate the maximum frequency of the digital circuit, you will use the following
formula.
tCLOCK=tCHQV+tPD(max)+tSETUP.
Here, in all FFs, normally tHOLD < tCHQV, means Clock to Q output delay includes the hold time. So we are not
considering the hold time for calculating the max. Frequency.

36. Why we avoid latches in the design, even if they provide only cell delay. Is there any time related
issues??
Whenever latch is enabled it will pass whatever is there on its D inputs to Q output. If suppose any glitch is coming
on D and latch is enabled it will pass it to q. Glitch always create problem u would be knowing this.
Latches are fast, consumes less power, less area than Flops but Glitches can also come along with these advantages,
that’s why we go for flops.
Also Latches are not DFT friendly... It is very difficult to perform Static timing analysis with latches in your design...

37. What is the difference between a latch and a flip-flop?

 Both latches and flip-flops are circuit elements whose output depends not only on the present inputs, but also on
previous inputs and outputs.
 They both are hence referred as "sequential" elements.
 In electronics, a latch, is a kind of bistable multi vibrator, an electronic circuit which has two stable states and
thereby can store one bit of of information. Today the word is mainly used for simple transparent storage elements,
while slightly more advanced non-transparent (or clocked) devices are described as flip-flops. Informally, as this
distinction is quite new, the two words are sometimes used interchangeably.
 In digital circuits, a flip-flop is a kind of bistable multi vibrator, an electronic circuit which has two stable states
and thereby is capable of serving as one bit of memory. Today, the term flip-flop has come to generally denote non-
transparent (clocked or edge-triggered) devices, while the simpler transparent ones are often referred to as latches.
 A flip-flop is controlled by (usually) one or two control signals and/or a gate or clock signal.
 Latches are level sensitive i.e. the output captures the input when the clock signal is high, so as long as the clock
is logic 1, the output can change if the input also changes.
 Flip-Flops are edge sensitive i.e. flip flop will store the input only when there is a rising or falling edge of the
clock.
 A positive level latch is transparent to the positive level(enable), and it latches the final input before it is
changing its level(i.e. before enable goes to '0' or before the clock goes to -ve level.)
 A positive edge flop will have its output effective when the clock input changes from '0' to '1' state ('1' to '0' for
negative edge flop) only.
 Latches are faster, flip flops are slower.
 Latch is sensitive to glitches on enable pin, whereas flip-flop is immune to glitches.
 Latches take fewer gates (less power) to implement than flip-flops.
 D-FF is built from two latches. They are in master slave configuration.
 Latch may be clocked or clock less. But flip flop is always clocked.
 For a transparent latch generally D to Q propagation delay is considered while for a flop clock to Q and setup
and hold time are very important.

38. What do you mean by scan chain reordering?

Answer1: Based on timing and congestion the tool optimally places standard cells. While doing so, if scan chains are
detached, it can break the chain ordering (which is done by a scan insertion tool like DFT compiler from Synopsys)
and can reorder to optimize it.... it maintains the number of flops in a chain.
Answer2: During placement, the optimization may make the scan chain difficult to route due to congestion. Hence
the tool will re-order the chain to reduce congestion.
This sometimes increases hold time problems in the chain. To overcome these buffers may have to be inserted into
the scan path. It may not be able to maintain the scan chain length exactly. It cannot swap cell from different clock
domains.
Because of scan chain reordering patterns generated earlier is of no use. But this is not a problem as ATPG can be
redone by reading the new netlist.
39. What is software reset and hardware reset?

Software reset is a reset managed by software by writing a special register bit dedicated for this purpose; it's usually
a synchronous reset.
Hardware reset is the traditional reset activated by setting the IC reset pin to '1' or '0' (depending on the convention:
active low or active high reset), it can be also generated inside the IC.

40. In a Design which type of RESET (asyn or syn) will you prefer??

Best Solution is "Assert RESET asynchronously and De-assert Synchronously"

Active Low or Active HIGH?
If active high reset is used, any noise on the reset line can cause a spike and these results in a reset. But if active Low
reset is used, this can never happen. So active low is preferred. This is the case where the reset comes from external
to chip, but if reset is internally generated; then this may not be big issue.
Power point of view:
In cases where leakage is significant, active Low reset causes more leakage; as in in-active state the reset is active
high and the transistor can leak slowly from high causing more leakage. So active high is preferred for low power.

41. Whether Positive skew is good for Setup? How?

positive skew is similar to useful skew , it is nothing but delaying capture clock by skew value correct than the
normal launch clock value whenever you delay the capture clock surely you gain that my margin which can reduce in
your setup violation. If you want to visualize properly, you can think like if you have more period then surely setup
violation will reduce correct. it is similar concept.
Negative skew is bad for setup?
Similar to my earlier answer here you are reducing the capture clock.
Positive skew is bad for hold? Negative skew is good for hold?
For example: FF1 --> FF2 --> FF3
case 1: All FF[flip flop ] has zero skew.
Analysis: You have a setup violation path from FF1 to FF2.
Work around: Trying to optimize the datapath from FF1 to FF2 , you cannot do it , as the path is already optimized.
Now what is the only option left is playing safely rather marginally with clock.
So you are planning for skewing the capture flip flop clock that is FF2, delaying , so assume you met with the setup
violation across FF1 to FF2.
Another scenario comes, you had delayed your FF2 more, so you have a hold violation to FF3.
hope the concept is clear.

42. What are the measures or precautions to be taken in the Design when the chip has both analog and
digital portions?
Designing for Optimal integration of Analog and Digital
 As today's IC has analog components also inbuilt, some design practices are required for optimal integration.
 Ensure in the floor planning stage that the analog block and the digital block are not sitting close-by, to reduce
the noise.
 Ensure that there exists separate ground for digital and analog ground to reduce the noise.
 Place appropriate guard-rings around the analog-macro.
 Incorporating in-built DAC-ADC converters, allows us to test the analog portion using digital testers in an
analog loop-back fashion.
 Perform techniques like clock-dithering for the digital portion.
43. What is local-skew, global-skew, and useful-skew mean?
Local skew: The difference between the clock reaching at the launching flop vs the clock reaching the destination
flip-flop of a timing-path.
Global skew: The difference between the earliest reaching flip-flop and latest reaching flip-flop for a same clock-
domain.
Useful skew: Useful skew is a concept of delaying the capturing flip-flop clock path, this approach helps in meeting
setup requirement with in the launch and capture timing path. But the hold-requirement has to be met for the design.

44. How many minimum modes should qualify STA for a chip?
1. Scan Shift mode
2. Scan Capture mode
3. MBIST mode
4. Functional modes for Each Interface
5. Boundary scan mode
6. scan-compression mode
How many minimum process lots, should STA be qualified?
1. Fast corner
2. Slow corner
3. Typical corner
How many minimum Timing, Should STA be qualified?
1. Normal delay mode (without applying duration)
2. On-chip variation mode (duration applied)
3. SI mode (Signal integrity cross talk impact on STA)
What are the various Timing Paths in a Chip?
1. Path starting from Input Data pad and Ending at Register pin.
2. Path starting from clock-pin of a Register and Ending at Data pin of a Register (Reg-to-Reg path).
3. Path starting from output of a Register and Ends at output pad of a chip.
4. Path starting from input data pad and ends at output data pad (pure combo path).

45. What is meant by virtual clock definition and why do i need it?

Ans: Virtual clock is mainly used to model the I/O timing specification. Based on what clock the output/input pads
are passing the data.

46. How to solve setup & Hold violations in the design?

Ans: To solve setup violation
1. optimizing/restructuring combination logic between the flops.
2. Tweak flops to offer lesser setup delay [DFFX1 -> DFFXx]
3. Tweak launch-flop to have better slew at the clock pin, this will make CK->Q of launch flop to be fast there by
helping fixing setup violations
4. Play with skew [ tweak clock network delay, slow-down clock to capturing flop and fasten the clock to launch-
flop](otherwise called as Useful-skews)

To solve Hold Violations

1. Adding delay/buffer[as buffer offers lesser delay, we go for special Delay cells whose functionality Y=A, but with
more delay]
2. Making the launch flop clock reaching delayed
3. Also, one can add lockup-latches [in cases where the hold time requirement is very huge, basically to avoid data
slip]
47. What is the implication of a combinatorial feedback loops in design testability?

The presence of feedback loops should be avoided at any stage of the design, by periodically checking for it, using
the lint or synthesis tools. The presence of the feedback loop causes races and hazards in the design, and 104 RTL
Design
leads to unpredictable logic behavior. Since the loops are delay-dependent, they cannot be tested with any ATPG
algorithm. Hence, combinatorial loops should be avoided in the logic.

48. Given two ASICs. one has setup violation and the other has hold violation. how can they be made to
work together without modifying the design?
Ans: Slow the clock down on the one with setup violations..
And add redundant logic in the path where you have hold violations.

49. What is "Scan" or why do we need Scan?

Ans : Scan Insertion and ATPG helps test ASICs (e.g. chips) during manufacture. If you know what JTAG boundary
scan is, then Scan is the same idea except that it is done inside the chip instead of on the entire board. Scan tests for
defects in the chip's circuitry after it is manufactured (e.g. Scan does not help you test whether your
Design functions as intended). An ASIC designer usually implements the scan themselves and occurs just after
synthesis. ATPG (Automated Test Pattern Generation) refers to the creation of "Test Vectors" that the Scan circuitry
enables to be introduced into the chip.
 The ATE (Automated Test Equipment) at the chip factory can put the chip into the scan test mode, and apply
the test vectors. If any vectors do not match, then the chip is defective and it is thrown away.
 Scan/ATPG tools will strive to maximize the "coverage" of the ATPG vectors. In other words, given some
measure of the total number of nodes in the chip that could be faulty (shorted, grounded, "stuck at 1", "stuck at 0"),
what percentage of them can be detected with the ATPG vectors? Scan is a good technology and can achive high
coverage in the 90% range.
50. What is an LFSR .List a few of its industry applications.?
Ans: LFSR is a linear feedback shift register where the input bit is driven by a linear function of the overall shift
register value. Coming to industrial applications, as far as I know, it is used for encryption and decryption and in
BIST(built-in-self-test) based applications..

51. what is false path? how it determine in ckt? What the effect of false path in ckt?
Ans: By timing all the paths in the circuit the timing analyzer can determine all the critical paths in the circuit.
However, the circuit may have false paths, which are the paths in the circuit which are never exercised during normal
circuit operation for any set of inputs.
An example of a false path is shown in figure below. The path going from the input A of the first MUX through the
combinational logic out through the B input of the second MUS is a false path. This path can never be activated since
if the A input of the first MUX is activated, then Sel line will also select the A input of the second MUX.
STA (Static Timing Analysis) tools are able to identify simple false paths; however they are not able to identify all
the false paths and sometimes report false paths as critical paths. Removal of false paths makes circuit testable and its
timing performance predictable (sometimes faster)

52. Consider two similar processors, one with a clock skew of 100ps and other with a clock skew of 50ps.
Which one is likely to have more power? Why?
Ans: Clock skew of 50ps is more likely to have clock power. This is because it is likely that low-skew processor has
better designed clock tree with more powerful and number of buffers and overheads to make skew better.

53. What are multi-cycle paths?

Ans: Multi-cycle paths are paths between registers that take more than one clock cycle to become stable.

54. You have two counters counting upto 16, built from negedge DFF , First circuit is synchronous and
second is "ripple" (cascading), Which circuit has a less propagation delay? Why?
Ans: The synchronous counter will have lesser delay as the input to each flop is readily available before the clock
edge. Whereas the cascade counter will take long time as the output of one flop is used as clock to the other. So the
delay will be propagating. For Eg: 16 state counter = 4 bit counter = 4 Flip flops Let 10ns be the delay of each flop
The worst case delay of ripple counter = 10 * 4 = 40ns The delay of synchronous counter = 10ns only.(Delay of 1
flop)

55. Explain about setup time and hold time, what will happen if there is setup time and hold tine violation,
how to overcome this?
Ans: Set up time is the amount of time before the clock edge that the input signal needs to be stable to guarantee it is
accepted properly on the clock edge.
Hold time is the amount of time after the clock edge that same input signal has to be held before changing it to make
sure it is sensed properly at the clock edge.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable:
this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to
either '1' or '0'. This whole process is known as metastability

56. What is skew, what are problems associated with it and how to minimize it?
Ans: In circuit design, clock skew is a phenomenon in synchronous circuits in which the clock signal (sent from the
clock circuit) arrives at different components at different times.
This is typically due to two causes. The first is a material flaw, which causes a signal to travel faster or slower than
expected. The second is distance: if the signal has to travel the entire length of a circuit, it will likely (depending on
the circuit's size) arrive at different parts of the circuit at different times. Clock skew can cause harm in two ways.
Suppose that a logic path travels through combinational logic from a source flip-flop to a destination flip-flop. If the
destination flip-flop receives the clock tick later than the source flip-flop, and if the logic path delay is short enough,
then the data signal might arrive at the destination flip-flop before the clock tick, destroying there the previous data
that should have been clocked through. This is called a hold violation because the previous data is not held long
enough at the destination flip-flop to be properly clocked through. If the destination flip-flop receives the clock tick
earlier than the source flip-flop, then the data signal has that much less time to reach the destination flip-flop before
the next clock tick. If it fails to do so, a setup violation occurs, so-called because the new data was not set up and
stable before the next clock tick arrived. A hold violation is more serious than a setup violation because it cannot be
fixed by increasing the clock period.
Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced to decrease the clock period at
which the circuit will operate correctly, and/or to increase the setup or hold safety margins. The optimal set of clock
delays is determined by a linear program, in which a setup and a hold constraint appears for each logic path. In this
linear program, zero clock skew is merely a feasible point.
Clock skew can be minimized by proper routing of clock signal (clock distribution tree) or putting variable delay
buffer so that all clock inputs arrive at the same time
57. What is slack?
Ans: 'Slack' is the amount of time you have that is measured from when an event 'actually happens' and when it 'must
happen’.. The term 'actually happens' can also be taken as being a predicted time for when the event will 'actually
happen'.
When something 'must happen' can also be called a 'deadline' so another definition of slack would be the time from
when something 'actually happens' (call this Tact) until the deadline (call this Tdead).
Slack = Tdead - Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadline' time...in other words it's too late and a
timing violation....you have a timing problem that needs some attention.

58. A very good interview question... What is difference between setup and hold time. The interviewer was
looking for one specific reason, and it’s really a good answer too. The hint is hold time doesn't depend on
clock, why is it so...?
Ans: Setup violations are related to two edges of clock, i mean you can vary the clock frequency to correct setup
violation. But for hold time, you are only concerned with one edge and does not basically depend on clock frequency

59. How to fix the hold/setup violation in scan path (Q to SI path)?

Ans : If the violations are small, as in most designs with well-balanced clock trees, the place and route tools can
generally fix these by adding small buffers/inverters. Some smart scan reordering tools will take a slightly farther
scan flip-flop to avoid hold problems.
If the violations are big, due to large clock skews, the best way to solve this is to add a data lockup latch.
I have always wondered why scan chain reordering tools don't take clock skew information into consideration. Not
sure if the latest tools uses this vital information.
I think the tools look first to reduce congestion, by reducing the number of clock buffers in the scan path, which will
minimize hold time violations, but there are always some left, so your process has to include a step where the post-
route netlist is re-analyzed for timing (both mission and scan mode), and any hold violations left in the scan path are
manually fixed.

60. I have 3 types of flops in my design.

1. CLK domain posedge
2. CLK domain negedge
3. RCO_CLK domain posedge only.
Is it feasible/possible to put them in 1 scan-chain ?

Ans: Yes, it is possible.

Assuming that CLK is a Return-to-Zero clock (0->1->0 pulse), you would stitch the negedge CLK domain flip-flops
before posedge CLK domain flip-flops, i.e., negedge CLK FFs are closer to scan input, and posedge CLK FFs are
closer to scan output.
RCO_CLK domain can be stitched at either end of the chain. However, if CLK has a significantly larger clock tree
than RCO_CLK clock tree, then it is better to put RCO_CLK domain FFs at the end of the chain. Otherwise, you may
need to skew your clock timing on the ATE.
This means your chain will look like this:
ScanIn -> negedge CLK -> posedge CLK -> RCO_CLK -> ScanOut

61. What is a BUS Primitive and clock_PO pattern?

Ans : A bus primitive is just a DFT model of a bus - a net that has more than one driver. It's important that you
constrain it during test.
A clock PO pattern is a pattern that measures a primary output that has connectivity to a clock. So if a clock signal
propagates through combinational logic to a primary output (PO), an ATPG vector can be created to measure the
results of that propagation

62. How to toggle reset to get coverage?

Ans : If the reset is asynchronous (and properly bypassed during scan), you can declare the reset pin as a clock during
ATPG, and ATPG will toggle it accordingly to get faults on reset pin.
If the reset is synchronous, you can treat the reset pin as a normal data pin, and ATPG should be able to cover faults
on the reset.
Be careful, however, if you run transition fault ATPG. Reset usually cannot toggle at-speed, so you may not want to
declare the reset as a clock when running transition fault ATPG.
You can also try to run the patterns that toggle the reset as a clock pin at a reduced speed on the tester, if you worry
about transition fault coverage on reset.

63. What is the use of compressor? Why can’t we use compressor for RAM?
Ans : You're getting your test methodology mixed, I think, but you can test a ROM with a compressor - also known
as a MISR. That's done all the time. The idea is that the contents of the ROM are simply read out, and fed into the
MISR (multiple input shift register), and the resulting signature is read out and compared with the expected
signature.
It's not so common to do that with RAMs, since both the write and read data are generated algorithmically.
However if your question is more general, the use of a compressor is usually to turn a large set of data into a smaller
one, which is very handy for when access to the circuit, or bandwidth, is limited.

64. What problems could be expected on silicon in scan mode? I am talking about the problems that could
hinder running chip in scan mode? like I have heard that sometimes testing in scan mode doesn't work at the
intended frequency it is designed for?
Ans : You can avoid having problems in the silicon by simulating your scan vectors with back-annotated timing
information (SDF). However, even then you may have some problems, because normally, simulation is not run with
all the same timing corners that are used to close timing.
When someone says that they are not able to run scan at-speed, it usually means that the ATPG was run without
considering all the false- and multi-cycle-paths that are present in the design. These paths don't generally run at-
speed. This happens a lot in multi-clock domain circuits.
Also very common is that the scan chains don't shift properly - they may have hold-time violations. This is hard to
overcome, but a partial set of patterns may be possible if you can figure out where the problem is. Again, if you
simulate the scan shift pre-silicon, you may avoid this.

65. How to achieve high fault coverage. How to increase it.

Ans: 1. 100% scan design
2. More number of test points
3. No X’s in the design
4. Use sequential patterns
5. Completely defined netlist, i.e there should be no floating outputs, or un connected inputs.
6. There should be logic to certain that there would be no contentions on the bus
7. Avoid floating bus using bus keepers.

66. Latch - how is it used in dft for sync two clock domains?
Ans: Latches are used as lockup latches in the scan chains. These are inserted in the chains where ever there is a
change in the clock domain. By clock domain we mean, two clocks or the same clock with phase difference.
Let us have a condition here to explain the things; we have a design with 2 clocks CLK1 and CLK2. There is a single
chain in the design, which means that the scan chain have flops which can be clocked by either of the clock.
The tool by default will order the flops in the scan chain such that first we have one clock domain's flop followed by
the other domain flops. Let us consider that the CLK2 flops follows CLK1 flops.
Now consider the flop which is at the boundary that is the one where the output of the CLK1's flop is going to the
CLK2's scan_in. Clock skew between these successive scan-storage cells must be less than the propagation delay
between the scan output of the first storage cell and the scan input of the next storage cell. Otherwise, data slippage
may occur. Thus, data that latches into the last flop of CLK1 also latches into the first flop of CLK2. This situation
results in an error because the CLK2's flop should latch the CLK1's "old" data rather than its "new" data.
To overcome this issue we add the lock up latch where ever there are clock domain crossing. In our example we
would add a lock-up latch which has an active high enable and is being controlled by inverted of CLK1. Thus
becomes transparent only when CLKA goes low and effectively adds a half clock of hold time to the output of the
last flip-flop of clock domain CLK1.
Now, imagine that we have two functionally asynchronous domains 1 and 2. Functionally asynchronous means that
during the normal mode of operation (Functional Mode), the two domains do not interact with each other. However,
very rarely do the designers have the liberty to make a separate scan chain for functionally asynchronous domains.
Let's consider the following scenario: where domain 1 has the average clock latency of 3ns, and domain 2 has the
average latency of 6ns. And the time period of the test clock is, let's say, 10ns.

Now, let's see the timing checks for this scenario. The output of the last flop of the domain 1 is in scan-chain and
connected to the Test-Enable input of the first flop of domain 2. The check would be like:

Owing to the positive clock skew, the setup check would be relaxed, but hold would be critical. Two possible options
to fix the hold timing:
 Insert the buffers, to add sufficient delay, so that hold is finally met.
 To add the Lock-Up Latch between the two flops where scan chain crosses the functional domains.
The first might not be a robust solution because the delay of the buffers would vary across the PVT Corners and RC
Corners. In the worst case, there might be a significant variation in the delays across corners and you might witness
closure of timing in one corner, but violation in other corner!

Second solution is a more robust solution because it obviates the above scenario. Hence see how it does it.
Timing Check would be like:

Hence, both setup and hold checks are relaxed!!

67. Explain Fault types ?

Ans: The different fault types are
1. Stuck at fault model : The node is modeled to be stuck at some value 0 or 1 depending on what we are targeting.
2. Iddq fault model : This is similar to the stuck at fault model but here instead of measuring the voltage we measure
the current . In a CMOS design at the quiescent state, ideally there is suppose to no current in the silicon, if there is
current then some node has either shorted to ground or to the power.
3. Transition fault model : This is considered to stuck at fault model within a time window. The value of the node
changes but not within the time ,at which it should change .For detecting such faults we have two vector for each
pattern one for launching the fault and the other to capture the fault. The time between the launch and the capture is
supposed to be equal to the time at which the chip would normally function. This is the reason it is all called at-speed
test.
4. Path delay fault model : In this fault model ,instead of concentrating on a single gate of the netlist ,we generally
are concern with a collection of gates which forms a valid path in the design. These are generally the critical paths of
the design. Here again we have two vectors for each pattern. Do let me know if you know what is a valid path ( don't
feel offended I am just writing this because you are out of touch with all these technical jargons since long , otherwise
I hope you must be knowing them).
The transition faults are also measured at the paths ends, but the major difference between the transition and the path
delay is that in the path delay we give the path where as in the case of transition the tool itself selects the path for give
fault.
The fault location for IDDQ, stuck-at and transition are same.
5. Bridging fault model : this is a new model which is gaining importance . In this case any two close lying net may
effect the value of each other. There is generally a victim and another is a aggressor, so an aggressor forces some
value on the victim . We first find the coupling capacitance of each net pair, then depending on the specs we may
select some nets which have coupling capacitance more then specified value, these are selected and then these
become the fault locations for the ATPG.

68. How do u break combinational loops. (*)How does introducing TIEX will eliminate combinational loop.
[ I told him by forcing known value we can break the loop]
Ans: By adding a tiex gate we can break the combinational loop. First what is a combinational loop. The value is not
stabilized, there are oscillation. So if we place a X gate at some place in the loop, we are not propagating the
deterministic value which was causing the oscillations.

Adverse Effect : Any X in the design would reduce the coverage.

The second solution would be to place a buffer with unit delay. In this case you would require sequential patterns.
Please note that we are not placing any Tiex or buffer with unit delay in the netlist, it is just that we are
telling ur ATPG tool to model them for the ATPG purpose. So you won't see any tiex or buf with unit delay gates in
the netlist.

69. What does test procedure files have?

Ans: The test procedure file contains all the scan information of your test ready netlist.
1. The number of the scan chains
2. The number of scan cells in each scan chain.
3. The shift clocks.
4. The capture clocks
5. Any test setup procedure required before starting the test pattern generation
6. The timing of the different clocks.
7. The time for forcing the Primary input , bidi inputs , scan inputs etc
8. The time to measure the primary outputs, scan outputs , etc ..
9. The pins which have to be held at some state in the different procedure as load_unload, shift etc ..
70. What are the violations which prevent scan insertion?

Ans: Scan design rules require that registers have the functionality, in test mode, to be a cell within a large shift
register. This enables data to get into and out of the chip. The following violations prevent a register from being
scannable:

• The flip-flop clock signal is uncontrollable.

• The latch is enabled at the beginning of the clock cycle.
• The asynchronous controls of registers are uncontrollable or are held active.
Uncontrollable Clocks

This violation can be caused by undefined or unconditioned clocks. DFT Compiler considers a clock to be controlled
only if both of these conditions are true:

• It is forced to a known state at time = 0 in the clock period (which is the same as the “clock off state” in
TetraMAX).

•It changes state as a result of the test clock toggling.

Latches Enabled at Beginning of Clock Cycle

This violation applies only when the scan style is set to level-sensitive scan design (LSSD). For a latch to be
scannable, the latch must be forced to hold its value at the beginning of the cycle, when the clock is inactive. This
violation can be caused by undefined or unconditioned clocks.

This violation indicates that there are registers that cannot be controlled by ATPG. If the violation is not corrected,
these registers will be unscannable and fault coverage will be reduced.

Asynchronous Control Pins in Active State

Asynchronous pins of a register must be capable of being disabled by an input of the design.If they cannot be
disabled, this is reported as a violation. This violation can be caused by asynchronous control signals (such as the
preset or clear pin of the flip-flop or latch) that are not properly conditioned before you run DFT Compiler.

71. What are the violations which prevent data capture?

Ans: The violations are described in the following sections:
• Clock Used As Data
• Black Box Feeds Into Clock or Asynchronous Control
• Source Register Launch Before Destination Register Capture
• Registered Clock-Gating Circuitry
• Three-State Contention
• Clock Feeding Multiple Register Inputs
72. What are the violations which reduces fault coverage?

Ans: Violations that can reduce fault coverage are

• Combinational Feedback Loops

• Clocks That Interact With Register Input
• Multiple Clocks That Feed Into Latches and Flip-Flops
• Black Boxes
Combinational Feedback Loops

An active (or sensitizable) feedback loop reduces the fault coverage that ATPG can achieve by increasing the
difficulty of controlling values on paths containing parts of the loop.

Clocks That Interact With Register Input

A clock that affects the data input of a register reduces the fault coverage attainable by ATPG, because ATPG pulses
only one clock at a time, keeping all other clocks in their off states. Attempting to fix this purely in the ATPG setup
can result in timing hazards.

Black Boxes

Logic that drives or is driven by black boxes cannot be tested because it is unobservable or uncontrollable. This
violation can drastically reduce fault coverage, because the logic that surrounds the black box is unobservable or
uncontrollable
73. What could be the possible reasons for scan chain failures during GLS (Gate level Simulation)? Other than
setup issues.

74. What are copy and shadow cell? How are they useful?

Shadow Element: The shadow element, either dependently- or independently-clocked, resides outside the scan
chain path. It can be inside or outside of a scan cell. Figure gives an example of a scan cell with a dependently-
clocked, non-observable shadow element with a non-inverted value.

You load a data value into the dependently-clocked shadow element with the shift procedure. If the shadow element
is independently clocked, you use a separate procedure called shadow_control to load it. You can optionally make a
shadow observable using the shadow_observe procedure. A scan cell may contain multiple shadows but only one
may be observable, because the tools allow only one shadow_observe procedure. A shadow element’s value may be
the inverse of the master’s value. The definition of a shadow element is based on the shadow having the same (or
inverse) value as the master element it shadows. A variety of interconnections of the master and shadow will
accomplish this. In Figure the shadow’s data input is connected to the master’s data input, and both FFs are triggered
by the same clock edge. The definition would also be met if the shadow’s data input was connected to the master’s
output and the shadow was triggered on the trailing edge, the master on the leading edge, of the same clock.

Copy Element
The copy element is a memory element that lies in the scan chain path and can contain the same (or inverted) data as
the associated master or slave element in the scan cell. Figure 3-7 gives an example of a copy element within a scan
cell in which a master element provides data to the copy.

The clock pulse that captures data into the copy’s associated scan cell element also captures data into the copy. Data
transfers from the associated scan cell element to the copy element in the second half of the same clock cycle. During
the shift procedure, a copy contains the same data as that in its associated memory element. However, during system
data capture, some types of scan cells allow copy elements to capture different data. When the copy’s value differs
from its associated element, the copy becomes the observation point of the scan cell. When the copy holds the same
data as its associated element, the associated element becomes the observation point.

75. What are the typical clock skew issues you faced during post layout/ timing simulation?

76. How do you test at-speed faults for inter clock domains?

Understanding inter-clock domain analysis

When functional paths exist across two clock domains (the register launching the data and the one capturing it are
clocked by two different clock sources), you must provide accurate specification of both clocks to allow a valid inter-
clock domain timing check. This is important especially when the clocks are specified with different waveforms and
frequencies.
When you specify multiple clocks in your design, the first step is to consider whether the inter-clock domain paths are
false or functional. If these paths are functional, then you must perform setup and hold checks between the clock
domains in SmartTime. Unless specified otherwise, SmartTime considers the inter-clock domain as false, and
therefore does not perform setup or hold checks between the clock domains.
Once you include the inter-clock domains for timing analysis, SmartTime analyzes for each inter-clock domain the
relationship between all the active clock edges over a common period equal to the least common multiple of the two
clock periods. The new common period represents a full repeating cycle (or pattern) of the two clock waveforms.
For setup check, SmartTime considers the tightest relation launch-capture to ensure that the data arrives before the
capture edge. The hold check verifies that a setup relationship is not overwritten by a following data launch.
 No at-speed testing is done with inter-clock domain. Inter-clock domain will be false path as there will be no logic.

77. Are multi-cycle paths tested in the design?

Yes…. How?

78. Why do you need multiple-load patterns? What are its advantages over basic scan patterns?
Same as 81

79. What are the typical steps to improve coverage when our coverage target is not achieved?

80. Steps to fix broken scan chain issues during ATPG? Step by step procedure to find the issue?
81. What is sequential depth?
82. How to specify clocks for at-speed testing in encounter test or any other tool? What is the syntax?

. What is split capture? Difference between split capture cycle and capture handling? What is the tradeoffs of split
capture cycle and capture handling? What is the benefit of using split capture_cycle vs capture handling?
A C3, C4 error is violated when a memory element captures data at the clocks trailing edge and the data comes from
a leading edge device.By default FastScan capture only on the leading edge of the capture
clock and does only one evaluation of the captured data. Thus in DRC is pointing to the condition where the trailing
edge device needs to be evaluated again to have the correct captured data from the leading edge data. The command:
set split capture_cycle ON
will tell the ATPG process to perform a second simulation evaluation to update the trailing edge memories.
By default the split capture cycle handling is turned off. Use of this command will allow FastScan to calculate the
correct expected values for the reported cells (trailing edge). This feature will assure that the correct simulation values
are generated. In the case where C3 and C4 DRC violations are encountered simply
turn on the split capture cycle handling and these DRC violations can then be ignored. You can think of the C3 and
C4 DRC violations as a prompt to turn this feature on. The DRC failure reports will still occur. However, with this
feature turned on they will have no negative impact on the simulation results. There will however be a small impact
on ATPG run times. It is this impact that results in the default for this command being set to off. Failing to set this
command or ignoring the C3 and C4 error often results in simulation mismatches during pattern verification.

The tradeoff is between test coverage and performance.

The use of capture handling will not impact performance. However it can have a impact on test coverage. Capture
handling only allows one expected value in the presence of a C3 or C4 DRC violation. In the case
where there is a capture handling source that drives sink cells will both new and old behavior. Then one of the sinks
will capture X. This allows the correct expected value for one sink while assuring that a simulation mismatch doesn't
occur for the second. In the case where a capture handling sink captures X the cell cannot be observed. This will
impact test coverage. Depending on the number and mix of old and new behavior this can have a major impact on test
coverage. But again there is no impact on run times.

The use of split capture_cycle will impact performance. In this case there will be two evaluations of the logic in place
of one. Depending on the design this can have a large impact on run times. The use of split capture_cycle will
however provide the highest level of test coverage.
In the case where only a few C3 or C4 DRC violations occur. The use of capture handling is recommended. There
will be no impact on performance and due to the small number of violations there will be little impact
to test coverage.
In the case where there are large numbers of C3 and C4 violations. Then the use of split capture_cycle will provide
the best level of test coverage. Again the impact will be on run times.

84. How do you do top-level atpg? Explain

Explain about hierarchical scan (doc in the folder)

85. What is clock feeds data race violation in ATPG?

86. what have you done to improve coverage in your designs?
87. What is broadcast scan architecture? Explain the compression technique used in your designs?

Broadcast Scan Architecture:

Tessent TestKompress achieves compression of scan test data by controlling a large number of internal scan chains
using a small number of scan channels. Scan channels can be thought of as virtual scan chains because, from the point
of view of the tester, they operate exactly the same as traditional scan chains. Therefore, any tester that can apply
traditional scan patterns can apply compressed patterns as described in the following topics:
• Scan Channels
• Structure and Function
• Test Patterns
Scan Channels
With Tessent TestKompress, the number of internal scan chains is significantly larger than the number of external
virtual scan chains the EDT logic presents to the tester. Figure 1-1 illustrates conceptually how a design tested with
EDT technology is seen from the tester compared to the same design tested using conventional scan and ATPG.
Under EDT methodology, the virtual scan chains are called scan channels to distinguish them from the scan chains
inside the core. Their number is significantly less than the number of internal scan chains. The amount of
compression is determined by two parameters:
• number of scan chains in the design core
• number of scan channels presented to the tester
For more information on establishing a compression target for your application, see “Effective Compression” on page
25 and “Compression Analysis” on page 51.

Structure and Function

EDT technology consists of logic embedded on-chip, new EDT-specific DRC, and a deterministic pattern generation
technique.The embedded logic includes a decompressor located between the external scan channel inputs and the
internal scan chain inputs and a compactor located between the internal scan chainoutputs and the external scan
channel outputs. See Figure 1-2.

You have the option of including bypass circuitry for which a third block (not shown) is added. No additional logic
(test points or X-bounding logic) is inserted into the core of the design. Therefore, EDT logic affects only scan
channel inputs and outputs, and thus has no effect on functional paths.
Figure 1-2 shows an example design with two scan channels and 20 short internal scan chains.
From the point of view of the ATE, the design appears to have two scan chains, each as long as the internal scan
chains. Each compressed test pattern has a small number of additional shift cycles, so the total number of shifts per
pattern would be slightly more than the number of scan cells in each chain.
Note
The term additional shift cycles refers to the sum of the initialization cycles, masking bits (when using Xpress),
low-power bits (when using a low-power decompressor), and user-defined pipeline bits.
You can use the following equation to predict the number of initialization cycles TestKompress adds to each pattern
load. (In this equation, ceil indicates the ceiling function that rounds a fraction to the next highest integer.) This
equation applies except when you have very few channels in which case there are four extra cycles per scan load.
(Note, this equation does not factor in additional shift cycles added to support masking and low-power.)
For example, if a design has 16 scan channels, 1250 scan cells per chain, and a 50-bit decompressor, we can calculate
the number of initialization cycles as 4 by using the above formula. Since each chain has 1,250 scan cells and each
compressed pattern requires four initialization cycles, the tester sees a design with 16 chains requiring 1,254 shifts per
pattern.
Test Patterns
Tessent TestKompress generates compressed test patterns specifically for on-chip processing by the EDT logic.
For a given testable fault, a compressed test pattern satisfies ATPG constraints and avoids bus contention, similar to
conventional ATPG.
A set of compressed test patterns is stored on the ATE and each test pattern applies data to the inputs of the
decompressor and holds the responses observed on the outputs of the compactor. The ATE applies the compressed
test patterns to the circuit through the decompressor, which lies between the scan channel pins and the internal scan
chains. From the perspective of the tester, there are relatively few scan chains present in the design. The compressed
test patterns, after passing through the decompressor, create the necessary values in the scan chains to guarantee fault
detection. The functional input and output pins are directly controlled (forced) and observed (measured) by the tester,
same as in conventional test. On the output side of the internal scan chains, hardware compactors reduce the number
of internal scan chains to feed the smaller number of external channels. The response captured in the scan cells is
compressed by the compactor and the compressed response is compared on the tester. The compactor ensures faults
are not masked and X-states do not corrupt the response. You define parameters, such as the number of scan channels
and the insertion of lockup cells, which are also part of the RTL code. Tessent TestKompress automatically
determines the internal structure of the EDT hardware based on the parameters you specify, the number of internal
scan chains, the length of the longest scan chain, and the clocking of the first and last scan cell in each chain. Test
patterns include parallel and serial test benches for Verilog as well as parallel and serial WGL, and most other
formats supported by Tessent FastScan.
Number of initialization cycles ceil
decompressor size
number of channels

88. What are the different atpg modes you do?

89. How do you handle false paths and multicycle paths in at speed atpg?
Refer Mentor Doc in the folder

90. Explain fault collapsing with respect to a 2-input and gate.

This reduction of the entire set of single faults by removing equivalent faults is referred to as fault collapsing. Fault
collapsing helps to reduce both test generation and fault simulation times. In the following subsections, we review
some well-known and commonly used fault models.
91. What is a redundant fault in fault classification? Give an example.
Refer scan and atpg process guide – Pg. 47 to Pg. 52 for complete fault list

92. How do you debug atpg simulation mismatch?

93. what is launch on extra shift? Explain?
94. what type of timing violations you see in atpg simulations?
95. Do you know about low power atpg? How will generate low power atpg patterns?
96. A chip has 100% atspeed coverage,but still the functional vector fails.Explain.

97. Compare TDF,path delay test and small signal defects test?

“Delay defect” refers to any type of physical defect, or an interaction of defects, that adds enough
signal-propagation delay in a device to produce an invalid response when the device operates at the
targeted frequency. In fact, it does cover some of them, but not enough to achieve the quality levels required at
STMicroelectronics, which is pursuing a strategic quality objective of zero DPPM. The traditional goal of ATPG
tools has been to minimize run time and pattern count, not cover SDDs. TD ATPG targets delay defects by generating
one pattern to launch a transition through a delay fault site—which may activate either a
slow-to-rise or a slow-to-fall defect—and by generating a second pattern to capture the response. During testing, if
the signal doesn’t propagate to an end point (a primary out-put or scan flop) in the at-speed cycle time, then incorrect
data is captured. In this scenario, the pattern sequence detects a delay defect through
the activated path. In summary, TD ATPG is effective for detecting delay defects of nominal and large
size, but because it doesn’t explicitly target delay faults along the minimum-slack paths, it’s not effective in
detecting delay defects of relatively small size. SDD ATPG, in its purest form, is similar to path-delay testing. It
targets each undetected fault along the path with minimum timing slack.

In Figure 1, path 1 has the minimum slack, so the pattern generator will target the fault through path 1. If
the fault is detected, it is categorized as DS (detected by simulation). The fault simulator also classifies bonus faults
as DS if they’re detected along their mini-mum-slack paths. If any fault—a targeted fault or a bonus fault—is
detected along a path shorter than its minimum-slack path, it is designated as TP (transition partially
detected). A TP fault will continue to be fault-simulated each time ATPG generates a new pattern in hopes that a
pattern will eventually be generated that detects, as a bonus fault, this same fault through its minimum-
slack path. The main draw-back with this method is that, in the process of targeting every undetected fault along its
minimum-slack path, SDD ATPG wastes time and patterns working on faults that don’t contribute to detecting
SDDs.

98. what is power aware atpg?

The electronics industry has adopted low-power features in major aspects of the design continuum. In response, EDA
venders and major semiconductor companies have defined the commonly-used power data standard formats to
describe the power requirements: UPF and CPF. Tessent FastScan and Tessent TestKompress support the following
versions of the UPF and CPF formats:
• IEEE 1801 standard / UPF 2.0
• Common Power Format (CPF) 1.0 and 1.1
You load this power data directly into Tessent FastScan and Tessent TestKompress to collect the power information.
Once loaded, the tools perform the necessary DRC’s to ensure that the DFT logic is inserted properly with respect to
the design’s power domains and, if the design passes the rule checks, perform ATPG with the given power mode
configuration. During the tradition fault model test stage, the circuit is configured into a static power mode by the test
procedure at beginning of capture cycle and stay at the same power mode for entire capture cycles. The ATPG engine
explicitly prevents the power control logic to change the active power mode.

99. What are set up and hold violations? Do DFT people need to worry about this?

Setup time: t setup = time before the clock edge that data must
be stable (i.e. not changing)
• Hold time: t hold = time after the clock edge that data must be
Stable

8 Ways To Fix Setup violation:

Setup violations are essentially where the data path is too slow compared to the clock speed at the capture flip-flop.
With that in mind there are several things a designer can do to fix the setup violations.

Method 1 : Reduce the amount of buffering in the path.

 It will reduce the cell delay but increase the wire delay. So if we can reduce more cell delay in comparison to
wire delay, the effective stage delay decreases.
Method 2 : Replace buffers with 2 Inverters place farther apart
 Adding 2 inverters in place of 1 buffer, reducing the overall stage delay.
o Adding inverter decreases the transition time 2 times then the existing buffer gate. Due to that, the RC
delay of the wire (interconnect delay) decreases.
o As such cell delay of 1 buffer gate ≈ cell delay of 2 Inverter gate

Method 3 : HVT swap. Means change HVT cells into SVT/RVT or into LVT.
 Low Vt decrease the transition time and so propagation delay decreases.
 Negative effect: Leakage current/power also increases.

Method 4 : Increase Driver Size or say increase Driver strength (also known as upsize the cell)

Method 5 : Insert Buffers

 Some time we insert the buffer to decrease over all delay in case of log wire.
 Inserting buffer decreases the transition time, which decreases the wire delay.
 If, the amount of wire delay decreases due to decreasing of transition time > Cell delay of buffer, over all
delay decreases.
 Negative Effect: Area will increase and increase in the power consumption.

Method 6 : Inserting repeaters:

 Concepts of Repeaters are same as I have discussed in “Inserting the Buffer” (above point). Just I am trying to
explain this in a different way but the over concept are same.

Method 7 : Adjust cell position in layout.

Method 8 : Clock skew:
 By delaying the clock to the end point can relax the timing of the path, but you have to make sure the
downstream paths are not critical paths.

2 Ways to Fix Hold Violations:

Hold violation is the opposite of setup violation. Hold violation happen when data is too fast compared to the clock
speed. For fixing the hold violation, delay should be increases in the data path.
Note: Hold violations is critical and on priority basis in comparison are not fixed before the chip is made, more there
is nothing that can be done post fabrication to fix hold problems unlike setup violation where the clock speed can be
reduced.
The designer needs to simply add more delay to the data path. This can be done by
Method 9 : By Adding delays.
 Adding buffer / Inverter pairs /delay cells to the data path helps to fix the hold violation.
 Note: The hold violation path may have its start point or end point in other setup violation paths. So we have
to take extra care before adding the buffer/delay.
o E.G. if the endpoint of hold violation path has setup violation with respect to some other path, insert
the buffer/delay nearer to start point of hold violation path. Else the setup violation increases in other path.
o if the start point of hold violation path has setup violation with respect to some other path, insert the
buffer/delay nearer to end point of hold violation path. Else the setup violation increases in other path.
Method 10 : Decreasing the size of certain cells in the data path.
 It is better to reduce the cells closer to the capture flip flop because there is less likely hood of affecting other
paths and causing new errors.

Note: Following points are recommended while fixing setup and hold violations.
 Make modification to the data path only.
o Adjusting register location or removing/adding buffers to the clock path will fix the violation that but
it may cause more violations for some other paths which may not present before.
 First try to fix setup violation as much as possible. Then later on start fixing hold violation.
 In general, hold time will be fixed during back-end work (during PNR) while building clock tree. If u r
a front-end designer, concentrate on fixing setup time violations rather than hold violations.
 Fix all the hold violation, if you have to choose between setup and hold.
o If a chip is done with some setup violations it can work by reducing the frequency.
o If a chip is done with hold violations, we have “JUST DUMP” the chip.

100. How do you get double pulse in TDF? Is there any circuit to get double pulse from PLL clock?

101. What test architectures you know?

MBIST

102. How does hold violations effect scan chain shifting?

103. Derive the set up and hold equations for a reg to reg path with combinational logic in between?

Setup time is defined as the minimum amount of time BEFORE the clock’s active edge by which the data must be
stable for it to be latched correctly. Any violation in this required time causes incorrect data to be captured and is
known as a setup violation.
Hold time is defined as the minimum amount of time AFTER the clock’s active edge during which the data must be
stable. Any violation in this required time causes incorrect data to be latched and is known as a hold violation.
For more information on the intra-flop aspects of setup and hold time, see reference [1].
Equations for Setup and Hold Time
Let’s first define clock-to-Q delay (Tclock-to-Q). In a positive edge triggered flip-flop, input signal is captured on the
positive edge of the clock and corresponding output is generated after a small delay called the Tclock-to-Q. The flip flop
can only do the job correctly if the data at its input does not change for some time before the clock edge (Tsetup) and
some time after the clock edge (Thold). Again, the clock signal which circulates via clock tree throughout the design
has its own variability termed as skew.
From Figure 1 below, we derive equations for setup time and hold time. Figure 1 shows two talking flops, the first
being the launching flop and the second is obviously the capturing flop. We shall derive equation for setup time for
the capturing flop and equation for hold time for the launching flop. However, the derived equations will be true for
either of the flops or for that matter any flops in the design.
In the diagram above, at time zero FF1 is to process D2 and FF2 is to process D1. Time taken for the data D2 to
propagate to FF2, counting from the clock edge at FF1, is invariably = Tc2q+Tcomband for FF2 to successfully latch it,
this D2 has to be maintained at D of FF2 for Tsetup time before the clock tree sends the next positive edge of the clock
to FF2. Hence to fulfill the setup time requirement, the equation should be like the following.
Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew ------- (1)
Let’s have a look at the timing diagram below to have a better understanding of the setup and hold time.

Now, to avoid the hold violation at the launching flop, the data should remain stable for some time (Thold) after the
clock edge. The equation to be satisfied to avoid hold violation looks somewhat like below:
Tc2q + Tcomb ≥ Thold + Tskew ------- (2)
As seen from the above two equations, it can be easily judged that positive skew is good for setup but bad for hold.

104. What are mealy and moore machines in FSM?

Mealy machine has outputs that depend on the state and input (thus, the FSM has the output written on edges)
Moore machine has outputs that depend on state only (thus, the FSM has the output written in the state itself.
Adv and Disadv
In Mealy as the output variable is a function both input and state, changes of state of the state variables will be
delayed with respect to changes of signal level in the input variables, there are possibilities of glitches
appearing in the output variables. Moore overcomes glitches as output dependent on only states and not the
input signal level.
All of the concepts can be applied to Moore-model state machines because any Moore state machine can be
implemented as a Mealy state machine, although the converse is not true.
 Moore machine: the outputs are properties of states themselves... which means that you get the output after the
machine reaches a particular state, or to get some output your machine has to be taken to a state which
provides you the output.The outputs are held until you go to some other state Mealy machine:
Mealy machines give you outputs instantly, that is immediately upon receiving input, but the output is not held after
that clock cycle.

105. What is the effect of clock gating on DFT?

Clock gating is a widely used design technique for reducing power by eliminating unnecessary storage element
switching activity. An example is shown in Figure 2.23a. The clock enable signal (EN) is generated at the rising edge
of CK and is loaded into the latch LAT at the failing edge of CK to become CEN. CEN is then used to enable or
disable clocking for the flip-flop DFF. Although clock gating is a good approach for reducing power consumption, it
prevents the clock ports of some flip-flops from being directly controlled by primary inputs. As a result,
modifications are necessary to allow the scan shift operation to be conducted on these storage elements.
The clock gating function should be disabled at least during the shift operation. Figure 2.23b shows how the clock
gating can be disabled. In this example, an OR gate is used to force CEN to 1 using either the test mode signal TM or
the scan enable signal SE. If TM is used, CEN will be held at 1 during the entire scan test operation (including the
capture operation). This will make it impossible to detect faults in the clock gating logic, causing fault coverage loss.
If SE is used, CEN will be held at 1 only during the shift operation but will be released during the capture operation;
hence, higher fault coverage can be achieved but at the expense of increased test generation complexity.

106. Explain couple of issues you faced in your DFT career and how you resolved them.

A. Post-Test ATE BIRA Pattern with default Algorithm simulations were failing (0 1 Mismatches).
We had to hack the input netlist for the hs_adcu HM. The hack was to tie the mux select line to 0. This mux has been
placed between the latch and the WRCK at the stp level, with WRCK and LSI_SCAN_CLOCK connected to D0 and
D1 respectively of the mux and LSI_SCAN_MODE as the select line. The clock for the stp was unavailable at stp
level due to the same reason and hence the sims were failing.
B. Clock Shape Distortion:
The timing simulations for ATE BIST patterns were failing (x mismatches)
The clk_out is output of pll and CP shown above is how this clocks looks when it reaches inside.It's a 2ns clock.
What comes out of pll has 1 ns on and off period. When it reaches flops it's has t on of 1.4 ns and off only for 0.6 ns

107. What are synchronous and asynchronous resets?

Refer to the reset doc in folder

108. How can you model an asynchronous reset flop from a synchronous flop?
Refer to the reset doc in folder

109. What are control points in DFT? How do you add controllability and observability logic?

Controllability: By controllability from DFT point of view, we intend if both ‘0’ and ‘1’ are able to propagate to
each and every node within the target patterns. A point is said to be controllable if both ‘0’ and ‘1’ can be propagated
through scan patterns.

What if a node is not controllable: To achieve DFT coverage for a node, it is needed to be controllable. If a node is
not controllable, it cannot be tested. For production mode devices, it is necessary to have certain minimum percentage
of nodes controllable to ensure reliable devices to the customers. So, less number of controllable nodes mean less
DFT coverage, and hence, less reliable devices.
 Figure 1 : Figure showing a node that is not controllable within targeted number of patterns

Inserting control points (enhancing controllability): A node can be made controllable by inserting control points. If
the test coverage target is not getting met through target number of patterns, control points are inserted to increase the
test coverage. A control point is an alternate path supplied to a node to let a particular value propagate to it. As shown
in figure1, NODEA is not controllable within targeted number of patterns. We need to insert a control point in order
to increase its controllability. As shown in figure2, an alternate path can be provided to NODEA controlled by enable
signal. Adding control point at NODEA not only improves the controllability of NODEA, but it also improves the
controllability of fanout cone of NODEA.

Figure 2: Inserting control point to enhance controllability

There can be three types of control points:

• ‘0’ control points – Suppose we were earlier able to propagate ‘1’ to NODEA. We only need to let ‘0’
propagate. In that case, we can add a ‘0’ control point
• ‘1’ control points - Suppose we were earlier able to propagate ‘0’ to NODEA. We only need to let ‘1’
propagate. In that case, we can add a ‘0’ control point
• Flop control points – In order to let propagate both ‘0’ and ‘1’ through control points, flops need to be
inserted.
In case of ‘0’ and ‘1’ control points, the control input of mux can be tied to ‘0’ or ‘1’. Hence, area overhead is only a
mux. On the other hand, flop control points come with an overhead of an extra flop.

Observability: By observability, we mean out ability to measure the state of a logic signal. When we say that a node
is observable, we mean that the value at the node can be shifted out through scan patterns and can be observed
through scan out ports.

What if a node is not observable: If a node is not observable, it means we cannot see the value at the node and it is not
possible to see the value at that node through targeted number of patterns. To have scan coverage for the node, it is
necessary to be observable. As in the case of less number of controllable nodes, if number of observable nodes is less,
it means less scan coverage. So, less number of observable nodes also means less reliable devices. There may be
many cases in which we cannot observe a node. The most common are the nodes connected to inputs of an analog
block not having a scan chain inside. Since, analog blocks do not have scan chains, the input nodes cannot be
observed in the normal scenario which renders the entire fanin logic unobserved.

Figure 3: Figure showing a non-observable node

How a node can be made observable: To improve the observability of nodes in the design, observe points are
inserted. An observe point is a flip-flop inserted in the design that observes the value at one or more point. It has no
functional purpose. It is inserted in the scan chain and shifts the observed data to scan out ports through scan shifting.
A flip flop inserted as observe point can be used to observe a large number of hard-to-detect faults which results in a
significant reduction in pattern count.

Figure 4 : Inserting observe point to enhance observability

110. Why Negative edge flops are used for TDO/WSO?

Depending on the state of the TAP controller, the contents of either the instruction register or a data register
are serially shifted out towards the TDO. The data out of the TDO is clocked at the falling edge (negative slope) of
the TCK pulses. When no data is shifted through the cells, the TDO driver is set to an inactive state, for example to
high impedance. To provide half cycle delay

111. Serial Fault Sims vs Parallel fault Simulation?