QUALCOMM Interview Questions

1. Basic view of compression?

Ans: compression is used to reduce test duration and test volume.
Compression contains three stages decompression, X tolerance and
compactor.

2. Difference between Stuck at and At Speed?

Ans: Stuck at:
A stuck-at fault model purely uses a SCAN shift clock for shifting in a
pattern and doing capture. It's designed to catch ports of logic gates to be
stuck at 0 or 1 due to manufacturing defects.
At Speed:
An at-speed fault model is supposed to detect slow to rise, or slow to
fall type transitions between sequential. You use a SCAN clock to shift in
data, but 2 pulses of a functional clock to launch and capture.

3. How many capture pulse are needed in at speed and Stuck at?
Ans: At speed:
 LOC: we need two capture pulses, one for launch and another
for capture data.
 LOS: we need one capture pulse, to capture data.
Stuck at:
We need one capture pulse, to capture data.

4. Difference between LOC and LOS, which method is better?

Ans: Differences between the LOC and LOS
a) For LOS the scan enable has to closed at functional frequency (which
may result in gate count increase with addition of large buffers), whereas in
LOC the timing on scan enable can relaxed between the last shift and
launch cycle.
b) LOS ATPG run time is less compared to the LOC for pattern
generation.
 c) Pattern count in LOS in less than the LOC.
d) Test/fault coverage for LOS is higher than the LOC.
Transition ATPG is meant for detecting slow-to-rise and slow-to-fall faults
on a particular node. In order to detect the transition fault, we have to
create the transition on the node. We can achieve this in two ways

I) Launch on last shift - In this method, during the last shift itself, we will
shift in the required value in to the flop which will create the required
transition on the intended node.

Advantages:
1) Tool has the controllability to put the required value in to the flop
to cause transition.
2) We will get good coverage as we are launching the value through
SD path.
Disadvantages:
1) Scan-enable need to change at-speed, we have to implement
pipeline logic in order to support this.

II) Launch on capture –

In this method, the flop which creates the launch on the intended node
will get the value through D path. Scan-enable will be low during this time.

Advantages:
1) No need to add pipeline logic for Scan-enable.
Disadvantages:
1) We may lose some coverage as the value is launched through D path.

It’s always better to go with LOS; the major advantage with LOS is
increased coverage and reduction in number of patterns. When the no of
patterns decreases, the test time reduces, which in turn reduces the cost
for test time to a great extend.
5. How OCC generates Capture cycles?
Ans: OCC (on-chip clock controller) use to generate capture cycles.
OCC input to generate capture cycles :
 scan enable : 0(capture mode) | 1(shift mode)
 scan input
 cap_cycle_config : number of clock pulse during capture
 Fast clock = on
 Slow clock = on
 Fast_cap_mode : 1(fast clock in at speed)|0(slow clock in stuckat)
6. What is Sequential Depth?
Ans: Sequential Depth nothing but number of capture pulse used in a scan
chain. Normally we need one capture pulse in capture mode in a struck at .
But due to number of non scan FFs we need more capture pulse in a
capture mode in scan chain.
Example:
Consider in between two scan FFs we have two non scan FFs, so we
need two capture pulses for two non scan FFs and one for capture scan FFs,
it mean in total we need three capture pulses in capture mode in struck at.

7. What are FAST SEQ and FULL SEQ?

Ans: FAST sequential ATPG:
 Limited to up to 10 capture cycles.
 Power aware ATPG support for shift and capture.
 Supported for all faults models except IDDQ and IDDQ bridging.
 Faster runtime than full sequential ATPG.
FULL sequential ATPG:
 No capture cycles limit.
 Power aware ATPG not supported except for low power fill
 Supported foe all faults models except IDDQ and IDDQ bridging.
 Slower runtime than fast sequential ATPG.
8. If there are two scan flops and the clock has some delay, what kind of
issue you are going to get and how will you resolve this issue?
Ans: If we have two scan FFs and we have skew between a clock , we are
going to get timing related issues like data jumping issue (hold violations).
To avoid hold violation in between two scan FFs we need to insert lock
up latch in between two scan FFs.

9. Why scan? What is controllability and Observability?

Ans: To get controllability and observability on each and every node in a
design we need scan.
Controllability: By controllability, we intend if both ‘0’ and ‘1’ are
able to propagate to each and every node within the target patterns.  A
point is said to be controllable if both ‘0’ and ‘1’ can be propagated through
scan pattern.

Observability: By observability, we mean out ability to measure the

state of a logic signal. When we say that a node is observable, we mean that
the value at the node can be shifted out through scan patterns and can be
observed through scan out ports. 

10.What is lockup Latch and where to use lockup latch?

Ans: lockup latch is basically a latch which is use to place between two scan
FFs to provide half cycle delay.
Lockup latch are used in clock mixing and in decompression and in
between two scan FFs in a scan chain to avoid data jumping.

11.What is Asynchronous Clock?

Ans: Asynchronous clock mean it’s have different frequency , different
phase and its coming from different source.
It means if we use asynchronous clock in a design for same scan chain
we need a lock up latch in between clock to avoid hold violations , due to
that we get data jumping issue.
12.Setup and Hold Violations with waveform and formulae and with
example.
Ans: Setup time:
It is defined as the minimum amount of time BEFORE the clock’s
active edge by which the data must be stable for it to be latched correctly.
Any violation in this required time causes incorrect data to be
captured and is known as a setup violation.

Hold time:
 It is defined as the minimum amount of time AFTER the clock’s
active edge during which the data must be stable.
Any violation in this required time causes incorrect data to be latched
and is known as a hold violation.

From Figure 1 below, we derive equations for setup time and hold
time. Figure 1 shows two talking flops, the first being the launching flop
and the second is obviously the capturing flop.
We shall derive equation for setup time for the capturing flop and
equation for hold time for the launching flop. However, the derived
equations will be true for either of the flops or for that matter any flops
in the design.

Figure 1 Two talking flops scenario

In the diagram above, at time zero FF1 is to process D2 and FF2 is
to process D1. Time taken for the data D2 to propagate to FF2, counting
from the clock edge at FF1, is invariably = Tc2q +Tcomb and for FF2 to
successfully latch it, this D2 has to be maintained at D of FF2 for
Tsetup time before the clock tree sends the next positive edge of the clock
to FF2. Hence to fulfill the setup time requirement, the equation should
be like the following.
Tc2q + Tcomb + Tsetup ≤ Tclk + Tskew         (1)

Let’s have a look at the timing diagram below to have a better

understanding of the setup and hold time.

Figure 2 Setup and hold timing diagram

Now, to avoid the hold violation at the launching flop, the data
should remain stable for some time (Thold) after the clock edge. The
equation to be satisfied to avoid hold violation looks somewhat like
below:
Tc2q + Tcomb ≥ Thold + Tskew             (2)
As seen from the above two equations, it can be easily judged that
positive skew is good for setup but bad for hold. The only region where
the input can vary is the ‘valid input window’ as shown in Figure 3.
 Figure 3 Valid input window

13.Timing and No-timing issues.

Ans: Timing issues occur due to timing related issues by comparing SDF file .
In Simulation, timing inputs
 TB
 ATPG patterns
 Scan Insertions netlist
 Verilog libraries
 SDF File
No-timing issues occur due to missing setup and libraries.
In Simulation, No-timing inputs
 TB
 ATPG patterns
 Scan insertions netlist
 Verilog libraries

14.How you debug Serial Patterns.

Ans: To debug serial patterns, first you have to check where chain test are
passing or not.
 i) If chain test is passing it mean shift path is clear, then issue will be at
capture mode. So we have to check where in capture mode capture
pulse are pulsing properly or not.
ii) If capture pulse are not pulsing we have to observe OCC output pins,
if it is not pulsing the capture pulse, then we have to analyse input
and control pins of OCC.
If chain test fails then you have to observe that due to which scan
FFs, we are getting simulation mismatches. To find scan cell we have to use
divide and conquer rule

15.If you have controllability but no observability at a node, how do you

resolve it? (Vice-Versa)
Ans: To get controllability on a particular node we need to replace with a
MUX/ OR gate.
Example:
If you take MUX , then MUX output connected to a node and one of the
input connected to actual input when are connected to a node , another
input should connected to test point/pin where you have controllability and
selected pin will connected to test point/pin where you have controllability.
To get observability on a particular node we need to replace with a
non functional scan FFs.
Example:
If you take non functional scan FFs, then it data pin connected to a node.
There you can observe data.

16. In simulation, Parallel patterns are failing but serial patterns are passing
why? (Vice-Versa)
Ans: In simulations, parallel patterns values are forced into input pins of the
scan FFs. If the patterns are not forced properly, parallel patterns will fail,
even though serial patterns pass.
 If parallel patterns are passing but serial patterns are failing, it is due
to scan chain path; in parallel we will force the patterns into scan FFs. But in
serial will shift the patterns into scan FFs. Serial patterns will fail due to
chain test failure or due to missing of capture pulse (scan/capture).