COUNTER

INTRODUCTION TO COUNTER
➢ Counter is a sequential circuit.
➢ A digital circuit which is used for a counting pulses is known counter.
➢ Counter is the widest application of flip-flops. It is a group of flip-flops with a clock signal applied.
➢ Counters are of two types: 1. Asynchronous or ripple counters.
2. Synchronous counters.
 INTRODUCTION TO COUNTER
➢Depending on the way in which the counting progresses, the synchronous or asynchronous counters are
classified as follows − i) Up counters ii) Down counters iii) Up/Down counters

➢ An up counter is a counter which counts in the upward direction, i.e 0, 1, 2, 3, 4,…….., N.

➢ An down counter is a counter which counts in the downward direction, i.e 0, N, N-1, N-2, N-3,……...,1, 0.

➢ Each of the counts of the counter is called the state of the counter.

➢ The number of states through which the counter passes before returning to the starting state is called the
modulus of the counter.

➢ So, the Modulus of the counter is equal to the total number of distinct state.

➢The 2-bit ripple counter is called as MOD-4 counter and 3-bit ripple counter is called as MOD-8 counter. So in
general, an n-bit ripple counter is called as modulo-N counter. Where, MOD number = 2n.
 Asynchronousor ripple counters
➢An arrangement of a group of flip-flops in a predetermined manner forms a binary counter. The applied
clock pulses are counted by the counter.

➢ Asynchronous counters are those counters which do not operate on simultaneous clocking.

➢ In asynchronous counter, only the first flip-flop is externally clocked using clock pulse while the clock
input for the successive flip-flops will be the output from a previous flip-flop.

➢ This means that only a single clock pulse is not driving all the flip-flops in the arrangement of the
counter.

➢Asynchronous counters are also known as ripple counters and are formed by the successive combination
of trailing edge-triggered flip-flops.

➢ It is called so because the data ripples between the output of one flip-flop to the input of the next.
 Asynchronousor ripple counters
Two bit ripple up counter using negative edge triggered flip flop
Three bit ripple up counter using negative edge
triggered flip flop

Here as we can clearly see that 3 bit negative edge-triggered flip-flops are sequentially connected where the
output of one flip-flop is provided as the input to the next. The input clock pulse is applied at the least
significant or the first most flip-flop in the arrangement.
 Three bit ripple up counter using negative edge
triggered flip flop

➢Initially when the clock input is applied at the LSB flip-flop i.e., A then the output QA will change from 0 to 1 at
the falling edge of the clock pulse. As we can see that at the first count of a clock pulse at the falling edge,
QA toggles from 0 to 1. Further QA holds its state 1 and toggles from 1 to 0 only when another falling edge of the
clock input is received. Again QA toggles from 0 to 1 at the next falling edge of the input clock pulse.

➢We know that only the first flip-flop is triggered with an external clock signal. So, now the output of flip-flop A
will act as the clock input for flip-flop B and the external clock signal will not be going to affect QB. Therefore, the
further toggling of the QB will depend on the falling edge of QA signal.

➢So, as we can see clearly in the timing diagram that QB undergoes toggling only at the falling edge of the
QA signal. And the clock input signal is not affecting the output of flip-flop B. Further for flip-flop C, the clock
input will now be the output of flip-flop B i.e., QB. So, the output QC will be according to the transition of QB.

➢As we can see in the diagram that first time QC toggles from 0 to 1 only at the first falling edge of QB signal. And
maintains the state till it reaches the next falling edge of QB. So, in this way, we can say that we are not
simultaneously providing a clock input to all the flip-flops in asynchronous counters.
Three bit ripple down counter using
negative edge triggered flip flop
Three bit ripple up counter using
positive edge triggered flip flop
four bit ripple up counter using
positive edge triggered flip flop
 Two bit ripple up-down counter
using negative edge triggered flip
flop
 SYNCHRONOUSCOUNTER
➢ In this type of counter there is no connections between the output of first flip
flop and clock input of next flip flop and so on.

➢ All the flip flops are clocked simultaneously.

➢ Design and implementation is complex.

➢Since clock is applied to all the flip flop simultaneously the total propagation
delay is equal to the propagation delay of only one flip flop. Hence they are faster.
Difference Between Asynchronous&
SynchronousCounter
DESIGN OF SYNCHRONOUSCOUNTER

➢ Step 1: No of flip flops ( N < 2 )

n
➢ Step 2: State Diagram

➢ Step 3: Choice of flip flops and Excitation Table

➢ Step 4: SOP Expression from Excitation Table

➢ Step 5: Minimal Expressions For Excitations using K-Map

➢ Step 6: Logic Diagram

 DESIGN OF SYNCHRONOUS 3BITUP DOWN
COUNTER USING J-K FLIP FLOPS

❖ Step 1: Determine the No of flip flops

✓ No of flip flops:3

✓ No of states : 8

✓ All states are valid.

✓ For selecting up and down modes, a control or mode signal M is required.

✓ M=1 for Up Counting and M=0 for Down Counting

 Step 2: State Diagram
1

000 001

0 1
1
0
0
010
111

1 0 0 1

110 011

0 0
0 1
1

101 100

1
Step 3: Choice of flip flops and Excitation Table
Present State Mode Next State Required Excitations

Q3 Q2 Q1 M Q3 Q2 Q1 J3 K3 J2 K2 J1 K1

0 0 0 0 1 1 1 1 × 1 × 1 × ✓J-K flip flop

0 0 0 1 0 0 1 0 × 0 × 1 × are selected
0 0 1 0 0 0 0 0 × 0 × × 1

0 0 1 1 0 1 0 0 × 1 × × 1

0 1 0 0 0 0 1 0 × × 1 1 ×

0 1 0 1 0 1 1 0 × × 0 1 ×

0 1 1 0 0 1 0 0 × × 0 × 1

0 1 1 1 1 0 0 1 × × 1 × 1
 Step 3: Continued
Present State Mode Next State Required Excitations
Q3 Q2 Q1 M Q3 Q2 Q1 J3 K3 J2 K2 J1 K1
1 0 0 0 0 1 1 × 1 1 × 1 ×
1 0 0 1 1 0 1 × 0 0 × 1 ×
1 0 1 0 1 0 0 × 0 0 × × 1
1 0 1 1 1 1 0 × 0 1 × × 1
1 1 0 0 1 0 1 × 0 × 1 1 ×
1 1 0 1 1 1 1 × 0 × 0 1 ×
1 1 1 0 1 1 0 × 0 × 0 × 1
1 1 1 1 0 0 0 × 1 × 1 × 1
Step 4: SOP Expression From Excitation Table

J 3 =  m (  ) +  d (8,9,1 0,11,1 2,1 3,1 4,1 5)

K 3 =  m (   ) +  d (0,1,2,3,4,5,6,7 )

J 2 =  m ( 0 , 3 , 8 , 11 ) +  d (4,5,6,7,12,13,14,15)

K 2 =  m ( 4 ,7 ,1 2   ) +  d ( 0 ,1,2 ,3,8 ,9 ,1 0 ,1 1)
 Step 5: Minimal Expressions For
Excitations using K-Map
Q1M
Q3Q2 00 01 11 10
0 1 3 2
00 1
4 5 7 6
J 3 = () + d(8,9,10,11,12,13,14,15) 01 1
12 13 15 14
11 × × × ×
DO IT YOURSELF
8 9 11 10
10 × × × ×

J3 = Q2’Q1’M’+Q2Q1M
 STEP 6:LOGIC DIAGRAM

M
1
J1 J2 Q2 J3 Q3
Q1
> > >
K1 Q1’ K2 Q2’ K3 Q3’

CLK
 DESIGN OF SYNCHRONOUS 3 BIT UP
COUNTER
❖ Step 1: Determine the No of flip flops: 3

❖ Step 2: State Diagram

000 001

010
111

011
110

101 100
 Step 3: Choice of flip flops and
Excitation Table
Present State Next State Required Excitations

Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1

0 0 0 0 0 1 0 × 0 × 1 ×

0 0 1 0 1 0 0 × 1 × × 1

HERE WE USE J-K 0 1 0 0 1 1 0 × × 0 1 ×

FLIP FLOP 0 1 1 1 0 0 1 × × 1 × 1

1 0 0 1 0 1 × 0 0 × 1 ×

1 0 1 1 1 0 × 0 1 × × 1

1 1 0 1 1 1 × 0 × 0 1 ×

1 1 1 0 0 0 × 1 × 1 × 1
Step 4: SOP Expression From Excitation Table

J 3 =  m ( 3 ) +  d (4,5,6,7 )

K 3 =  m ( 7 ) +  d (0,1,2,3)

J 2 =  m (1,5 ) +  d ( 2 ,3,6 ,7 )

K 2 =  m ( 3,7 ) +  d ( 0 ,1,4 ,5 )
 Step 5: Minimal Expressions For
Excitations using K-Map

Q2 Q1
Q3 00 01 11 10
0 1 3 2
J 3 =  m (3 ) +  d (4,5,6,7 ) 0 1
4 5 7 6
1 × × × ×

DO IT YOURSELF
J3 = Q2Q1
 DESIGN SYNCHRONOUS
MOD 6COUNTER
❖ Step 1: Determine the No of flip flops.

✓ The number of states through which the counter passes before returning
to the starting state is called Modulus of Counter.
✓ No of states : 6
✓ No of Flip Flops: 3 (N < 2 i.e 6 < 2 )
✓ 3 Flip flops have 8 states. So, the remaining two states 110 and 111 are
invalid.
 Step 2: State Diagram

111
000 001
110

101 010

INVALID STATES 100 011

 Step 3: Choice of flip flops and
Excitation Table

Present State Next State Required Excitations

Q3 Q2 Q1 Q3 Q2 Q1 J3 K3 J2 K2 J1 K1

0 0 0 0 0 1 0 × 0 × 1 ×
HERE WE USE J-K
FLIP FLOP
0 0 1 0 1 0 0 × 1 × × 1

0 1 0 0 1 1 0 × × 0 1 ×

0 1 1 1 0 0 1 × × 1 × 1

1 0 0 1 0 1 × 0 0 × 1 ×

1 0 1 0 0 0 × 1 0 × × 1
Step 4: SOP Expression From Excitation Table

J 3 =  m ( 3 ) +  d (4,5,6,7 )

K 3 =  m (5 ) +  d (0,1,2,3,6,7 )

J 2 =  m (1) +  d ( 2 ,3,6 ,7 )

K 2 =  m ( 3 ) +  d ( 0 ,1,4,5 ,6 ,7 )

STEP 5 & STEP 6

DO IT YOURSELF
Problem:
Design synchronous up counter for sequence: 0 → 1 → 3 → 4
→ 5 → 7 → 0, using T flip-flop.

❖ No of flip flops: 3
❖ For given sequence, state transition diagram as following:
State Transition Table Logic & State Transition Table

PRESENT NEXT PRESENT STATE NEXT STATE

STATE STATE
Q3 Q2 Q1 Q3 Q2 Q1
0 1
0 0 0 0 0 1
1 3 0 0 1 0 1 1
3 4 0 1 1 1 0 0
4 5 1 0 0 1 0 1
5 7 1 0 1 1 1 1
7 0 1 1 1 0 0 0
 EXCITATION TABLE
PRESENT INPUT TABLE OF FLIP-
QT Q(T+1) T
NEXT STATE
STATE FLOPS
0 0 0 Q3 Q2 Q1 Q3 Q2 Q1 T3 T2 T1
0 1 1
0 0 0 0 0 1 0 0 1
1 0 1
0 0 1 0 1 1 0 1 0
1 1 0
0 1 1 1 0 0
1 1 1
1 0 0 1 0 1
0 0 1
1 0 1 1 1 1
0 1 0
1 1 1 0 0 0
1 1 1
Find value of T3 , T2 , T1 in Terms of Q3 , Q2 , Q1 using K-Map

T3 = Q2 T =Q +Q
2 1 2

T =Q’
1 2
BLOCK DIAGRAM
SHIFT REGISTER COUNTER
4 BIT RING COUNTER
 4 BIT RING COUNTER
CLOCK
PULSE QA QB QC QD
1000 0 0 0 0 1
1 1 0 0 0
0001
0100
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
0010

5 1 0 0 0
STATE DIAGRAM
6 0 1 0 0
7 0 0 1 0

SEQUENCE TABLE
TIMING DIAGRAM OF 4 BIT RING
COUNTER
4 BIT JOHNSON COUNTER
 4 BIT JOHNSON COUNTER
CLOCK
Q0 Q1 Q2 Q3
PULSE
0 0 0 0 0
0000 1000
1 1 0 0 0
2 1 1 0 0
0001 1100
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
1110 6 0 0 1 1
0011
7 0 0 0 1
8 0 0 0 0
0111 1111
9 1 0 0 0
TIMING DIAGRAM OF 4 BIT RING
COUNTER
 Finite State Machine
➢ FSM is a calculation model that can be executed with the help of hardware otherwise software. This is
used for creating sequential logic as well as a few computer programs.

➢FSMs are used to solve the problems in fields like mathematics, games, linguistics, and artificial
intelligence. In a system where specific inputs can cause specific changes in state that can be signified
with the help of FSMs.
➢A synchronous sequential circuit is also called as Finite State Machine FSM, if it has finite number of states.
There are two types of FSMs.
✓ Mealy State Machine
✓ Moore State Machine

Mealy State Machine: A Finite State Machine is said to be Mealy

state machine, if outputs depend on both present inputs & present
states. The block diagram of Mealy state machine is shown in the
following figure.
As shown in figure, there are two parts present in Mealy state
machine. Those are combinational logic and memory. Memory is
useful to provide some or part of previous outputs present states as
inputs of combinational logic. So, based on the present inputs and
present states, the Mealy state machine produces outputs. Therefore,
the outputs will be valid only at positive or negative transition of the
clock signal.
Finite State Machine

In the figure, there are three states,

namely A, B & C. These states are labelled
inside the circles & each circle
corresponds to one state. Transitions
between these states are represented with
directed lines. Here, 0 / 0, 1 / 0 & 1 / 1
denotes input / output. In the above figure,
there are two transitions from each state
based on the value of input, x.
In general, the number of states required
in Mealy state machine is less than or
equal to the number of states required in
Moore state machine. There is an
equivalent Moore state machine for each
Mealy state machine.
Moore State Machine
A Finite State Machine is said to be Moore state machine, if outputs depend only on present states. The block
diagram of Moore state machine is shown in the following figure.

➢In the above figure, there are four states, namely A, B, C & D. These states and the respective outputs are labelled inside the circles.
Here, only the input value is labelled on each transition. In the above figure, there are two transitions from each state based on the value
of input, x.

➢In general, the number of states required in Moore state machine is more than or equal to the number of states required in Mealy state
machine. There is an equivalent Mealy state machine for each Moore state machine. So, based on the requirement we can use one of
them.
Pulse Train Generator
➢ Pulse generators are items of electronic test equipment that are used to generate pulses - normally rectangular
pulses.
➢ Typically pulse generators will provide a number of functions and capabilities:

➢ Rectangular wave generation : As the name implies a pulse generator is designed to produce pulses that are rectangular in nature,
often capable of driving logic circuitry, although they are not necessarily confined to just this type of application.

➢ Pulse width: In order to produce a variety of waveforms, the pulse width can be varied.

➢ Repetition rate : The repetition rate is a key parameter. When used in a "free run" mode, the repetition rate can be varied.

➢Pulse trigger: Using an external waveform, it is possible to trigger the pulse generator. Pulse triggering can normally occur on
either the negative or positive edge via a selection switch.

➢ Pulse delay: When a pulse is triggered it is normal to be able to select a delay for the pulse from the pulse generator. This delay is
adjustable.

➢ Pulse amplitude: Although the pulse amplitude will normally be required to drive logic circuits, the amplitude is normally
adjustable. If nothing else this is required because there are many standard logic levels in use today.

➢ Pulse rise and fall times: For some applications it may be necessary to be able to adjust the rise and fall times of the logic outputs.
This facility is available on many pulse generators.
 Do It Yourself
1. What is Counter? What are its types?
2. Explain the terms Synchronous and Asynchronous.
3. What is the difference between Synchronous and asynchronous counter?
4. What are the merits and demerits of synchronous counter over asynchronous counter?
5. Explain the working of 4-bit ripple up counter using J-K flip-flop with suitable circuit diagram and timing
diagram.
6. Explain the working of 4-bit ripple down counter using J-K flip-flop with suitable circuit diagram and timing
diagram.
7. What do you mean by Ring Counter? Explain it with truth table and timing diagram.
8. Explain with truth table and waveforms a 4-bit Johnson Counter.
9. Explain with help of neat and clean diagrams the working operation of i) SISO ii) SIPO iii) PISO iv) PIPO.
10. Design a Synchronous 3-bit up counter.
11. Design a Synchronous 3-bit down counter.
12. Design a Synchronous 3-bit up-down counter.
13. Design a MOD-3 counter.
14. Design a MOD-6 counter.
15. Design a MOD-10 counter.