‫قسم الهندسة الكهربائية‬

‫المستوي الثالث‬
‫بكالريوس كهرباء‬
‫‪Digital Electronics2‬‬
‫الكترونيات رقمية‪2‬‬
‫‪Lecture3‬‬
‫‪Dr. Mugahid Omer Hajeltoum‬‬
 Counters

• A counter is a sequential digital device,

which is used for counting ( up or down).
• Counters construct of flip-flops plus
combinational circuits.
• Types of counters
o Asynchronous (Ripple) counters.
o Synchronous (parallel) counters.
 Asynchronous Ripple Counter

• In asynchronous counters each flip flop output serves

as the clock input signal for the next FF in the
sequence.
• The FFs don’t change states at exactly the same time
as they don’t have a common clock pulse.
• A ripple counter consists of n FFs , the number of its
states equals 2n , and It can count from 0 to (2n -1).
 Asynchronous Ripple Counter

• Binary counter : Group of FFs connected in a

special arrangement in which the states of FF
represent the binary number equivalent to the
number of pulses that have occurred at the input of
the counter.
• Binary ripple counter is called also, a Mod-X
counter, where X is the number of counter states
and its equal to 2n , for n FFs .
• The first FF in the counter is called LSB , and the
last FF is called MSB.
• The output of MSB divides the input clock
frequency by X
 Asynchronous Ripple Counter

• The figure below shows a 4-bit binary counter (Mod-16) :

• The clock pulse applied only to the Clk input of flip flop A.
• FF A will toggle each time the clock pulse make a transition.
• Since The output of FF A is the input of FF B ,FF B will
toggle each time the output of FF A goes from 1 to 0 , and so
on.
QA QB QC QD
 Asynchronous Ripple Counter

• FF A responds to the clock

pulses. FF B has to wait for FF A
to change states before its
toggled , and so on.
• Thus, all FFs don’t changes
states in exact synchronism with
the clock pulse. And because of
that it is called asynchronous
counters.
• After 15 clock pulse , the counter
recycle back to count (0000) .
Timing diagram of 4-bit Ripple Counter
4-bit Ripple Counter using T FF
 Example

Design 2- bit binary ripple counter using

JK FF
State diagram

Logic diagram

Timing Truth table

diagram
Q1 Q
Q00
 Truncated Ripple Counter

• In the previous slides we know how to design a

binary ripple counters with mod number=2n, where
n equals the number of FFs, like Mod-5, Mod-6 or
Mod-16
• What about Mod-5, Mod-6 or Mod 15 counters?
• How we can design a counter with mod number ≠
2n ?
• By allowing the counter to skip states that are
normally part of the counting sequence. The
resulting sequence is called truncated sequence.
 Truncated Ripple Counter

• One of the most common to obtain a truncated sequence is

explained in the figure above, where a 3-bit binary counter
connected to a NAND gate which connected to asynchronous
clear input of the flip-flop.
• Without the NAND gate the counter is a 8-Mod binary
counter, which will count from 000 through 111.
• When the NAND output goes low, it will clear all the FFs
 Truncated Ripple Counter

• The inputs of the NAND gate are the CB

A
outputs of the B and C FFs.
000
• So, the NAND output will go low
001
whenever B=C=1. This condition will
010
occur when the counter goes from 101 to
011
110.
100
• Thus , we can say that this counter counts
101
from 000 (0) to 101 (5) and then recycles
110
to 000.
• It is essentially skips 110 and 111 so that Temporary
it goes through only six different states. state
needed to
• Thus , it is a Mod-6 counter. clear
counter
 Truncated Ripple Counter

• Mod-6 counter
produced by clearing a
Mod-8 counter when
count of 6 (110) occurs
• The waveform at the B
output contains a spike
Timing diagram
caused by the
momentary occurrence
of the 110 state before
clearing.
State diagram
 General Procedure for Designing MOD-X
Ripple Counter

1. Find the smallest number of FFs such that X ≤ 2 n .

2. Connect them as counter. “If X = 2n , don’t do steps 3
and 4”.
3. Connect a NAND gate to the synchronous Clear inputs
of all the FFs.
4. Determine which FFs will be in high state at a count=X;
then connect the normal outputs of these FFs to the
NAND gate inputs.
 Example
Design MOD-10 counter
• 23 = 8 , 24 = 16 .
DCB
• Thus, the number of FFs we have to use is 4 FFs. A
• Connect the FFs as a counter 0000
• Mod-10 counter will count from 0000 through 1001. 0001
• So, it must be rest to 0000 state when the count of 1010 is 0010
reached. 0011
0100
0101
0110
0111
Q’ Q’ 1000
1001
1010
 Example

Mod-10 counter produced by clearing a Mod-16 counter when count

of 10 (1001) occurs

State Diagram Timing Diagram

 Asynchronous Down Counters

• The ripple down counters, will count downward

from maximum count to 0.
Stat CB
• It works in the same method that the ripple up e A
counters works. 7 111
6 110
5 101
4 100
3 011
2 010
1 001
0 000
Mod-8 down ripple counter
 Asynchronous Down Counters
Mod-8 down ripple counter timing diagram

Mod-8 down ripple

counter state diagram
 Asynchronous Bidirectional Counters
• This counter designed to count in both directions up and down.
• It counts up or down depending on the status of the control signals
UP and DOWN
• When the UP input is at 1 and the DOWN input is at 0, the NAND
network between FF0 and FF1 will gate the non-inverted output
(Q) of FF0 into the clock input of FF1, and so on for the next FFs.
Thus the counter will count up.

3-bit bidirectional ripple counter

 Asynchronous bidirectional Counters
• When the UP input is at 0 and the DOWN input is at 1, the
NAND network between FF0 and FF1 will gate the inverted
output (Q) of FF0 into the clock input of FF1, and so on for the
next FFs. Thus the counter will count down .
Up CBA Down CBA
states states
0 000 7 111
1 001 6 110
2 010 5 101
3 011 4 100
4 100 3 011
5 101 2 010
6 110 1 001
7 111 0 000
 Synchronous (Parallel) Counter

• An asynchronous suffers from what is known as

“Propagation Delay” in which the timing signal is
delayed a fraction through each flip-flop.

• All the individual output bits changing state at exactly

the same time in response to the common clock signal
with no ripple effect and therefore, no propagation
delay.
Synchronous Binary Counter
 Synchronous Binary Counter
• The external clock pulses are fed directly to each of the J-K flip
flops in the counter chain and that both the J and K inputs are all
tied together in toggle mode.
• But only in the first flip-flop, flip-flop FFA (LSB) are they
connected HIGH, logic “1” allowing the flip-flop to toggle on
every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock
signal, advancing one state for each pulse.
• The J and K inputs of flip-flop FFB are connected directly to the
output QA of flip-flop FFA
• The J and K inputs of flip-flops FFC and FFD are driven from
separate AND gates which are also supplied with signals from the
input and output of the previous stage.
• And the additional AND gates generate the required logic for the
JK inputs of the next stage.
 Design Procedure for a Synchronous
Counter

Procedure to design a parallel counter :

1.Determine the number of FF you have to use.
2.Obtain the state diagram.
3.Obtain the excitation table using state transition
table for any particular FF .
4.Obtain and simplify the function of each FF input
using K-map.
5.Draw the circuit.
 Example

• Design a Mod-4 synchronous counter

1. 2n = 4 n = 2 FFs

2. State transition diagram

 Example

Q (t) Q(t+1) J K

0 0 0 X
3. The excitation table 0 1 1 X
1 0 X 1
1 1 X 0

Present state Next state Inputs J and K

B A B A JB KB JA KA
0 0 0 1 0 X 1 X
0 1 1 0 1 X X 1
1 0 1 1 X 0 1 X
1 1 0 0 X 1 X 1
 Example

4. Simplified functions using K-map

A A
B B

A A
B
B

5. Circuit diagram
 Advantages of synchronous counters over
Asynchronous :

• In parallel counter all the FFs will change states

simultaneously .Thus ,unlike the asynchronous counters , the
propagation delays of the FFs do not add together to produce
the of overall delay .
• The total response time of a synchronous counter is the time
it take one FF to toggle plus the time for the new logic levels
to propagate through a signal AND gate to reach the J,K
inputs.
 Random Counters
Example: Design synchronous counter to count the following
sequence 0-1-2-4-5-6 and repeat the sequence using T FF

Excitation table
F.F
 Random Counters

Simplified functions using K-map

Random Counters

Logic diagram
 Advantages of synchronous counters over
Asynchronous :

• In parallel counter all the FFs will change states

simultaneously .Thus ,unlike the asynchronous counters , the
propagation delays of the FFs do not add together to produce
the of overall delay.
• The total response time of a synchronous counter is the time
it take one FF to toggle plus the time for the new logic levels
to propagate through a signal AND gate to reach the J,K
inputs.
 Exercise 9

1. In order to connect up a circuit of JK FFs as an asynchronous up

counter , you have to:
A.Set J=K=1, connect Q output to the clock of the next FF.
B.Set J=K=1, connect Q output to the clock of the next FF.
C.Set J=K=0, connect Q output to the clock of the next FF.
D.Set J=K=0, connect Q output to the clock of the next FF.

2. Design a Mod-16 ripple down counter using negative trigger.

3. Design a Mod-8 synchronous up counter .