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Fresher Interview Questionnaire

The document outlines a series of questions and topics related to digital electronics, Verilog, System Verilog, and aptitude, along with a self-assessment report. It highlights areas of weakness in problem-solving and fundamental concepts, particularly in digital design and coding applications. The report also provides a plan for improvement through practice and revision of relevant materials.

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Saikrishna Garlapati
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6 views6 pages

Fresher Interview Questionnaire

The document outlines a series of questions and topics related to digital electronics, Verilog, System Verilog, and aptitude, along with a self-assessment report. It highlights areas of weakness in problem-solving and fundamental concepts, particularly in digital design and coding applications. The report also provides a plan for improvement through practice and revision of relevant materials.

Uploaded by

Saikrishna Garlapati
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Digital:

1. How many 2:1 multiplexers will you need to design a 2 n :1 MUX?


2. What is a ring oscillator? What would be the frequency of a ring oscillator
implemented using three NOT gates if each gate has a delay of 2 ps?

3. What is the difference between Synchronous and Asynchronous circuits?


4. Setup, hold? For a given sequential circuit as shown below, assume that
both the flip flops have a clock to output delay = 10ns, setup time=5ns
and hold time=2ns. Also assume that the combinatorial data path has a
delay of 10ns. Calculate the maximum frequency of CLKA that is possible
for design to operate correctly?

5. What is the minimum number of flip-flops required to implement a digital


synchronous circuit with 9 states?
6. Design a sequence detector state machine that detects a pattern “10110”
from an input serial stream. Use D Flip-Flops.
7. What are the different steps in a typical ASIC or SOC design flow?

Verilog:
8. How many flip-flops will be needed when following two codes are
synthesized?
a)
always @(posedge clk) begin
B = A;
C = B;
end
b)
always @(posedge clk) begin
B <= A;
C <= B;
End
9. What is the output of following code?

module test;
int alpha,beta;
initial begin
alpha = 4;
beta = 3;
beta <= beta + alpha;
alpha <= alpha + beta;
alpha = alpha - 1;
$display(“Alpha=%0d Beta=%0d”, alpha,beta);
end
endmodule

10. What will be the value of “c” in following 2 cases (after 5 sim units)?
1)
initial begin
a=0; b=1;
c = #5 a+b;
end
2)
initial begin
a=0; b=1;
#5 c = a+b;
end
initial begin
a=0;
#3 a=1;
End
11. Task vs Function?

System Verilog:
12. What is the difference between private, public and protected data
members of a System Verilog class?
13. What are interfaces in SystemVerilog? What are modports? What is a
clocking block and what are the benefits of using clocking blocks inside an
interface?
14. How can we disable or enable constraints selectively in a class?
15. Will there be any difference in the values generated in following
constraints?
1)
class ABSolveBefore;
rand bit A;
rand bit [1:0] B;
constraint c_ab {
(A==0) -> B==0;
solve A before B;
}
endclass
2)
class ABSolveBefore;
rand bit A;
rand bit [1:0] B;
constraint c_ab {
(A==0) -> B==0;
solve B before A;
}
Endclass

16. How can we use constraints to generate a dynamic array with random
but unique values? Refer to the code below:
class TestClass;
rand bit[3:0] my_array[]; //dynamic array of bit[3:0]
endclass
17. What is the use of “wait fork” and “disable fork” constructs?
18. How many parallel processes does this code generate?
fork
for (int i=0; i < 10; i++ ) begin
ABC();
end
join
19. What is an abstract class? What is a virtual and pure virtual function?
20. Is overriding a constraint in the derived class possible?
class Base;
rand int a ;
rand int b;
constraint c_a_b_const {
a < b;
}
endclass

class Derived extends Base;


constraint c_a_b_const {
a > b;
}
Endclass
21. In SV, can a base class handle hold a derived class object or is it
reverse?
22. What are the differences between Immediate and Concurrent
assertions?

UVM:

Aptitude:
23. a/2 = b/3 = c/5, the value of (a+b+c)/c is
24. Key presses
25. A man covers a distance on scooter. Had he moved 3 kmph faster he
would have taken 40 min less. If he had moved 2 kmph slower, he would
have taken 40 min more. The distance is
26. Three numbers are in the ratio 3:4:5. The sum of the largest and the
smallest equals the Sum of the third and 52. The smallest number is
27. Two trains start from A & B and travel towards each other at speed of
50kmph and 60kmph resp. At the time of the meeting the second train
has traveled 120km more than the first. The distance between them in km
is?
Report:
Digital: 3/10
Drawbacks:
- Lack of exposure, practice in problem solving in digital electronics
involving basic gates like muxes, inverters and sequential circuit
diagrams, delays and FSMs and its implementation using flops, STA.
(4th question, 6th ques)
- Weak with fundamentals and basics. Need to be strong at basics
and solve the problems by referring basic concepts. (2 nd question,
5th question)
- Inability to arrive at the correct solution through analytical
procedure/logical reasoning, giving incorrect reasoning (1 st question)
- Need to build basic knowledge about ASIC design flowchart and be
strong at important theoretical questions. (7 th question)
- Not thinking out loud while solving the problem so that interviewer
could get an idea about your approach. Need to explain the
interviewer the solution approach properly.
- Need to be sure of your answer whether it is right or wrong. Don’t
be blank or give half-hearted answer. If not able to answer, be
curious to know/discuss with the interviewer by telling him what you
know.

To do:
- Practice the interview preparation material drastically improve
exposure to problem solving at the areas mentioned above (all the
three documents that I sent and problems in Morris mano textbook)

Verilog: 5/10
- Good with the knowledge, bad at application and problem solving.
- Need to be increase problem solving by understanding code-
snippets with the concepts of blocking/non-blocking, delays etc

To do:
- Revise, revise, revise and go through interview questions and get
familiar with different code snippets and writing code of basic blocks
in Verilog.

System Verilog: 6/10


- Good knowledge and application.
- Need to practice and go through many more possible interview
questions involving interfaces, clocking blocks, OOPS, constraints,
assertions.

To do:
- Same as for Verilog, including the areas mentioned for System
Verilog above.

Aptitude: 7/10
- Good, need to improve speed and exposure to trickier and wider
range of problems.

To do:
- Practice from the material/internet.

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