Full Digital IC Design

Diploma (#012)
Diploma Scheduling (100 hrs.) Course sessions dates

Thursday 1 August
The Diploma will start at Thursday 1 August, 2024
Friday 2 August
and then end at Friday 12 October, 2024.
Thursday 8 August

Friday 9 August
The sessions will be every week on Thursday
and Friday for 11 weeks (22 sessions) Thursday 15 August
Friday 16 August
Thursday 22 August
Session duration: 4.5 hours
Friday 23 August
Thursday 29 August

Target Audience: Friday 30 August

 Graduated Electronics and Thursday 5 September

Communication Engineers Friday 6 September
 Graduated Computer Engineers Thursday 12 September
 Senior Electronics and Communication Friday 13 September
department students
 Senior Computer department students Thursday 20 September

Friday 21 September
Thursday 27 September

About the Instructor: Friday 28 September

Thursday 4 October
Ali Eltemsah is a Senior Digital IC Design Friday 5 October
Engineer with +5 years of industrial technical Thursday 11 October
experience. He worked for +2 years at S-
Friday 12 October
Vision and +3 years at MEMS-Vision

LinkedIn:
https://www.linkedin.com/in/ali-m-eltemsah-
25a81b12a/

Facebook:

https://www.facebook.com/profile.php?id=100001579
355627
Program Modules
This Diploma is designed to allow the people who are passionate about Digital IC
Design field to put them on the road and give them a much better understanding of
all the basics as well as advanced concepts and gaining enough technical skills
needed to be ready to works in the field.
The diploma will start from the writing a professional Verilog code to describe your digital
circuit through HDL language and then building a Verilog environment to verify design
and fix bugs and then going through the ASIC flow staring from synthesizing your HDL
code and see the impact of your code on power, area and speed and then prepare your
chip for fabrication and testing as well as learn some TCL scripting skills needed to be
ready to automate the EDA tools needed through the diploma

Course Structure
Module 1 (21 hrs.)

Verilog HDL Language (Theoretical+ Practical)

Module 2 (5 hrs.)

Power Aware Design (Theoretical+ Practical)

Module 3 (5 hrs.)

Clock Domain Crossing (Theoretical+ Practical)

Module 4 (9 hrs.)

TCL Scripting Language (Theoretical+ Practical)

Module 5 (20 hrs.)

Logic Synthesis (Theoretical+ Practical)

Module 6 (5 hrs.)

Formal Verification (Theoretical+ Practical)

Module 7 (10 hrs.)

DFT (Theoretical+ Practical)

Module 8 (20 hrs.)

ASIC Flow (Place & Route) (Theoretical+ Practical)

Module 9 (5 hrs.)

Post-layout Verification (Gate Level Simulation) (Practical)

MODULE 1

Verilog HDL Language

Overview
This Module will provide you with a sound knowledge of the Verilog
hardware description language (HDL) as Verilog becomes the most dominant HDL
used around the world. It will include Verilog Basics as well as advanced topics. It
helps you to write an optimized synthesizable parameterized HDL code as well
as developing a very advanced self-checking test-bench to test your design.

Syllabus:

 Introduction to Verilog  Structural Verilog and module

 Verilog Coding styles instantiation
 Structure of Verilog Module  Parameter & localparam
 Module Declaration  Multidimensional arrays
 Port Declaration  Functions & Tasks.
 Verilog Data Types  For Generate
 Procedural Blocks  IF Generate
o always block  Simulation Race
o initial block o Read-Write Race
 Sensitivity List o Write-Write Race
 Unintentional Latch Inference
 Continuous Assignment
 Simulation synthesis mismatch
 If-else statement
 Incomplete Sensitivity list
 Case statement
 Combinational Loops
 Blocking & Non-Blocking
Assignment  Finite State Machine
o Mealy FSM
 Specifying Numbers in Verilog
o Moore FSM
 Verilog Operators  State Vector Encoding
 Verilog System Functions o Minimal Encoding
 Verilog Time Scale/precision o Gray Encoding
 Synthesizable For Loop o One-Hot Encoding
 Un-Synthesizable Constructs
MODULE 2

Power Aware Design

Overview
Power analysis became a mainstream focus area even for CMOS based
VLSI circuits. This Module will give you a very good understanding of the different
Power Consumption sources in the CMOS Circuits as well as you will learn
different techniques of low power designs.

Syllabus

 Understanding Power Consumption sources

o Leakage Power
o Short Circuit Power
o Static Power
o Glitching Power
o Switching Power
 Understanding Low Power Techniques
o Clock Gating
o Power Gating
o Multiple VTH
o Multiple Voltage Islands
o Different operating frequencies

Projects: -
 Integer Clock Divider
 Clock Gating Unit
MODULE 3

Clock Domain Crossing

Overview
This Module will provide you with the knowledge of clock domain crossing.
Clock Domain Crossing (CDC) in digital domain is defined as the process of
passing a signal or vector (multi bit signal) from one clock domain to another clock
domain which cause many issues can a functional failure to the circuit.

Syllabus:

 Introduction to clock domain crossing

 CDC Problems
o Meta-stability
o Data Incoherence
o Data Loss
 Synchronization techniques
o Multi-Flop Synchronization Scheme
o Multi-Flop/Gray code Synchronization Scheme
o Synchronized Enable Synchronization Scheme
o Synchronized MUX-Select Synchronization Scheme
o FIFO Synchronization Scheme
o Ready-acknowledge handshaking
 FIFO Depth Calculation.
 Reset Synchronizer
MODULE 4

TCL scripting

Overview
This Module will provide you with a good knowledge of TCL language.
TCL language becomes a universal scripting language as most of the EDA tools
support TCL-based scripts.it is a high-level, interpreted, general-purpose, dynamic
programming language, it was designed with the goal of being very simple but
powerful. TCL is string based scripting language. TCL is shortened form of Tool
Command Language as it casts everything into the context of a command.

Syllabus:

 Intro to TCL language

 TCL Basic syntax
 TCL Commands
o Command substitution
o Variable substitution
 Data Types
o String
o List
o Associative Array
 Operators
 Decisions
 Loops
 Procedures
 File I/O
 Regular Expression
MODULE 5

Logic Synthesis

Overview
This Module covers the Logic synthesis flow using Design Compiler,
Logic Synthesis (RTL Synthesis) is the process of transforming your RTL code
Written in HDL (such as Verilog or VHDL) into a gate-level netlist, given all the
specified constraints and optimization settings. Understanding Static Timing
Analysis (STA) and solving the design timing violations, generate timing. Area
and power reports and going through Design Compiler Commands and
developing Synthesis scripts.

Syllabus

• Introduction to Logic Synthesis Flow

• Design Compiler (DC) Flow
• Reading Design in Design Compiler
• Defining Design Environment
• Defining Design and Technology Libraries
• Defining Design Constrains
• Compile Flow and Strategies
• Static Timing Analysis
• Setup Time Check
• Hold Time Check
• Removal Time Check
• Recovery Time Check
• Multicycle Paths
• False Paths
• Design Optimization
• Gate level netlist generation
• Generation of design reports
• Area report
• Timing report
• Power report
• Role of each LIB, DB, SDF, SPF and GDS files
• Developing DC-Tcl scripts to constrain design and run synthesis
MODULE 6

Formal Verification

Overview
This Module will
provide you with the
knowledge and practical of
Syllabus: formal verification process.
Formal Verification refers
to the process of
 Introduction to Formal Verification establishing functional
 Formality Tool Flow equivalence of two designs
 Defining Golden Design without running
simulations. It is used to
 Defining Implementation Design verify the RTL verses
 Defining Technology Libraries netlist post synthesis and
 Defining Design Constrains post
 Verifying Design Equivalence
 Generation reports and review
comparing points through GUI
MODULE 7

DFT (Design For Test)

Overview
This Module will provide you with the knowledge and practical of Design
for Test. DFT refers to the process of testing the design for manufacturing
defects. This process required RTL modifications as well as scan insertions
through synthesis tool.

Syllabus:

 Introduction to DFT
 Controllability and Observability
 Stuck-At Fault Models
 Scan Flip Flop & Scan Chains
 Scan Flip Flop Insertion
 Mechanics of Scan Chains
 Stitching the Chain
 Shift and Capture
 DFT Compiler Flow
o RTL Preparation For DFT.
o Test-Ready Compile
o Configuring scan chain
o Defining the DFT Signals
o Creating Test Protocol
o Performing Pre-DFT Test DRC
o Previewing Scan Insertion
o DFT Insertion
o Performing Post-DFT Test DRC
o Reporting Test Coverage
 Area Impact of Scan Flops
 Timing Impact of Scan Flops
MODULE 8

ASIC Flow (Place & Route)

Overview
This Module will provide you with the knowledge and the practical of
Place & Route Flow. Place & Route Flow is the backend stage that converts the
gate level netlist produced during synthesis into a physical design to be fabricated
on the silicon level on as specific technology node. ASIC flow stages can be
divided into Floor planning, Standard cell placement, Clock tree synthesis, Routing
and chip finishing until generation of GDS file.

Syllabus

• Introduction to Place & Route Flow

• Chip Size Definition
• Pin Placement
• Floorplannig
• Automatic Floorplanning
• Manual Floorplanning
• Hybrid Floorplanning
• Power Planning
• Placement
• Clock Tree Synthesis
• Routing
• Global Routing
• Detailed Routing
• Chip Finishing
• Filler Cells
• Metal Filling
• Timing Closure
• Setup
• Hold
• DRC (Design Rule Checking)
• Chip Finishing
• Parasitices Extraction
• GDS Generation
MODULE 9

Post-layout Verification (Gate Level

Simulation)

Overview
This Module will provide you with a good knowledge of gate level
simulation and its difference verses RTL simulation which is known as functional
simulation as it verifies only the functionality of the design and not consider the
propagation delay of the gates while GLS (Gate Level Simulation) verify
Functionality while considering the actual propagation delay of the gates so it
becomes a great confidence booster in the quality of the design after fabrication.

Syllabus:
Diploma fees:
 Environment Setup
o Vital Technology Libraries
o SDF File
o Post-PNR Netlist
 Developing Self Checking
Testbench
 Learn how to run the simulator
and debug timing as well as
functionality of different paths
 Final Project

Low Power Multi-Clock Digital

Communication System

Final Project Phases: -

1- RTL Design from scratch to all the blocks

2- RTL verification using self-checking Verilog environment including all corner
cases of all system commands
3- Synthesize your design and report clean timing reports and solve
any timing issues as well as area and power reports
4- Insert DFT logic and check timing is still clean, power and area matching
system specifications
5- Going through the ASIC flow and GDS generation
6- Running formal verification post-synthesis, post-dft as well as post PnR
7- Run Gate level simulation post PnR and check Clock domain crossing issues.
Diploma fees:

Regular Fees (deadline 15 July): 4700 LE

This includes: -

- All Diploma Materials Hardcopy.

- Attend all Diploma Sessions & Labs.
- Signed and Verified Certificate.
- Attend any missing sessions in the next courses.
- Center fees

For Registration, Please Follow the steps:

1- Download Game3at+ App

2- Find Ali Eltemsah circle
3- View the circle posts, click on registration form link
4- Please wait to my confirmation on your mail

Cancellation Policy:

- 100 % will be refunded before 15 July

- 80 % will be refunded before first session
- Full payments are non-refundable after first session