Introduction to Combinational Circuit Design

Lab 1: Design of Logic gates

1.1 Introduction
The purpose of this experiment is to simulate the behavior of several of the basic logic gates and
you will connect several logic gates together to create simple digital model.

1.2 Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
1.3 Logic Gates and their Properties
Gate

OR

AND

Description
The output is active high
if any one of the input is
in active high state,
Mathematically,
Q = A+B

Truth Table
A B Output Q
0

0 0

1 1

0 1

1 1 1
The output is active high A B Output Q
only if both the inputs are
in active high
state, 0 0 0
Mathematically,
Q = A.B
0 1 0
1

NOT

0 0

1 1 1
A
Output Q

In this gate the output is

opposite to the input
state, Mathematically,
0
Q=A
1

1
0

Logic Symbol

Pin Diagram

NOR

The output is active high A B Output Q

only if both the inputs are
in active low state, 0 0 1
Mathematically,
Q = A+B
0 1 0
1

NAND

0 0

1 1 0
The output is active high A B Output Q
only if any one of the
input is in active low 0 0 1
state, Mathematically,
Q = A.B
0 1 1
1

0 1

1 1 0
The output is active high A B Output Q
only if any one of the
input is in active high 0 0 0
state, Mathematically,
Q=A B
0 1 1
EXOR

0 1

1 0

7486

1. 4 Pre lab Questions

1.
2.
3.
4.
5.
6.
7.

What is truth table?

Which gates are called universal gates?
Define HDL?
What is the difference b/w HDL and software language?
Define Entity and architecture?
Define identifiers.
A basic 2-input logic circuit has a HIGH on one input and a LOW on the other input, and the
output is HIGH. What type of logic circuit is it?
8. A logic circuit requires HIGH on all its inputs to make the output HIGH. What type of logic
circuit is it?
9. Develop the truth table for a 3-input AND gate and also determine the total number of
possible combinations for a 4-input AND gate.

1.5 VHDL Program for Basic Logic Gates

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
2

use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Logic_gates is
Port ( A, B, : in std_logic;
Y_OR,Y_AND,Y_NOT,Y_NOR,Y_NAND,Y_EXOR : out std_logic);
end Lgic_gates;
architecture LG of Logic_gates is
begin
Y_OR <= A or B;
Y_AND <= A and B;
Y_NOT <= not A ;
Y_NOR <= A nor B;
Y_NAND <= A nand B;
Y_EXOR <= A xor B;
end LG;

1.6 Post lab Questions

1.
2.
3.
4.
5.
6.
7.
8.

What is meant by ports?

Write the different types of port modes.
What are different types of architecture modeling?
Write the use of IEEE.std_logic_1164.all.
What are different types of operators?
What is difference b/w <= and := operators?
What is meant by simulation?
How to give the inputs in modelsim software.

Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification sign.
Answer the pre-lab questions
Complete VHDL code design for all logic gates and output signal waveforms
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the logic gates to
your staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each logic gates
Output signal waveform for all logic gates and its truth table

15 points
15 points

Lab 2: Design of Binary Adders

2.1 Introduction
The purpose of this experiment is to introduce the design of simple combinational circuits, in
this case half adders, half subtractors, full adders and full subtractors.

2.2 Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
2.3 Logic Diagram

Figure 2.1 Half adder

Figure 2.2 Full adder

Figure 2.3 Half subtracter

Figure 2.4 Full subtracter

2.4 Pre lab Questions

1.
2.
3.
4.
5.
6.

What is meant by combinational circuits?

Write the sum and carry expression for half and full adder.
Write the difference and borrow expression for half and full subtractor.
Define component and component instantiation.
What is signal? How it is declared?
What are the different logic state systems in std_logic?

2.5 VHDL Program

// Half Adder
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfadder is
Port ( a, b : in std_logic; sum, carry : out std_logic);
end halfadder;
architecture halfadder of halfadder is
begin
sum <= a xor b;
carry <= a and b;
end halfadder;
TEST BENCH WAVEFORMS FOR HALF-ADDER
Time (n

100

200

300

400

1
1

500

// Half Subtractor
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
5

600

700

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity halfsubtractor is
Port ( a, b : in std_logic; difference, borrow : out std_logic);
end halfsubtractor;
architecture halfsubtractor of halfsubtractor is
signal abar : std_logic;
begin
abar <= not a;
difference <= a xor b;
borrow

<= abar and b;

end halfsubtractor;

TEST BENCH WAVEFORMS FOR HALF-SUBTRACTOR

Time (ns)

100

200

300

400

1
1

500

Differe

Borrow

// Full Adder
// Dataflow Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FA_dataflow is
Port ( A, B, Cin : in std_logic;
SUM, Cout : out std_logic);
6

600

700

800

900

1000

1100

end FA_dataflow;
architecture FA_dataflow of FA_dataflow is
begin
SUM <= A xor B xor Cin;
Cout <= (A and B) or (A and Cin) or (B and Cin);
end FA_dataflow;
// Structural Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity onebitFA is
Port ( a, b, cin : in std_logic; Sum, cout : out std_logic);
end onebitFA;
architecture onebitFA of onebitFA is
component xor2
port (a, b : in std_logic; c : out std_logic);
end component;
component and2
port (a, b : in std_logic; c : out std_logic);
end component;
component or3
port (a, b, c : in std_logic; d

: out std_logic);

end component;
signal y1,y2,y3,y4 : std_logic;
begin
7

a1 : xor2 port map (a,b,y1);

a2 : xor2 port map (y1,cin,sum);
b1 : and2 port map (a,b,y2);
b2 : and2 port map (a,cin,y3);
b3 : and2 port map (b,cin,y4);
d1 : or3 port map (y2,y3,y4,cout);
end onebitFA;
// Dataflow Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity onebitFA_d is
Port ( a, b, cin : in std_logic; sum, cout : out std_logic);
end onebitFA_d;
architecture onebitFA_d of onebitFA_d is
begin
sum <= a xor b xor cin;
cout <= ((a and b)or(a and cin)or(b and cin));
end onebitFA_d;

TEST BENCH WAVEFORMS FOR FULL-ADDER

Time (n

Cin

100

200

300

400

500

600

700

800

1
1
1

900

Co

// Full Subtractor
// Structural Description
8

1000

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity onebitFS is
Port ( A, B, Bin : in std_logic;
D, Bout : out std_logic);
end onebitFS;
architecture onebitFS of onebitFS is
component and3
port ( a,b,c :

in

std_logic; d :

out std_logic);

end component;
component and2
port ( a,b : in std_logic; c : out std_logic);
end component;
component or3
port ( a,b,c : in std_logic; d : out std_logic);
end component;
component or4
port ( a,b,c,d

: in std_logic; e :

out std_logic);

end component;
signal Abar, Bbar, Binbar : std_logic;
signal y : std_logic_vector(6 downto 0);
begin
Abar <= not A;
Bbar <= not B;
9

Binbar <= not Binbar;

x1 : and3 port map (Abar, Bbar, Bin, y(0));
x2 : and3 port map (Abar, B, Binbar, y(1));
x3 : and3 port map (A, Bbar, Binbar, y(2));
x4 : and3 port map (A, B, Bin, y(3));
x5 : or4 port map (y(0), y(1), y(2), y(3), D);
x6 : and2 port map (Abar, Bin, y(4));
x7 : and2 port map (Abar, B, y(5));
x8 : and2 port map (B, bin, y(6));
x9 : or3 port map (y(4), y(5), y(6), Bout);
end onebitFS;
// Dataflow Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FS_dataflow is
Port ( a, b, bin : in std_logic; d, bout : out std_logic);
end FS_dataflow;
architecture FS_dataflow of FS_dataflow is
signal abar, bbar, binbar : std_logic;
begin
abar <= not a;
bbar <= not b;
binbar <= not bin;
d <= ((abar and bbar and bin)or(abar and b and binbar)or(a and bbar and
10

binbar)or(a and b and bin));

bout <= ((abar and bin)or(abar and b)or(b and bin));
end FS_dataflow;

TEST BENCH WAVEFORMS FOR FULL-SUBTRACTOR

Time (n

Bin

100

200

300

400

500

600

700

800

1
1
1

1000

1100

900

Bo

2.6 Post lab Questions

1. What are the signal assignment statements?
2. What are the concurrent statements?
3. Write short notes on following.
i. Process statement
ii. Block statement
4. Write about sequential statements.
5. What is the difference b/w high impedance state of the signal(Z) and unknown state of the
signal(X).
Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification sign.
Answer the pre-lab questions
Complete VHDL code design for all logic gates and output signal waveforms
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the logic gates to
your staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments and its truth table

11

15 points
15 points

1200

Lab 3: Design of Multiplexers and Demultiplexers

3.1 Introduction
The purpose of this experiment is to write and simulate a VHDL program for Multiplexers and
Demultiplexers.

3.2 Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
3.3 Block Diagram

Figure 3.2 Function Table

Figure 3.1 4:1 Multiplexer Block diagram

Figure 3.3 1:4 Demux Symbol

Figure 3.4 Function Table

3.4 Logic Diagram

12

Figure 3.5 4:1 Multiplexer

Figure 3.6 1:4 Demultiplexer Logic

3.4 Pre lab Questions

1. Define mux and demux.
2. Write their applications.
13

3.
4.
5.
6.

What is the relationship b/w input lines and select lines.

Design 4:1 mux and 1:4 demux.
write brief notes on case statement.
Write the difference b/w if and while statement

3.5 VHDL Program

// Multiplexer:
// DATAFLOW DESCRIPTION OF 4 TO 1 MUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity V4to1mux_D is
Port ( S : in std_logic_vector(1 downto 0);
E : in std_logic;
A, B, C, D : in std_logic;
Y : out std_logic);
end V4to1mux_D;
architecture V4to1mux_D of V4to1mux_D is
signal Y1 : std_logic;
begin
with S select Y1 <=
A when "00",
B when "01",
C when "10",
D when "11",
'Z' when others;
Y <= Y1 when E ='0' else 'Z';
end V4to1mux_D;
14

// BEHAVIORAL DESCRIPTION OF 4 TO 1 MUX

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity V4to1mux_B is
Port ( S : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic);
end V4to1mux_B;
architecture V4to1mux_B of V4to1mux_B is
begin
process (S,A,B,C,D)
begin
case s is
when "00" => Y <= A;
when "01" => Y <= B;
when "10" => Y <= C;
when "11" => Y <= D;
when others => Y <= '-';
end case;
end process;
end V4to1mux_B;

// STRUCTURAL DESCRIPTION OF 4 TO 1 MUX

library IEEE;
15

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity V4to1mux_s is
Port ( S : in std_logic_vector(1 downto 0);
A, B, C, D : in std_logic;
Y : out std_logic);
end V4to1mux_s;
architecture V4to1mux_s of V4to1mux_s is
component and3
port (A,B,C : in std_logic;
D

: out std_logic);

end component;
component or4
port (A,B,C,D : in std_logic;
E

: out std_logic);

end component;
signal s1_L, s0_L, x1, x2, x3, x4 : std_logic;
begin
s1_L <= not s(1);
s0_L <= not s(0);
u1 : and3 port map (a, s1_L, s0_L, x1);
u2 : and3 port map (b, s1_L, s(0), x2);
u3 : and3 port map (c, s(1), s0_L, x3);
u4 : and3 port map (d, s(1), s(0) ,x4);
u5 : or4 port map (x1,x2, x3,x4,Y);
16

end V4to1mux_s;

TEST BENCH WAVEFORM FOR MULTIPLEXER

Time (ns)
D[3:0

100

200

300

400

500

600

700

1111

1101

1011

1001

0111

0101

0011

0001

S[1:0

00

01

10

11

00

01

10

11

Enab

800

// Demultiplexer
// BEHAVIORAL DESCRIPTION OF 1 TO 4 DEMUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity V1to4demux_b is
Port ( Din : in std_logic;
E : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(0 to 3));
end V1to4demux_b;
architecture V1to4demux_b of V1to4demux_b is
signal Z : std_logic_vector (0 to 3);
begin
process (Din,E,S)
begin
if Din = '0' then
case S is
when "00" | "01" | "10" | "11" => Z <= "0000";
17

900

1000

1100

1200

when others => Z <="ZZZZ";

end case;
elsif Din = '1' then
case S is
when "00" => Z <= "1000";
when "01" => Z <= "0100";
when "10" => Z <= "0010";
when "11" => Z <= "0001";
when others => Z <="ZZZZ";
end case;
end if;
if E = '1' then Y <= Z;

else Y <= "XXXX";

end process;
end v1to4demux_b;
// STRUCTURAL DESCRIPTION OF 1 TO 4 DEMUX
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity V1to4demux_s is
Port ( Din : in std_logic;
E : in std_logic;
S : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(0 to 3));
end V1to4demux_s;
architecture V1to4demux_s of V1to4demux_s is
18

end if;

component and4
port (A,B,C,D : in std_logic; E : out std_logic);
end component;
signal S1_L, S0_L : std_logic;
begin
S1_L <= not S(1);
S0_L <= not S(0);

u1 : and4 port map(Din, E, S1_L, S0_L, Y(0));

u2 : and4 port map(Din, E, S1_L, S(0), Y(1));
u3 : and4 port map(Din, E, S(1), S0_L, Y(2));
u4 : and4 port map(Din, E, S(1), S(0), Y(3));
end V1to4demux_s;

TEST BENCH WAVEFORMS FOR DEMULTIPLEXER

Time (ns)
Din

S[1:0

00

Y[3:

100

200

300

400

1
01
0000

10
0010

11
0000

500

600

700

800

900

1000

1100

1200

00
1000

01
0000

10
0010

11
0000

00
0000

01
0000

10
0010

11
0000

00
0000

3.6 Post Lab questions

1. Implement the function f(A,B,C)=m(0,1,3,5,7) by using Mux.
2. Write the VHDL code for the above design
3. Write the VHDL code for full subtractor using Demux.

Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements" document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification sign.
Answer the pre-lab questions
Complete VHDL code design for all logic gates and output signal waveforms
Answer the post-lab questions
19

0000

Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the logic gates to
your staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments and its truth table

20

15 points
15 points

Lab 4: Design of Encoders and Decoders

4.1

Introduction

The purpose of this experiment is to introduce you to the basics of Encoders and Decoders. In this
lab, you have to implement Priority Encoder and the Boolean function using Decoders.

4.2

Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.

4.3

Block Diagram

Figure 4.1 4-to-2 bit Encoder

Figure 4.2 2-to-4 Binary Decoders

4.4. Logic Diagram

21

Figure 4.3 4x2 Decoder

Figure 4.4 4x2 Decoder

4.5 Pre lab Questions

1.
2.
3.
4.
5.

What is difference b/w encoder and data selector.

What is the difference b/w decoder and data distributor.
Give the applications of encoder and decoder.
Write short notes on with select statement.
What are the different logic state systems in std_ulogic?

4.6 VHDL Program

// DATAFLOW DESCRIPTION OF 8 TO 3 ENCODER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity oct2bin_D is
22

Port ( D : in std_logic_vector(0 to 7);

E : in std_logic;
Y : out std_logic_vector(2 downto 0));
end oct2bin_D;
architecture oct2bin_D of oct2bin_D is
signal z : std_logic_vector(2 downto 0);
begin
with D select z <=
"000" when "10000000",
"001" when "01000000",
"010" when "00100000",
"011" when "00010000",
"100" when "00001000",
"101" when "00000100",
"110" when "00000010",
"111" when "00000001",
"XXX" when others;
Y <= z when E = '1' else "XXX";
end oct2bin_D;
//BEHAVIORAL DESCRIPTION OF 8 TO 3 ENCODER
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Oct2Bin_b is
23

Port ( D : in std_logic_vector(0 to 7);

E : in std_logic;
Y : out std_logic_vector(2 downto 0));
end Oct2Bin_b;

architecture Oct2Bin_b of Oct2Bin_b is

signal z : std_logic_vector(2 downto 0);
begin
process(D)
begin
case

D is
when "10000000" => z <= "000";
when "01000000" => z <= "001";
when "00100000" => z <= "010";
when "00010000" => z <= "011";
when "00001000" => z <= "100";
when "00000100" => z <= "101";
when "00000010" => z <= "110";
when "00000001" => z <= "111";
when others

=> z <= "XXX";

end case;
if E = '1' then Y <= z; else Y <= "XXX"; end if;
end process;
end Oct2Bin_b;
// STRUCTURAL DESCRIPTION OF 8 TO 3 ENCODER
library IEEE;
24

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity oct2bin_s is
Port ( D : in std_logic_vector(0 to 7);
Y : out std_logic_vector(2 downto 0));
end oct2bin_s;
architecture oct2bin_s of oct2bin_s is

component or4
port(A,B,C,D : in std_logic; E : out std_logic);
end component;
begin
u1 : or4 port map (D(4),D(5),D(6),D(7),Y(2));
u2 : or4 port map (D(2),D(3),D(6),D(7),Y(1));
u3 : or4 port map (D(1),D(3),D(5),D(7),Y(0));
end oct2bin_s;
TEST BENCH WAVEFORMS FOR ENCODER
Time (ns)
in[7:0]
out[2:

100

200

300

400

500

600

700

800

00000001

00000010

00000100

00001000

00010000

00100000

01000000

10000000

10000001

000

001

010

011

100

// STRUCTURAL DESCRIPTION OF 2 TO 4 DECODER

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
25

101

110

111

use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity V2to4dec_S is
Port ( A, B, E : in std_logic;
Y : out std_logic_vector(3 downto 0));
end V2to4dec_S;
architecture V2to4dec_S of V2to4dec_S is
component and3
port (a,b,c : in std_logic; d : out std_logic);
end component;
signal Abar, Bbar : std_logic;

begin
Abar <= not A;
Bbar <= not B;

U1 : and3 port map (Abar, Bbar, E, Y(0));

U2 : and3 port map (Abar, B, E, Y(1));
U3 : and3 port map (A, Bbar, E, Y(2));
U4 : and3 port map (A, B, E, Y(3));
end V2to4dec_S;

TEST BENCH WAVEFORM FOR DECODER

Time (ns)

100

200

300

400

500

600

700

in[1:0

00

01

10

11

00

01

10

11

out[3:

0001

0010

0100

1000

26

0001

0010

0100

800
1000

4.7 Post Lab questions

1. Implement full adder by using suitable decoder.
2. Write the VHDL code for the above design
3. Write the VHDL code for 3 bit Gray to binary code converter.
4. Write short notes on test bench with examples.
Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements"document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification sign.
Answer the pre-lab questions
Complete VHDL code design for all logic gates and output signal waveforms
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the logic gates to
your staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments and its truth table

27

15 points
15 points

Introduction to Sequential Design

Lab 5: Flip Flops
5.1 Introduction
The purpose of this experiment is to introduce you to the basics of flip-flops. In this
lab, you will test the behavior of several flip-flops and you will connect several logic gates
together to create simple sequential circuits.
5.2 Software tools Requirement
Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
5.3 Flip-Flops block diagram and their properties
Flip-flops are synchronous bitable devices. The term synchronous means the output
changes state only when the clock input is triggered. That is, changes in the output occur in
synchronization with the clock. A flip-flop circuit has two outputs, one for the normal value
and one for the complement value of the stored bit. Since memory elements in sequential
circuits are usually flip-flops, it is worth summarizing the behavior of various flip-flop types
before proceeding further. All flip-flops can be divided into four basic types: SR, JK, D and
T. They differ in the number of inputs and in the response invoked by different value of input
signals. The four types of flip-flops are defined in the Table 5.1. Each of these flip-flops can
be uniquely described by its graphical symbol, its characteristic table, its characteristic
equation or excitation table. All flip-flops have output signals Q and Q'.

FlipFlop Flip-Flop Symbol Characteristic Table

Name

28

Characteristic
Equation

Excitation Table

SR

JK

R Q(next)

Q Q(next) S R

K Q(next)

Q Q(next) J K

0 X

1 X

X 1

X 0

Q(next) = S + RQ
SR = 0

Q(next) = JQ + KQ

Q(next)

Q(next) = D

Q(next)

Q(next) = TQ + TQ

Table 5.1 Flip-flops and their properties

5.4 Logic Diagram

Figure 5.1 D- Flip Flop

Figure 5.2 JK Flip Flop

29

0 X

X 0

Q Q(next)

Q Q(next)

Figure 5.3 T Flip Flop

5. 4 Pre-lab Questions
1
2
3
4
5
6
7
8
9

Describe the main difference between a gated S-R latch and an edge-triggered S-R flip-flop.
How does a JK flip-flop differ from an SR flip-flop in its basic operation?
Describe the basic difference between pulse-triggered and edge-triggered flip-flops.
What is use of characteristic and excitation table?
What are synchronous and asynchronous circuits?
How many flip flops due you require storing the data 1101?
What is propagation delays set up time and hold time?
How to generate clock signal in VHDL?
What are the different wait statements?

5.5 VHDL Program

// T Flip Flop
library ieee;
use ieee.std_logic_1164.all;
entity tff is
port(t,clk:in std_logic;
q,qbar:inout std_logic);
end tff;
architecture beh of tff is
begin
process(clk)
begin
if clk'event and clk='1' then
elsif q='1' then
30

q<=not(t);
else
q<=t;
end if;
end process;
qbar<=not(q);
end beh;
// D Flip Flop
library ieee;
use ieee.std_logic_1164.all;
Entity dff is
Port(d,clk :in std_logic; q,qbar :inout std_logic) ;
End dff ;

Architecture beh of dff is

Begin
Process(clk)
Begin
If(clk=1 ) then
q<=d; qbar<=not(t);
end if;
end process;
end beh;

31

// JK Flip Flop
library ieee;
use ieee.std_logic_1164.all;
Entity jkff is
Port(j,k,clk :in std_logic; q,qbar :inout std_logic) ;
End jkff ;

Architecture beh of jkff is

Begin
Process(clk)
Begin
If(clkevent and clk=1 ) then
q<=(j and (not q)) or ((not k) and q);
qbar<=not(q);
end if;
end process;
end beh;

5.6 Post lab

1. Discuss the application of flip-flops in data storage.
2. Draw the logic diagram of Master Slave JK flip-flop.
3. A flip-flop is presently in the RESET state and must go to the SET state on the next clock
pulse. What must J and K be?
4. What do you know about clk and clk event in VHDL?
5. Convert the following.
32

a. JK to T f/f
b. SR to D
6. Write the VHDL code for question no 5.
Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements" document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification for circuit diagram
Answer the pre-lab questions
Complete paper design for all three designs including K-maps and minimized equations and
the truth table for each of the output signals.
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the circuits to your
staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments and its truth table

33

15 points
15 points

Lab 6: Counters and Shift Registers

6.1 Introduction
The purpose of this experiment is to introduce the design of Synchronous Counters. The student
should also be able to design n-bit up/down Counter and shift registers.

6.2 Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
6.3 Logic Diagram

Figure 6.1 Updown Counter

Figure 6.2 Ring Counter

Figure 6.3 SISO Shift Register

34

Figure 6.4 PIPO Shift Register

6.4 PreLab questions

1. How does synchronous counter differ from asynchronous counter?
2. How many flip-flops do you require to design Mod-6 counter.
3. What are the different types of counters?
4. What are the different types of shift registers?
5. How many f/fs are needed for n-bit counter?
6. What is meant by universal shift register.

6.4 VHDL Program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity up_down_counter is
Port ( D : in std_logic_vector(3 downto 0);
load : in std_logic;
enable : in std_logic;
CLK : in std_logic;
mode : in std_logic;
count : out std_logic_vector(3 downto 0));
35

end up_down_counter;
architecture up_down_counter of up_down_counter is
signal z : std_logic_vector(3 downto 0);
begin
process(CLK, enable)
begin
if(CLK='1' and CLK'event) then
if(enable='1') then
if(load='1') then z <= D;
else
if(mode='0') then z <= signed(z)+'1';
elsif(mode='1') then z <= signed(z)-'1';
end if;
end if;
else z <= "0000";
end if;
end if;
end process;
count <= z;
end up_down_counter;
TEST BENCH WAVEFORMS FOR UP-DOWN COUNTERS
Time (ns)
CLK

Data_in[3

up_down

reset

count_en

load
count[3:0]

100

200

300

400

500

600

700

800

900

10

1
0
// Ring Counter
0
1

1
0
2

0
4

36

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ring_counter is
Port ( CLK : in std_logic;
reset : in std_logic;
enable : in std_logic;
count : out std_logic_vector(7 downto 0));
end ring_counter;
architecture ring_counter of ring_counter is
signal z : std_logic_vector(7 downto 0);
begin
process(reset, CLK)
begin
if(CLK='1' and CLK'event) then
if (reset='1')

then z <= "00000001";

else
if(enable='1') then z <= z(6 downto 0) & z(7);
end if;
end if;
end if;
end process;
count <= z;

end ring_counter;
37

TEST BENCH WAVEFORM FOR RING COUNTER

Time (ns)
CLK

Reset

Enable

Count[7:

100

200

300

400

500

6
7

0
00000001

00000010

00000100

// Shift Register
library ieee;
use ieee.std_logic_1164.all;

entity dff is
port(d,clk:in bit;
pre,clr:in bit;
q,qb:buffer bit);
end dff;

architecture dff_bhv of dff is

begin
process(clk,pre,clr)
begin
if(pre='0') then
q<='1'; qb<='0';
elsif(clr='0')then
q<='0'; qb<='1';
elsif clk='0' and clk'event then
q <= d; qb<=not q;
38

00001000

00010000

00100000

end if;
end process;
end dff_bhv;
// SISO
library ieee;
use ieee.std_logic_1164.all;

entity siso is
port(d:in bit_vector(3 downto 0);
din:in bit;
clk,pre,clr:in bit;
q,qb:buffer bit_vector(3 downto 0));
end siso;

architecture siso_str of siso is

component dff
port(d,clk:in bit;
pre,clr:in bit;
q,qb:buffer bit);
end component;
begin
f1:dff port map(din,clk,pre,clr,q(0),open);
f2:dff port map(q(0),clk,pre,clr,q(1),open);
f3:dff port map(q(1),clk,pre,clr,q(2),open);
f4:dff port map(q(2),clk,pre,clr,q(3),open);
end siso_str;
39

// PIPO
library ieee;
use ieee.std_logic_1164.all;
entity pipo is
port(d:in bit_vector(3 downto 0);
--din:in bit;
clk,pre,clr:in bit;
q,qb:buffer bit_vector(3 downto 0));
end pipo;
architecture pipo_str of pipo is
component dff
port(d,clk:in bit;
pre,clr:in bit;
q,qb:buffer bit);
end component;
begin
f1:dff port map(d(0),clk,pre,clr,q(0),open);
f2:dff port map(d(1),clk,pre,clr,q(1),open);
f3:dff port map(d(2),clk,pre,clr,q(2),open);
f4:dff port map(d(3),clk,pre,clr,q(3),open);
end pipo_str;
// SERIAL-IN SERIAL-OUT SHIFT REGISTER USING GENERATE AND GENERIC
STATEMENTS
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
40

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity shift_reg is
generic (length : integer :=4);
Port ( Din, CLK : in std_logic;
Dout : out std_logic);
end shift_reg;

architecture shift_reg of shift_reg is

component DFF
port(D,CLK : in std_logic; Q,QN : out std_logic);
end component;

signal y : std_logic_vector(4 downto 0);

begin

y(0) <= Din;

g1 : for i in 0 to (length-1) generate
d1 : DFF port map(y(i), clk, y(i+1));
end generate;
Dout <= Y(length);
end shift_reg;
// Universal shift registers
// BEHAVIORAL DESCRIPTION OF 4-BIT SHIFTER : METHOD-2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
41

use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity shifter2 is
Port ( data : in std_logic_vector(3 downto 0);
load, enable, clock : in std_logic;
mode : in std_logic_vector(1 downto 0);
Y : out std_logic_vector(3 downto 0));
end shifter2;
architecture shifter2 of shifter2 is
signal z : std_logic_vector(3 downto 0);
begin
process (clock)
begin
if(clock='1' and clock'event) then
if(load='0') then z <= data;
else
case mode is
when "00" => z <= z(2 downto 0) & '0';
when "01" => z <= '0' & z(3 downto 1) ;
when "10" => z <= z(0) & z(3 downto 1) ;
when "11" => z <= z(2 downto 0) & z(3);
when others => z <= "0000";
end case;
end if;
end if;
end process;
Y <= z when enable='0' else "0000";
end shifter2;

6.5 PostLab questions

1.Write the use of enable and reset signal.
2.What is the function of generic statement?
3.Design mod-6 counter using d flf and write the VHDL code.
Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirementsdocument available on the class web page. Be sure to include the following
items in your lab report:
42

Lab cover sheet with staff verification for circuit diagram

Answer the pre-lab questions
Complete paper design for all three designs including K-maps and minimized equations and
the truth table for each of the output signals.
Answer the post-lab questions

Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the circuits to your
staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments and its truth table

15 points
15 points

Lab 7: Design of Multiplier Architectures

7.1 Introduction
The purpose of this experiment is to design different types of multiplier architectures. The student
should also be able to design different types of n-bit multiplier architectures.

7.2 Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
7.3 Multiplier Architecture

43

Figure 7.1 Array multiplier

Figure 7.2 Braun multiplier

7.4 Pre lab questions

1. Write the applications of multiplier.
44

2.
3.
4.
5.

What is the use of work.data_type package?

What is meant by subtype? How to declare it?
What is the use of generate statement?
Write any 4 types of multiplier.

7.5 VHDL Program

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity systolic_array is
Port ( A, B : in std_logic_vector(3 downto 0);
P : out std_logic_vector(7 downto 0));
end systolic_array;

architecture systolic_array of systolic_array is

signal c0, c1, c2, c3, s0, s1, s2, s3 : std_logic_vector(3 downto 0);
component basic_cell
port(A,B,Sin,Cin : in std_logic; Sout,Cout : out std_logic);
end component;
begin
B1 : basic_cell port map(A(0),B(0),'0','0', P(0), c0(0));
B2 : basic_cell port map(A(1),B(0),'0',c0(0),s0(1),c0(1));
B3 : basic_cell port map(A(2),B(0),'0',c0(1),s0(2),c0(2));
B4 : basic_cell port map(A(3),B(0),'0',c0(2),s0(3),c0(3));

B5 : basic_cell port map(A(0),B(1),s0(1),'0', P(1), c1(0));

B6 : basic_cell port map(A(1),B(1),s0(2),c1(0),s1(1),c1(1));
45

B7 : basic_cell port map(A(2),B(1),s0(3),c1(1),s1(2),c1(2));

B8 : basic_cell port map(A(3),B(1),'0', c1(2),s1(3),c1(3));
B9 : basic_cell port map(A(0),B(2),s1(1),'0', P(2), c2(0));
B10 : basic_cell port map(A(1),B(2),s1(2),c2(0),s2(1),c2(1));
B11 : basic_cell port map(A(2),B(2),s1(3),c2(1),s2(2),c2(2));
B12 : basic_cell port map(A(3),B(2),'0', c2(2),s2(3),c2(3));

B13 : basic_cell port map(A(0),B(3),s2(1),'0', P(3),c3(0));

B14 : basic_cell port map(A(1),B(3),s2(2),c3(0),P(4),c3(1));
B15 : basic_cell port map(A(2),B(3),s2(3),c3(1),P(5),c3(2));
B16 : basic_cell port map(A(3),B(3),'0', c3(2),P(6),P(7));
end systolic_array;

TEST BENCH WAVEFORM FOR SYSTOLIC ARRAY MULTIPLIER

Time (ns)
A[3:0

100

200

300

400

500

600

700

800

900

1000

1100

1200

B[3:0

P[7:0

00

01

04

09

10

19

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity braun_array is
Port ( A, B : in std_logic_vector(3 downto 0);
P : out std_logic_vector(7 downto 0));
end braun_array;
46

24

31

40

51

64

59

90

architecture braun_array of braun_array is

signal K : std_logic_vector(15 downto 0);
signal S,C : std_logic_vector(11 downto 0);
component and2
port(A,B : in std_logic; C : out std_logic);
end component;

component FA_dataflow
port(A,B,Cin : std_logic; SUM,Cout : out std_logic);
end component;
begin
G0 : and2 port map(A(0), B(0), K(0));
G1 : and2 port map(A(1), B(0), K(1));
G2 : and2 port map(A(2), B(0), K(2));
G3 : and2 port map(A(3), B(0), K(3));
G4 : and2 port map(A(0), B(1), K(4));
G5 : and2 port map(A(1), B(1), K(5));
G6 : and2 port map(A(2), B(1), K(6));
G7 : and2 port map(A(3), B(1), K(7));
G8 : and2 port map(A(0), B(2), K(8));
G9 : and2 port map(A(1), B(2), K(9));
G10 : and2 port map(A(2), B(2), K(10));
G11 : and2 port map(A(3), B(2), K(11));
G12 : and2 port map(A(0), B(3), K(12));
G13 : and2 port map(A(1), B(3), K(13));
47

G14 : and2 port map(A(2), B(3), K(14));

G15 : and2 port map(A(3), B(3), K(15));
FA0 : FA_dataflow port map(K(1), K(4), '0', S(0), C(0));
FA1 : FA_dataflow port map(K(2), K(5), '0', S(1), C(1));
FA2 : FA_dataflow port map(K(3), K(6), '0', S(2), C(2));
FA3 : FA_dataflow port map(S(1), K(8), C(0), S(3), C(3));
FA4 : FA_dataflow port map(S(2), K(9), C(1), S(4), C(4));
FA5 : FA_dataflow port map(K(7), K(10), C(2), S(5), C(5));
FA6 : FA_dataflow port map(S(4), K(12), C(3), S(6), C(6));
FA7 : FA_dataflow port map(S(5), K(13), C(4), S(7), C(7));
FA8 : FA_dataflow port map(K(11), K(14), C(5), S(8), C(8));
FA9 : FA_dataflow port map(S(7), '0',

C(6), S(9), C(9));

FA10 : FA_dataflow port map(S(8), C(9), C(7), S(10), C(10));

FA11 : FA_dataflow port map(K(15), C(10), C(8), S(11), C(11));
P(0) <= K(0); P(1) <= S(0); P(2) <= S(3); P(3) <= S(6);
P(4) <= S(9); P(5) <= S(10); P(6) <= S(11); P(7) <= C(11);
end braun_array;
TEST BENCH WAVEFORM FOR 4-BIT BRAUN ARRAY MULTIPLIER

Time (ns)
A[3:0

100

200

300

400

500

600

700

800

900

1000

1100

1200

B[3:0

P[7:0

00

01

04

09

10

19

24

31

40

51

64

7.6 Postlab:
1. How to design 32bitX32bit multiplier from 8 bit multiplier.
2. Write the VHDL code for the above design.
3. How to perform multiplication for negative numbers?
4. Draw the architecture of 4-BIT Bough-Wooly Multiplier.
Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
48

79

90

Report Requirements" document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification for circuit diagram
Answer the pre-lab questions
Complete paper design for all three designs including K-maps and minimized equations and
the truth table for each of the output signals.
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the circuits to your
staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments and its truth table

15 points
15 points

Lab 8: Design of Arithmetic Logic Unit(ALU)

8.1 Introduction
The purpose of this experiment is to design an Arithmetic Logic Design (ALU). The student should
also be able to design an ALU with additional features.

8.2 Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
8.3.Block Diagram

49

Figure 8.1. Arithmetic Logic Unit (ALU)

8.4 Pre lab questions

1. What is ALU?
2. What are the operations can be done by using ALU?
3. What are the predefined Attributes?
8.5 VHDL Program
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity alu is
Port ( A, B : in std_logic_vector(7 downto 0);
sel : in std_logic_vector(4 downto 0);
F : out std_logic_vector(7 downto 0));
50

end alu;
architecture alu of alu is
begin
process(sel,A,B)
begin
case conv_integer(sel) is

--

when 0 =>

F <=A;

when 1 =>

F <=A+"00000001";

when 2 =>

F <=B;

when 3 =>

F <=B+"00000001";

when 4 =>

F <=A-"00000001";

when 5 =>

F <=B-"00000001";

when 6 =>

F <=A+B;

when 7 =>

F <=A+B+"00000001";

when 8 =>

F <=A-B;

when 9 =>

F <=A-B-"00000001";

when 10 =>

F <=signed(A) * signed(B);

when 11 =>

F <="XXXXXXXX";

when 12 =>

F <=A or B;

when 13 =>

F <=A nor B;

when 14 =>

F <=A and B;

when 15 =>

F <=A nand B;

when 16 =>

F <=A xor B;

when 17 =>

F <=A xnor B;

when 18 =>

F <=not A;

when 19 =>

F <=not B;
51

when 20 =>

F <="XXXXXXXX";

when 21 =>

F <="XXXXXXXX";

when 22 =>

F <='0'&A(7 downto 1);

when 23 =>

F <=A(7)&A(7 downto 1);

when 24 =>

F <='0'&B(7 downto 1);

when 25 =>

F <=B(7)&B(7 downto 1);

when 26 =>

F <=A(6 downto 0)&'0';

when 27 =>

F <=A(6 downto 0)&'0';

when 28 =>

F <=B(6 downto 0)&'0';

when 29 =>

F <=B(6 downto 0)&'0';

when others => F <= "00000000";

end case;
end process;
end alu;
TEST BENCH WAVEFORM FOR ALU
Time (ns)

100

200

300

400

500

600

700

800

900

1000

1100

1200

A[7:0]

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

B[7:0]

F0

D0

B0

90

70

50

30

10

E0

C0

A0

80

60

select[4:0]

00

02

04

06

08

0A

0C

0E

10

12

14

16

18

F[15:0]

0000

00D0

001F

00C0

FFD0

1900

0070

0010

0060

FF6F

0000

0058

00

ALU_zero_

Time (ns)

100

200

300

400

500

600

700

800

900

1000

1100

1200

A[7:0]

00

10

20

30

40

50

60

70

80

90

A0

B0

C0

B[7:0]

F0

D0

B0

90

70

50

30

10

E0

C0

A0

80

60

select[4:0]

01

03

05

07

09

0B

0D

0F

11

13

15

17

19

F[15:0]
ALU_zero_

0001

8.6 Post lab

0

00D1

00AF

00C1

FFCF

0001

FF8F

FFEF

FF9F

FF3F

0000

0058

003

1. What is the use of conv statement?

2. How to perform rotate operation in ALU?
3. Write the difference b/w rotate and shift operation.
4. Design an ALU to perform floating point addition.
52

5. Write the VHDL coding for Barrel Shifter.

Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements" document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification for circuit diagram
Answer the pre-lab questions
Complete paper design for all three designs including K-maps and minimized equations and
the truth table for each of the output signals.
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the circuits to your
staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments and its truth table

15 points
15 points

Lab 9: Design of Random Access Memory (RAM) and First

In First Out (FIFO)
9.1 Introduction
The purpose of this experiment is to design Random Access Memory (RAM) and First in First out
(FIFO). The student should also be able to design other kinds of memory and stacks with additional
features.

9.2 Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
9.3.Block Diagram

53

Figure 9.1 Random Access Memory

9.4. Pre lab questions

1.
2.
3.
4.
5.

What is memory and what are its types?

Write the use of RAM and ROM.
What is STACK?
What is QUEUE?
Write down the uses of Type statement.

9.5 VHDL Program

// RANDOM ACCESS MEMORY
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity ram_sp_ar_sw is
generic (
DATA_WIDTH :integer := 8;
54

ADDR_WIDTH :integer := 8
);
port (
clk

:in std_logic;

-- Clock Input

address :in std_logic_vector (ADDR_WIDTH-1 downto 0); -- address Input

data :inout std_logic_vector (DATA_WIDTH-1 downto 0); -- data bi-directional
cs

:in std_logic;

-- Chip Select

we

:in std_logic;

-- Write Enable/Read Enable

oe

:in std_logic

-- Output Enable

);
end entity;
architecture rtl of ram_sp_ar_sw is
----------------Internal variables---------------constant RAM_DEPTH :integer := 2**ADDR_WIDTH;
signal data_out :std_logic_vector (DATA_WIDTH-1 downto 0);
type RAM is array (integer range <>)of std_logic_vector (DATA_WIDTH-1 downto 0);
signal mem : RAM (0 to RAM_DEPTH-1);
begin
----------------Code Starts Here------------------- Tri-State Buffer control
-- output : When we = 0, oe = 1, cs = 1
data <= data_out when (cs = '1' and oe = '1' and we = '0') else (others=>'Z');
-- Memory Write Block
-- Write Operation : When we = 1, cs = 1
MEM_WRITE:
process (clk) begin
55

if (rising_edge(clk)) then
if (cs = '1' and we = '1') then
mem(conv_integer(address)) <= data;
end if;
end if;
end process;
-- Memory Read Block
-- Read Operation : When we = 0, oe = 1, cs = 1
MEM_READ:
process (clk) begin
if (rising_edge(clk)) then
if (cs = '1' and we = '0' and oe = '1') then
data_out <= mem(conv_integer(address));
end if;
end if;
end process;

end architecture;
TEST BENCH WAVEFORM FOR RAM

9.6 Post lab questions

1. Write the VHDL code for LIFO.
56

2. How to synchronize host FIFO and target FIFO.

Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirements" document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification for circuit diagram
Answer the pre-lab questions
Complete paper design for all three designs including K-maps and minimized equations and
the truth table for each of the output signals.
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the circuits to your
staff in-charge.
The lab report will be graded as follows (for the 30 points):
VHDL code for each experiments
Output signal waveform for all experiments

15 points
15 points

Lab 10: Control Logic Design

10.1 Introduction
The purpose of this experiment is to simulate for the given state transition diagram of a
Moore and Mealy finite state machines.

10.2

Software tools Requirement

Equipments:
Computer with Modelsim Software
Specifications:
HP Computer P4 Processor 2.8 GHz, 2GB RAM, 160 GB Hard Disk
Softwares: Modelsim - 5.7c, Xilinx - 6.1i.
10.3

State Diagram

57

Figure 10.1 Moore Machine

Next state and output

Present State
Figure 10.2 Mealy Machine

10.4
1
2
3

10.5

Pre lab Questions

How the clocked sequential circuits can be analyzed?
What is the difference b/w moore and mealy state machines.
What is the use of state reduction technique.

VHDL Program

--Modeling a Moore FSM

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Moore_Fsm is
port(A, CLOCK:in bit; Z:out std_logic);
end Moore_Fsm;

architecture Fsm_Example of Moore_Fsm is

type State_Type is (ST0, ST1, ST2, ST3);
signal Moore_State:State_Type;
begin

58

process(CLOCK)
begin
if CLOCK=0 then
case Moore_State is
when ST0=>
Z<=1;
if A=1
then Moore_State<=ST2;
end if;
when ST1=>
Z<=0;
if A=1 then
Moore_State<=ST3;
end if;
when ST2=>
Z<=0;
if A=0 then
Moore_State<=ST1;
else
Moore_State<=ST3;
end if;
when ST3=>
Z<=1;
if A=1 then
Moore_State<=ST0;
end if;
59

end case;
end if;
end process;
end Fsm_Example;

--Modeling a Mealy FSM

library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Mealy_Fsm is
port(A, CLOCK:in bit; Z:out std_logic);
end Mealy_Fsm;

architecture Fsm_Example of Mealy_Fsm is

type Mealy_Type is (ST0, ST1, ST2, ST3);
signal P_State, N_State:Mealy_Type;
begin
Seq_part:process(CLOCK)
begin
-- Synchronous Section
if CLOCK=0 then
P_State<=N_State;
end if;
end process Seq_part;
COMB_PART:process(P_State, A)
begin
60

case P_State is
when ST0=>
if A=1 then
Z<=1;
N_State<=ST3;
else
Z<=0;
end if;
when ST1=>
if A=1 then
Z<=0;
N_State<=ST0;
else
Z<=1;
end if;
when ST2=>
if A=0 then
Z<=0;
else
Z<=1;
N_State<=ST1;
end if;
when ST3=>
Z<=0;
if A=0 then
N_State<=ST2;
61

else
N_State<=ST1;
end if;
end case;
end if;
end process COMB_PART;
end Fsm_Example;

10.6 Post-lab Questions

1. Differentiate ASM and FSM.
2. Design a mealy type sequence detector to detect serial input sequence of 101 using VHDL.
3. Design a moore type sequence detector to detect serial input sequence of 101 VHDL.
Lab Report
Each individual will be required to submit a lab report. Use the format specified in the "Lab
Report Requirement document available on the class web page. Be sure to include the following
items in your lab report:
Lab cover sheet with staff verification sign.
Answer the pre-lab questions
Complete VHDL code design for all logic gates and output signal waveforms
Answer the post-lab questions
Grading
Pre-lab Work
Lab Performance
Post-lab Work
Lab report

20 points
30 points
20 points
30 points

For the lab performance - at a minimum, demonstrate the operation of all the logic gates to
your staff in-charge
The lab report will be graded as follows (for the 30 points):
VHDL code for each state machine
Output signal waveform for both design

62

15 points
15 points