Objective Question Bank: FinFET, Gate-All-Around

(GAA) FETs, and Nanosheet Transistors

Wafer Bonding and 3D Stacking
Dr. Md Jawaid Alam
June 10, 2025

Instructions
Each question is multiple choice with one correct answer. Difficulty levels are indicated
as:
A = Average, AA = Above Average, T = Tough

Questions: FinFET, GAA, and Nanosheet Transistors

Q1. (A) What is the primary advantage of FinFETs over traditional planar MOSFETs?

(a) Lower cost

(b) Better gate control
(c) Larger size
(d) Higher leakage current

Answer: (b)
Explanation: FinFETs have a 3D structure that provides better gate control over
the channel, reducing short-channel effects.

Q2. (A) In a FinFET, what does the ”fin” represent?

(a) Gate oxide

(b) Source contact
(c) Vertical silicon channel
(d) Metal interconnect

Answer: (c)
Explanation: The ”fin” is a vertical silicon channel that is wrapped around by the
gate to improve control.

Q3. (A) What short-channel effect is most effectively mitigated by FinFETs?

(a) Gate-induced drain leakage

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 (b) Subthreshold leakage
(c) Avalanche breakdown
(d) Punch-through

Answer: (d)
Explanation: FinFETs reduce punch-through by better electrostatic control using
the multi-gate structure.

Q4. (A) FinFET is an example of which type of transistor architecture?

(a) Single-gate planar

(b) Double-gate
(c) Surrounding gate
(d) None of the above

Answer: (b)
Explanation: FinFETs typically have gates on both sides of the fin, making them
double-gate devices.

Q5. (A) In GAA FETs, the gate surrounds the channel:

(a) On one side

(b) On two sides
(c) On three sides
(d) On all sides

Answer: (d)
Explanation: Gate-All-Around FETs completely surround the channel, offering su-
perior control over it.

Q6. (A) Which material is commonly used as the channel in nanosheet transistors?

(a) Silicon
(b) Germanium
(c) Gallium Arsenide
(d) Indium Phosphide

Answer: (a)
Explanation: Silicon is the most commonly used channel material due to its well-
established processing and performance.

Q7. (A) What is the main reason for shifting to GAA FETs at advanced nodes (e.g.,
3nm)?

(a) Higher thermal conductivity

(b) Better electrostatic control
(c) Simpler fabrication

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 (d) Larger form factor

Answer: (b)
Explanation: GAA FETs offer superior gate control, which is critical at extremely
scaled nodes.

Q8. (A) In nanosheet FETs, what defines the width of the channel?

(a) Gate length

(b) Sheet thickness
(c) Sheet width
(d) Spacer thickness

Answer: (c)
Explanation: The channel width is determined by the width of the individual
nanosheets.

Q9. (AA) What limits the scalability of FinFETs below 5nm?

(a) Fin height

(b) Gate length
(c) Gate-to-fin alignment precision
(d) Parasitic resistance

Answer: (c)
Explanation: At extremely small nodes, precise alignment becomes increasingly
difficult and limits scaling.

Q10. (AA) Which company first introduced GAA nanosheet transistors in commercial
chips?

(a) Intel
(b) AMD
(c) TSMC
(d) Samsung

Answer: (d)
Explanation: Samsung was the first to introduce GAA nanosheet FETs in mass
production around 3nm node.

Q11. (AA) In GAA FETs, increasing the number of stacked nanosheets primarily im-
proves:

(a) Leakage current

(b) Drive current
(c) Thermal conductivity
(d) Substrate biasing

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 Answer: (b)
Explanation: More stacked nanosheets increase the effective channel width, thus
improving drive current.

Q12. (AA) One fabrication challenge in nanosheet transistors is:

(a) Doping the channel uniformly

(b) Forming high-k dielectric
(c) Removing the sacrificial layers selectively
(d) Etching the contact poly pitch

Answer: (c)
Explanation: Selectively etching away sacrificial layers without damaging nanosheets
is a key challenge.

Q13. (AA) What type of carrier mobility enhancement is seen in nanosheet transistors?

(a) Ballistic transport

(b) Strain engineering
(c) Gate underlap
(d) Punch-through suppression

Answer: (b)
Explanation: Strain is engineered into the nanosheets to enhance carrier mobility.

Q14. (AA) GAA FETs can be considered an evolution of:

(a) Planar MOSFETs

(b) SOI MOSFETs
(c) FinFETs
(d) Tunnel FETs

Answer: (c)
Explanation: GAA is a natural extension of FinFETs with better gate control by
wrapping the gate entirely.

Q15. (AA) The nanosheet channel is typically formed by:

(a) Direct printing

(b) Atomic Layer Deposition
(c) Epitaxial growth and selective etching
(d) CMP planarization

Answer: (c)
Explanation: Epitaxial growth followed by selective etching is used to form stacked
nanosheets.

Q16. (T) The subthreshold slope in GAA nanosheet FETs is ideally closer to:

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 (a) 100 mV/dec
(b) 70 mV/dec
(c) 60 mV/dec
(d) 40 mV/dec

Answer: (c)
Explanation: Ideal subthreshold slope is 60 mV/dec at room temperature, which
GAA FETs closely approach.

Q17. (T) Which simulation method is most suitable for quantum transport modeling in
nanosheet FETs?

(a) Drift-diffusion
(b) Monte Carlo
(c) Non-equilibrium Green’s Function (NEGF)
(d) Finite Element Method (FEM)

Answer: (c)
Explanation: NEGF captures quantum effects accurately, which dominate at nanoscale
dimensions.

Q18. (T) What challenge arises due to narrow spacing between nanosheets?

(a) Increased threshold voltage

(b) Parasitic capacitance and gate-to-gate coupling
(c) Gate resistance
(d) Gate-induced drain leakage

Answer: (b)
Explanation: Tight spacing increases coupling and parasitic capacitance, degrading
performance.

Q19. (T) In GAA nanosheet FETs, what factor most directly affects electrostatic in-
tegrity?

(a) Sheet thickness

(b) Sheet width
(c) Gate dielectric constant
(d) Channel doping

Answer: (a)
Explanation: Thinner sheets allow the gate to better control the entire channel,
enhancing integrity.

Q20. (T) Which of the following best describes the trend in contact resistance as tran-
sistor dimensions shrink in nanosheet technology?

(a) It decreases due to better metals

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 (b) It remains constant
(c) It increases due to limited contact area
(d) It is unaffected by scaling

Answer: (c)
Explanation: As size shrinks, contact area reduces, causing higher resistance despite
material improvements.

Questions: Wafer Bonding and 3D Stacking

Q21. Which of the following is a key advantage of 3D IC integration?
A. Increased surface area
B. Improved planar scalability
C. Reduced interconnect length (Correct)
D. Higher yield
Explanation: 3D ICs significantly reduce interconnect length due to vertical stack-
ing, improving speed and reducing power.

Q22. What does TSV stand for in the context of 3D integration?

A. Transistor Signal Vector
B. Through-Silicon Via (Correct)
C. Thermal Silicon Vector
D. Transfer Substrate Via
Explanation: TSVs are vertical electrical connections passing through silicon
wafers to connect different layers in 3D ICs.

Q23. Which type of bonding provides the highest alignment accuracy?

A. Wafer-to-wafer bonding
B. Die-to-wafer bonding (Correct)
C. Fusion bonding
D. Thermocompression bonding
Explanation: Die-to-wafer bonding allows placement of known-good dies and
achieves better alignment and yield.

Q24. Which bonding method is best suited for low-temperature processes?

A. Fusion bonding
B. Hybrid bonding (Correct)
C. Thermocompression bonding
D. Anodic bonding
Explanation: Hybrid bonding can be performed at lower temperatures compared
to fusion or thermocompression methods.

Q25. A disadvantage of wafer-to-wafer bonding is:

A. High throughput
B. Difficult to align large dies (Correct)
C. High accuracy alignment
D. Ease of testing individual dies

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 Explanation: Misalignment and low yield due to bonding of entire wafers with
some defective dies is a key drawback.

Q26. Which of the following is NOT typically associated with hybrid bonding?
A. Copper interconnects
B. Direct oxide-oxide contact
C. High-temperature annealing (Correct)
D. Dielectric planarization
Explanation: Hybrid bonding works at relatively lower temperatures, reducing
thermal stress and mismatch.

Q27. In TSV fabrication, what is the typical order of process steps?

A. Bonding, Liner Deposition, Etch, Fill
B. Etch, Liner Deposition, Fill (Correct)
C. Liner Deposition, Etch, Fill
D. Etch, Fill, Liner Deposition
Explanation: First, vias are etched, then lined with dielectric or barrier, followed
by metal fill.

Q28. Which material is commonly used to fill TSVs?

A. Aluminum
B. Polysilicon
C. Copper (Correct)
D. Tungsten
Explanation: Copper is preferred due to its high conductivity and compatibility
with damascene processes.

Q29. Which of the following is a major challenge in 3D stacking?

A. Lithography scaling
B. Thermal management (Correct)
C. Device variability
D. Gate leakage
Explanation: Stacked dies increase power density, making heat removal and dis-
sipation difficult.

Q30. What is an advantage of die-to-wafer over wafer-to-wafer bonding?

A. Faster bonding speed
B. Higher yield (Correct)
C. Better chemical compatibility
D. Larger die size
Explanation: Known-good dies are used in die-to-wafer, improving yield and
reducing cost.

Q31. In hybrid bonding, the metal pads are typically made of:
A. Aluminum
B. Nickel
C. Copper (Correct)
D. Gold

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 Explanation: Copper pads allow for both electrical and mechanical connection in
hybrid bonding.

Q32. Which bonding technique is generally used in MEMS packaging?

A. Thermocompression bonding (Correct)
B. Hybrid bonding
C. Wafer fusion
D. Electrostatic bonding
Explanation: Thermocompression bonding is widely used in MEMS for robust
mechanical joins.

Q33. Which of the following improves the electrical performance of 3D ICs?

A. Long global wires
B. High-k dielectric
C. Reduced via resistance (Correct)
D. Wide pitch interconnects
Explanation: Lower via resistance improves speed and reduces power loss in 3D
ICs.

Q34. Which is a direct bonding technique?

A. Thermocompression
B. Adhesive bonding
C. Fusion bonding (Correct)
D. Metal eutectic bonding
Explanation: Fusion bonding creates a direct chemical bond between oxide sur-
faces.

Q35. What is the typical TSV diameter in advanced 3D ICs?

A. 50–100 µm
B. 10–50 µm (Correct)
C. 100–200 µm
D. >200 µm
Explanation: TSVs for logic and memory stacking typically fall in the 10–50 µm
range.

Q36. Which of the following limits wafer-to-wafer bonding yield?

A. Bonding speed
B. Die yield variation (Correct)
C. Wafer size
D. Die thickness
Explanation: A single defective die on a wafer reduces the effective yield in wafer-
to-wafer schemes.

Q37. Anodic bonding typically requires:

A. Copper and glass
B. Silicon and glass (Correct)
C. Silicon and copper
D. Glass and aluminum

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 Explanation: Anodic bonding is performed between silicon and alkali-containing
glass at elevated temperatures.

Q38. Which factor is most critical in hybrid bonding alignment?

A. Wafer thickness
B. Dielectric constant
C. Overlay accuracy (Correct)
D. TSV depth
Explanation: Precise overlay ensures electrical contact and reliable bonding in
hybrid schemes.

Q39. Which bonding is commonly used in temporary wafer handling?

A. Thermocompression bonding
B. Adhesive bonding (Correct)
C. Anodic bonding
D. Direct fusion bonding
Explanation: Temporary wafer bonding using adhesives allows thinning and pro-
cessing of device wafers.

Q40. Why is low-temperature bonding important in 3D IC fabrication?

A. Faster bonding time
B. Protects BEOL layers (Correct)
C. Allows larger wafers
D. Improves copper diffusion
Explanation: Lower temperatures minimize damage to interconnects and previ-
ously fabricated layers.