EXPERIMENT 1

Aim: Write down VHDL program for half adder and full adder.

Apparatus: Xilinx ISE 14.7

System Description:

In electronics, an adder or summer is a digital circuit that performs addition of binary numbers.
In many computers and other kinds of processors, adders are used not only in the arithmetic logic
unit(s), but also in other parts of the processor, where they are used to calculate addresses, table
indices, and similar operations.

Half Adder: Half adder is a combinational arithmetic circuit that adds two numbers and
produces a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit
(S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From this it is
clear that a half adder circuit can be easily constructed using one X-OR gate and one AND gate.
Half adder is the simplest of all adder circuit, but it has a major disadvantage. The half adder can
add only two input bits (A and B) and has nothing to do with the carry if there is any in the input.
So if the input to a half adder have a carry, then it will be neglected it and adds only the A and B
bits. That means the binary addition process is not complete and that’s why it is called a half
adder.

Full Adder: Full adder is a conditional circuit which performs full binary addition that means it
adds two bits and a carry and outputs a sum bit and a carry bit. Any bit of augend can either be 1
or 0 and we can represent with variable A, similarly any bit of addend we represent with variable
B. The carry after addition of same significant bit of augend and addend can represent by C.

Logic Diagram:

Figure 1.1 Half Adder Circuit Diagram Figure 1.2 Full Adder Circuit Diagram
 Truth Table

Inputs Outputs
A B Cin Cout S
0 0 0 0 0
1 0 0 0 1
0 1 0 0 1
1 1 0 1 0
0 0 1 0 1
1 0 1 1 0
0 1 1 1 0
1 1 1 1 1

SCHEMATIC:

Figure 1.3

Half Adder RTL Schematic

 Figure 1.3 Full Adder RTL Schematic

VHDL CODE FOR HALF ADDER

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity halfadder1 is

Port ( a,b : in STD_LOGIC;

e : in STD_LOGIC;

sum,cout : out STD_LOGIC);

end halfadder1;

architecture Behavioral of halfadder1 is

begin
process(a,b,e)

begin

sum <= e and (a xor b);

cout<= e and (a and b);

end process ;

end Behavioral;

VHDL CODE FOR FULL ADDER

entityfulladderbehavioural is

Port ( a,b,c : in STD_LOGIC;

e : in STD_LOGIC;

sum,carry : out STD_LOGIC);

endfulladderbehavioural;

architecture Behavioral of fulladderbehavioural is

begin

process(a,b,c,e)

begin

sum<= e and (a xor b xor c);

carry<= e and (((a xor b)and c) or (a and b));

end process ;

end Behavioral;

OUTPUT
:

Figure 1.4 Half Adder output

Figure 1.5 Full Adder Output

 EXPERIMENT 2

Aim: Write down VHDL program for 4 to 1 Multiplexer.

Apparatus: Xilinx ISE 14.7

System Description:

A digital MUX is a combinational circuit that selects one input out of several inputs and directs it
to a single output. The particular input section is controlled by a set of select inputs.

Logic Diagram:

Figure 2.1 4 : 1 Multiplexer Circuit Diagram

Table 2.1 4:1 Multiplexer Truth Table

Truth Table

Select Output
Input’s
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
SCHEMATIC:

Figure 2.2

4 :1 Multiplexer RTL Schematic

VHDL CODE

entity mux41 is

Port ( x : in STD_LOGIC_VECTOR(3 downto 0);

s : in STD_LOGIC_VECTOR(1 downto 0);

e : in STD_LOGIC;

y : out STD_LOGIC);

end mux41;

architecture Behavioral of mux41 is

begin

process(x,e)

begin

if(e = '1') then

if(s(0) ='0' and s(1)='0')then

y <= x(0);

elsif(s(0) ='0' and s(1)='1')then

y <= x(1);

elsif(s(0) ='1' and s(1)='1')then

y <= x(2);

elsif(s(0) ='1' and s(1)='0')then

y <= x(3);

end if;

else

y <= 'X';

end if;

end process;

end Behavioral;

OUTPUT

Figure 2.3

4 : 1 Multiplexer Output
 EXPERIMENT 3

Aim: Write down VHDL program for D flip flop and T flip flop.

Apparatus: Xilinx ISE 14.7

System Description:

The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that ensures
that inputs S and R are never equal to one at the same time. The D-type flip flop are constructed
from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a
single D (data) input.
Then this single data input, labelled D, is used in place of the “set” signal, and the inverter is
used to generate the complementary “reset” input thereby making a level-sensitive D-type flip-
flop from a level-sensitive RS-latch as now S = D and R = not D as shown.
T flip flop is also known as “Toggle Flip – flop”. To avoid the occurrence of intermediate state
in SR flip – flop, we should provide only one input to the flip – flop called Trigger input or
Toggle input (T). Then the flip – flop acts as a Toggle switch. Toggling means ‘Changing the
next state output to complement of the present state output’.

We can design the T flip – flop by making simple modifications to the JK flip – flop. The T flip
– flop is a single input device and hence by connecting J and K inputs together and giving them
with single input called T we can convert a JK flip – flop into T flip – flop. So a T flip – flop is
sometimes called as single input JK flip – flop.

D-type Flip-Flop Circuit T-type Flip-Flop Circuit

 Truth Table

SCHEMATIC:

Figure 3.1

D-Flip Flop RTL Schematic

 Figure 3.2

T- Flip Flop RTL Schematic

VHDL CODE FOR D-FLIP FLOP

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 14:15:01 01/25/2017

-- Design Name:

-- Module Name: dflipflop - Behavioral

-- Project Name:

-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:
--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Dfflop is

Port ( clk : in STD_LOGIC;

x : in STD_LOGIC;

pr : in STD_LOGIC;

clr : in STD_LOGIC;

q : out STD_LOGIC) ;

end Dfflop;

architecture Behavioral of Dfflop is

begin

process(clk,clr,pr)

begin

if ((pr = '1') and (clr ='1')) then

q <= 'X';

elsif((pr = '1') and (clr = '0')) then

q <= '1';

elsif((pr = '0') and (clr = '1')) then

q <= '0';

elsif((pr = '0') and (clr = '0')) then

if(rising_edge(clk)) then

q <= x;

end if;

end if;

end process;

end Behavioral;

VHDL CODE FOR T-FLIPFLOP

----------------------------------------------------------------------------------

-- Company:

-- Engineer:

--

-- Create Date: 14:28:44 01/25/2017

-- Design Name:

-- Module Name: Tflipflop - Behavioral

-- Project Name:
-- Target Devices:

-- Tool versions:

-- Description:

--

-- Dependencies:

--

-- Revision:

-- Revision 0.01 - File Created

-- Additional Comments:

--

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity Tflipflop is

Port ( clk : in STD_LOGIC;

x : in STD_LOGIC;
 pr : in STD_LOGIC;

clr : in STD_LOGIC;

q : inout STD_LOGIC);

end Tflipflop;

architecture Behavioral of Tflipflop is

begin

process(clk,clr,pr)

begin

if((pr = '1') and(clr = '0')) then

q <= '1';

elsif((pr = '0') and (clr = '1')) then

q <= '0';

elsif((pr = '1') and (clr = '1')) then

q <= 'X';

elsif((pr = '0') and (clr = '0')) then

if(rising_edge(clk)) then

if(x = '1') then

q <= not(q);

elsif(x = '0') then

q <= q;

end if;
end if;

end if;

end process;

end Behavioral;

OUTPUT:

D flip flop

T flip flop
 EXPERIMENT 4

Aim: To write down VHDL program for 4 to 2 encoder.

Apparatus: Xilinx ISE 14.7

System Description:

An encoder is a device which converts familiar numbers or characters or symbols into a coded
format. It accepts the alphabetic characters and decimal numbers as inputs and produces the
outputs as a coded representation of the inputs.It encodes the given information into a more
compact form. In other words, it is a combinational circuit that performs the opposite function of
a decoder.

The block diagram and truth table of a 4 input encoder is shown in below figure. The truth table
consists of four rows , since , it is assumed that only one input is the value of 1 then the
corresponding binary code associated with that enabled input is displayed at the outputs. It is to
be observed from the table is the output Yo is 1 when either input w1 or w3 is 1, also the output
Y1 is set to 1 when either input w2 or w3 is 1.

Symbol and Truth Table:

SCHEMATIC:

RTL schematic of encoder

VHDL CODE

entityencoderdataflow is

Port ( x : in STD_LOGIC_VECTOR(3 downto 0);

e : in STD_LOGIC;

o : out STD_LOGIC_VECTOR(1 downto 0));

endencoderdataflow;

architecture Behavioral of encoderdataflow is

begin

process(x,e)

begin

if( e = '1') then

case x is
when "0001" => o <= "00";

when "0010" => o <= "10";

when "0100" => o <= "10";

when "1000" => o <= "11";

when others => o <= "XX";

end case;

else

o <= "XX";

end if;

end process ;

end Behavioral;

OUTPUT
 EXPERIMENT 5

Aim: : To write down VHDL program for 2 to 4 decoder.

Apparatus: Xilinx ISE 14.7

System Description:

The Binary Decoder is another combinational logic circuit constructed from individual logic
gates and is the exact opposite to that of an “Encoder” we looked at in the last tutorial. The name
“Decoder” means to translate or decode coded information from one format into another, so a
digital decoder transforms a set of digital input signals into an equivalent decimal code at its
output.

Circuit and Truth Table:

SCHEMATIC:
 RTL schematic of decoder

VHDL CODE

entitydecoderbehavioural is

Port ( x : in STD_LOGIC_VECTOR(1 DOWNTO 0);

e : in STD_LOGIC;

o : out STD_LOGIC_VECTOR(3 DOWNTO 0));

enddecoderbehavioural;

architecture Behavioral of decoderbehavioural is

begin

process(x,e)

begin

if(e = '1') then

case x is

when "00" => o <= "0001";

when "01" => o <= "0010";

when "10" => o <= "0100";

when "11" => o <= "1000";

when others => o <= "XXXX";

end case ;

else

o <= "XXXX";

end if;

end process ;

end Behavioral;

Output
 EXPERIMENT 6

Aim: Write down VHDL program for 1-bit comparator.

Apparatus: Xilinx ISE 14.7

System Description:

A digital comparator or magnitude comparator is a hardware electronic device that takes two
numbers as input in binary form and determine whether one number is greater than, less than or
equal to the other number. Comparators are used in a central processing units (CPU) and
microcontrollers. Examples of digital comparator include the CMOS 4063 and 4585 and the TTL
7485 and 74682-’89.

The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers
have analog comparators on some of their inputs that can be read or trigger an interrupt.

Logic Diagram and Truth Table:

SCHEMATIC:

RTL schematic of 1-bit comparator

VHDL CODE

entity comparator is

Port ( a,b : in STD_LOGIC;

e: in STD_LOGIC;

x,y,z : out STD_LOGIC);

end comparator;

architecture Behavioral of comparator is

begin

process(a,b,e)

begin

if(e = '1') then

if (a>b) then

x<= '1';y<= '0';z<= '0';

elsif (a=b) then

x<= '0';y<= '1';z<= '0';

elsif (a<b) then

x<= '0';y<= '0';z<= '1';

else

x <='X';y<='X'; z <= 'X';

end if ;

end if;

end process ;

end Behavioral;
Output
 EXPERIMENT 7

Aim: Write a VHDL program for a 4-bit comparator.

Apparatus: Xilinx ISE 14.7

System Description:

A digital comparator or magnitude comparator is a hardware circuit that takes two numbers as
input in binary form and determines whether one number is equal to , less than or greater than
the other number. Comparator are used in CPU and microcontroller. Examples of digital
comparator include CMOS 4063 and 4858 and TTL 7485 and 74682-‘89

The analog equivalent of digital comparator is the voltage comparator. Many microcontrollers
have analog comparators on some of their inputs that can be read or trigger an interrupt.

Logic Diagram and Truth Table:

SCHEMATIC:
 RTL schematic of 4-bit comparator

VHDL CODE

entitycomparator_four is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

b : in STD_LOGIC_VECTOR (3 downto 0);

e : in STD_LOGIC;

x : out STD_LOGIC;

y : out STD_LOGIC;

z : out STD_LOGIC);

endcomparator_four;

architecture Behavioral of comparator_four is

begin

process(a,b,e)

begin

if(e = '1') then

if(a>b)

then x<='1'; y<='0';z<='0';

elsif(a<b)

then x<='0'; y<='0';z<='1';

else

x<='0'; y<='1';z<='0';

end if;

else

x <= 'X';

y <= 'X';

z <= 'X';

end if;

end process;

end Behavioral;

Output
 EXPERIMENT 8

Aim: Write down VHDL program for 3-bit Binary to gray Code Convertor.

Apparatus: Xilinx ISE 14.7

System Description:

The reflected binary code, also known as gray code after frank gray, is a binary numerical system
where two successive values differ in only one bit.It is a non-weighted code.

The reflected binary system was originally designed to prevent spurious output from
electromechanical switches. Today, Gray codes are widely used to facilitate error correction in
digital communication such as digital terrestrial and some cable TV systems.

LOGIC DIAGRAM:

TRUTH TABLE:

B(2) B(1) B(0) G(2) G(1) G(0)

0 0 0 0 0 0
0 0 1 0 0 1
0 1 0 0 1 0
0 1 1 0 1 1
1 0 0 1 0 0
1 0 1 1 0 1
1 1 0 1 1 0
1 1 1 1 1 1
SCHEMATIC:

RTL schematic of binary to gray convertor

VHDL CODE

entity b2gray is

Port ( x : in STD_LOGIC_VECTOR(2 downto 0);

e : in STD_LOGIC;

y : out STD_LOGIC_VECTOR(2 downto 0));

end b2gray;

architecture Behavioral of b2gray is

begin

process(x,e)

begin

if(e = '1') then

y(2) <= x(2);

y(1) <= x(2) xor x(1);

y(0) <= x(1) xor x(0);

else y <= "XXX";

end if;

end process;

end Behavioral;

OUTPUT
 EXPERIMENT 9

Aim: Write down VHDL program for BCD to Seven Segment Decoder.

Apparatus: Xilinx ISE 14.7

System Description:

A seven segment display is a form of electronic display device for displaying decimal numerical
that is an alternative to the more complex dot matrix displays. Seven-segment displays are
widely used in digital clocks, electronic meters, and other electronic devices for displaying
numerical information.

The idea of the seven segment display is quite old. In 1910, for example, seven segment display
illuminated by incandescent bulbs were used on a power plant boiler room signal panel.

Truth Table:

Bcd(3) Bcd(2) Bcd(1) Bcd(0) A B C D E F G

0 0 0 0 1 1 1 0 1 1 1

0 0 0 1 0 0 1 0 0 1 0

0 0 1 0 1 0 1 1 1 0 1

0 0 1 1 1 0 1 1 0 1 1

0 1 0 0 0 1 1 1 0 1 0

0 1 0 1 1 1 0 1 0 1 1

0 1 1 0 1 1 0 1 1 1 1

0 1 1 1 1 0 1 0 0 1 0

1 0 0 0 1 1 1 1 1 1 1

1 0 0 1 1 1 1 1 0 1 1
SCHEMATIC:

RTL schematic of BCD to 7 segment decoder

VHDL CODE

entity bcd2seven is

Port ( x : in STD_LOGIC_VECTOR(3 downto 0);

e : in STD_LOGIC;

o : out STD_LOGIC_VECTOR(6 downto 0));

end bcd2seven;
architecture Behavioral of bcd2seven is

begin

process(x,e)

begin

if (e = '1') then

case x is

when "0000" => o <= "0000001";

when "0001" => o <= "1001111";

when "0010" => o <= "0010010";

when "0011" => o <= "0000110";

when "0100" => o <= "1001100";

when "0101" => o <= "0100100";

when "0110" => o <= "0100000";

when "0111" => o <= "0001111";

when "1000" => o <= "0000000";

when "1001" => o <= "0000100";

when others => o <= "XXXXXXX";

end case ;

else

o <= "XXXXXXX";

end if;

end process;

end Behavioral;
OUTPUT
 EXPERIMENT 10

AIM: Write down VHDL program for Serial in Parallel out (SIPO) register using Behavioral
Modelling style.

APPARATUS: Xilinx ISE 14.7

SYSTEM DESCRIPTION:

A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it
shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It is
different in that it makes all the internal stages available as outputs. Therefore, a serial-
in/parallel-out shift register converts data from serial format to parallel format.

The practical application of the serial-in/parallel-out shift register is to convert data from serial
format on a single wire to parallel format on multiple wires. Perhaps, we will illuminate four
LEDs (Light Emitting Diodes) with the four outputs

LOGIC DIAGRAM:

Figure 10.1: SIPO shift register using D- flipflops (4 bit)

The truth table and following waveforms show the propagation of the logic “1” through the
register from left to right as follows:

Basic Data Movement through A Shift Register

Clock Pulse No QA QB QC QD

0 0 0 0 0

1 1 0 0 0

2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0
SCHEMATIC:

Figure 10.2 : 4 bit SIPO RTL Schematic

VHDL CODE
entity sipo_4bit is
Port ( data,clr,clk,en : in STD_LOGIC;
QA,QB,QC,QD: inout STD_LOGIC);
end sipo_4bit;

architecture Behavioral of sipo_4bit is

begin
process(clk,clr)
begin
if (clr = '1') then
QA<='0';QB<='0';QC<='0';QD<='0';
else if(en='1') then
if (rising_edge(clk)) then
QA<=data;
QB<=QA;
QC<=QB;
QD<=QC;
else if(en='0') then
QA<='Z';QB<='Z';QC<='Z';QD<='Z';
end if;
end if;
end if;
end if;
end process;
end Behavioral;

OUTPUT :

Figure 10.3: 4bit SIPO Output

 EXPERIMENT 11

AIM: Write down VHDL program for 3 bit UP/DOWN Counter

APPARATUS: Xilinx ISE 14.7

SYSTEM DESCRIPTION:

In digital logic and computing, a counter is a device which stores (and sometimes displays) the
number of times a particular event or process has occurred, often in relationship to a clock signal.
A counter that can change state in either direction, under the control of an up or down selector
input, is known as an up/down counter. When the selector is in the up state, the counter
increments its value. When the selector is in the down state, the counter decrements the count.

CIRCUIT DIAGRAM

Fig 10.1: 3-bit UP/DOWN counter using T-flip flops

TRUTH TABLE:

C qc qb qa QC QB QA
1 0 0 0 0 0 1
1 0 0 1 0 1 0
1 0 1 0 0 1 1
1 0 1 1 1 0 0
1 1 0 0 1 0 1
1 1 0 1 1 1 0
1 1 1 0 1 1 1
1 1 1 1 0 0 0
0 0 0 0 1 1 1
0 0 0 1 0 0 0
0 0 1 0 0 0 1
0 0 1 1 0 1 0
0 1 0 0 0 1 1
0 1 0 1 1 0 0
0 1 1 0 1 0 1
0 1 1 1 1 1 0

SCHEMATIC:

Fig 10.2 RTL schematic of up/down counter

VHDL CODE:

entity counter is
port( reset,c,clk : in std_logic;
q : inout integer range 0 to 7);
end counter;

architecture Behavioral of counter is

begin

process(clk,reset)
variable ctr: std_logic:='1';
begin

if (reset = '1' or ctr='1') then

q<= 0;
ctr:='0';
else if (rising_edge(clk)) then
if (c='1') then
if (q = 7 and ctr='0') then
q<=0;
else
q<=q + 1;
ctr:='0';
end if;
else if (c='0') then
if (q = 0 and ctr='0' ) then
q<= 7;
else
q<= q - 1;
ctr:='0';
end if;
end if;
end if;
end if;
end if;

end process;
end Behavioral;
OUTPUT:

Fig 10.3: 4-bit up-down counter output

 EXPERIMENT 12

AIM: Write a VHDL program for 3 bit even parity checker using Behavioral modeling style.

APPARATUS: Xilinx ISE 14.7 .

SYSTEM DESCRIPTION:

It is a logic circuit that checks for possible errors in the transmission. This circuit can be an even
parity checker or odd parity checker depending on the type of parity generated at the
transmission end. When this circuit is used as even parity checker, the number of input bits must
always be even.
When a parity error occurs, the ‘sum even’ output goes low and ‘sum odd’ output goes high. If
this logic circuit is used as an odd parity checker, the number of input bits should be odd, but if
an error occurs the ‘sum odd’ output goes low and ‘sum even’ output goes high.

Even Parity Checker

Consider that three input message along with even parity bit is generated at the transmitting end.
These 4 bits are applied as input to the parity checker circuit which checks the possibility of error
on the data. Since the data is transmitted with even parity, four bits received at circuit must have
an even number of 1s.
If any error occurs, the received message consists of odd number of 1s. The output of the parity
checker is denoted by PEC (parity error check).
The below table shows the truth table for the even parity checker in which PEC = 1 if the error
occurs, i.e., the four bits received have odd number of 1s and PEC = 0 if no error occurs, i.e., if
the 4-bit message has even number of 1s.

CIRCUIT DIAGRAM

Figure 12.1: 3 bit Even Prioriy Checker

The above logic expression for the even parity checker can be implemented by using three Ex-
OR gates as shown in figure. If the received message consists of five bits, then one more Ex-OR
gate is required for the even parity checking.
TRUTH TABLE

e x3 x2 x1 x0 o
0 X X X X X
1 0 0 0 1 1
1 0 0 1 0 1
1 0 0 1 1 0
1 0 1 0 0 1
1 0 1 0 1 0
1 0 1 1 0 0
1 0 1 1 1 1
1 1 0 0 0 1
1 1 0 0 1 0
1 1 0 1 0 0
1 1 0 1 1 1

SCHEMATIC:

Figure 12.2: 3 bit Even Parity Checker

VHDL CODE:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entitythreebit is
Port ( x : in STD_LOGIC_VECTOR(3 downto 0);
e : in STD_LOGIC;
o : out STD_LOGIC);
endthreebit;

architecture Behavioral of threebit is

begin
process(x,e)
begin
if(e = '1') then
o <= x(3) xor x(2) xor x(1) xor x(0);
elsif(e = '0') then

o <= 'X';
end if;
end process;
end Behavioral;

OUTPUT:

Figure 12.4: 3 bit Even Priority Checker Output

 EXPERIMENT 13

AIM: Write a VHDL program for 4:2 Priority Encoder using Behavioral modeling style.

APPARATUS: Xilinx ISE 14.7 .

SYSTEM DESCRIPTION:

A 4-bit priority encoder (also sometimes called a priority decoder). This circuit basically
converts the 4-bit input into a binary representation. If the input n is active, all lower inputs (n-1
.. 0) are ignored.
The circuit operation is simple. Each output is driven by an OR-gate which is connected to the
NAND-INV outputs of the corresponding input lines. The NAND gate of each stages receives its
input bit, as well as the NAND gate outputs of all higher priority stages. This structure implies
that an active input on stage n effectively disables all lower stages n-1 to 0.
Note that the circuit function as specified here does not depend at all on the least significand
input bit.
A common use of priority encoders is for interrupt controllers, to select the most critical out of
multiple interrupt requests. Due to electrical reasons (open collector outputs), priority encoders
with active-low inputs are also often used in practice.

CIRCUIT DIGRAM

Figure 13.1: Priority Encoder

TRUTH TABLE

Table 13.1: Priority Encoder Truth Table

x3 x2 x1 x0 y1 y0
1 X X X 1 1
0 1 X X 1 0
0 0 1 X 0 1
0 0 0 1 0 0
SCHEMATIC:

Figure 13.2: 4:2 Priority Encoder RTL Schematic

VHDL CODE:

entitypriorityencoder is
Port ( e : in STD_LOGIC;
x : in STD_LOGIC_VECTOR(3 downto 0);
y : out STD_LOGIC_VECTOR(1 downto 0)
);
endpriorityencoder;

architecture Behavioral of priorityencoder is

begin
process(x,e)
begin
if(e = '1') then
if(x(3) = '1') then
y <= "11";
elsif(x(2) = '1') then
y <= "10";
elsif(x(1) = '1') then
y <= "01";
elsif(x(0) = '1') then
y <= "00";
else
y <= "XX";
end if;
elsif(e = '0') then
y <= "XX";
end if;
end process;
end Behavioral;

OUTPUT

Figure 13.4: 4:2 Priority Encoder Output