Dar es Salaam Maritime Institute

Field Effect Transistor (FET’s)

Instructor: Dr. W. E. Ngongi

Department of Marine Engineering

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Field Effect Transistor (FET)
• Has three terminals just like BJT.

• It is operation principles are

completely different.

• Called UNIPOLAR device because

current flow depends only on one type
of charge carriers holes or
electronics.
2
Field Effect Transistor (FET) cont. …

• It is a voltage controlled device (while

BJT is current controlled device) i.e. the
current flow is controlled by an
external applied voltage.
• There are two main types of FETs:
– Junction Field Effect Transistor (JFET)
– Metal-Oxide Semiconductor FET
(MOSFET).
3
 D
IC D - Drain
ID

G = Gate
IB BJT G FET S = Source

VGS
S
IE
IS

Current Controlled Voltage Controlled

IB and IC ID and VGS

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Junction FET (Simplified Structure)

Drain (D)

P N P
Gate
DEPLETION
LAYER

Source (S)

n-channel (JFET)

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Junction FET (Simplified Structure) cont. …

Drain (D)

N N
P
Gate
DEPLETION
LAYER

Source (S)

p-channel (JFET)

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Circuit symbol

OR n - Channel

OR p - Channel

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Junction FET cont. …
• In the absence of any applied voltage the
JFET has two p-n junctions under no bias
condition.
• The result is a deflection region at each
junction.

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Basic Operation of JFET
ID
D Deflection
Region

e
e
N VDS
P P
e
Gate
e DEPLETION
LAYER

VGS = 0V, VDS some voltage 9

Basic Operation of JFET cont. …
• JFET operates with reverse biased gate
channel junction (i.e. no conduction
between the gate and the channel).
• For n-channel JFET, VGS ≤ 0, i.e. VGS max =
0.

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 D

ID

VA
VA

VB

VC

VS S
VA>VB>VC>VS

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Basic Operation of JFET cont. …
• The width of the depletion layer depends
on the magnitude of the reverse.
• Voltage between the p and n material
ID

IDSS VGS

0 VDS
VP
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Basic Operation of JFET cont. …
• As VDS is increased we find that the
current ID increases in direction
proportional to it.
• But the increase in VDS causes the
depletion region to increase until the
region are also about to meet near the
drain end.
• This condition is called PINCH – OFF.

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Basic Operation of JFET cont. …
• At the point where pinch-off occur the -
gate - to - channel- is reversed by the
value VDS. This value is called the pinch-
off voltage VP.
• For VDS above pinch-off voltage ID remains
constant. This value of current is called
saturation current, IDSS.
• IDSS is the maximum current which a
transistor can produce.
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Basic Operation of JFET cont. …
• Saturation current, IDSS is the
maximum drain current, ID that a
specific JFET can produce regardless
of the external circuit.
ID

VGS = 0V
IDSS
Constant current or
active region Breakdown
Dynamic
region

0 VDS
VP
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Drain characteristics
• JFET is operated in the constant current
region.

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 Drain Characteristics

ID
D

VDS
G P P
N

VGS

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Drain characteristics cont. …
ID (mA)

VGS = 0

VGS = -1V
VGS = -2V
VGS = -3V

VDS (V)
VP VGS = -4 (Cut-off)

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Drain characteristics cont. …
• Increasing the reverse bias value of VGS
(i.e. making VGS more negative) causes
the pinch-off condition to occur at smaller
values of VDS and the smaller saturation
current results.
• IDSS is defined for VGS = 0 and VDS ≥ | VP|,
VGS = -4 is called VGS (Cut-off).
• This value of VGS is called VGS (cut-off).

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Drain characteristics cont. …
• VP and VGS (cut-off) are always equal in
magnitude but opposite in sign e.g. VP =
+4V, VGS (cut-off) = -4V.

• Increasing the reverse bias value of VGS

(i.e. making VGS more negative).

• The dashed line which is a parabola joins

on each curve where pinch-off occurs.
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Drain characteristics cont. …
• The value of VDS on the parabola is called
saturation voltage VDS (sat).

• The equation of the parabola is:

2
 VDS(sat) 
I D  I DSS  
 P 
V
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Drain characteristics cont. …
• In any value of VGS, the corresponding
VDS(sat) is the deference between VGS and
VP. i.e.

VDS(Sat)  VGS  VP

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Transfer characteristics
• Plot of output current (ID) versus input
current voltage (VGS) for fixed output
voltage (VDS).
• ID = f(VGS)|VDS = constant
• the transfer characteristics is given by:
2
 VGS 
I D  I DSS 1  
 VP 
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P-channel JFET
ID
D

VDS
G N N
P

VGS

VGS ≥ 0V, VDS ≤ 0V 24

 ID (mA)

VGS = 0V
IDSS
VGS = +1V
VGS = +2V
VGS = +3V
VGS = +4V
-VDS (V)
4 3 2 1 VDS = constant
VP
Transfer Characteristics Drain Characteristics

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Example
• For a given cct below VGS(cut-off) = -4V and
IDSS = 12mA. Determine the minimum
value of VDD required to put the transistor
in constant current region of operation.
• Given: VGS = 0;
IDSS = 12mA;
VGS (cut-off) = -4V;
VDD min = ?

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 RD = 560Ω

VDS
VDD
VGS

N-Channel

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Example cont. …
• For the transistor to be in the linear region
VDS ≥ VP
• For VDD min, VDS = VP, but |VP| = |VGS cut-off|
• VDS = VP = 4V and ID = IDSS because VGS =
0.

VDD  VDS  ID R D
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For VDD min  VDS min  I D R D
 VP  I D R D
 VP  I DSSR D
 4V  12mA  560Ω
VDD min  10.72V
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JFET Biasing
• Like BJT, a JFET used as an ac amplifier
must be biased in order to create a dc
output voltage around which ac variation
can occur (Q-point).
• For a common source configuration the
input is VGS and the output is VDS.
iD

Ugs Ugs is used to control iD

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ID

Q-point VGS = -1V

VDS

Load Line

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Fixed Bias
VDD

ID

RD

G
VDS

VGS
VDS

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Fixed Bias
• Two dc power supplies VDD and VGS
• VDS = VDD – IDRD

VDD VDS
ID  
RD RD

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Example
• Given IDSS = 10mA and VP = 4V. Compute
the Q-point values of ID and when VGS = -
1.5V. Assume that the JFET is biased in
the pinch-off region. V
DD

RD = 2kΩ

VGS

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Solution
2
 VGS 
I D  I DSS 1   pinch region
 VP 
I D  3.9mA
VDS  VDD  I D R D  8.2V

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Self bias
- Requires only a single dc supply
VDD

ID

RD

S
VGS

RS IDRS

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VG  0V

VS  I D R S

VGS  VG  VS  0  I D R S
VGS  IDR S
VDS  VDD  I D R S  R D 
2
 VGS 
Recall I D  I DSS 1 - 
 VP  37
VGS  IDR S
General algebraic solution is
 B  B  4AC
2

ID 
2A
A  RS
2
where
2
 VP 
B   2 VP R S  
 I DSS 
C  VP
2

Hence VDS  VDD  I D R S  R D  38

Example
• For the JFET given below determine the Q-point
values of ID and VDS if IDSS = 10mA and VP = -4V.
VDD = 15V

RD = 1.5kΩ

RS = 600Ω

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A  3.6  10 5

B  6.4  10 3

C  16
I D  3.0mA
VDS  8.7V

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Small-signal JFET parameter
• Transconductance
• Defined as the ratio of small signal output
current to small signal input voltage with
the dc output held constant.

io
gm 
uin Vo  constant

41
For JFET

id = io

ugs = uin

id
gm 
u gs VDS  Constant 42
Also
ΔI D
gm 
ΔVGS VDS  Constant

Transconductance is the slop of the transfer characteristics.

It can be shown that;

2I DSS ID
gm  (Siemens)
VP I DS
-value of gm increases with increasing ID and is
maximum when ID = IDSS
- When ID = IDSS, gm is given a special symbol gmo. 43
 2I DSS
g mo  (Siemens)
VP
From
2IDSS I D
gm 
VP I DSS

2
 VGS 
I DSS 1  
gm 
2I DSS  VP 
VP I DSS
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 2I DSS  VGS 
gm  1  
VP  VP 

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Output resistance

u dS
ro 
id VGS  constant

VDS
ro 
I D VGS  constant

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 ID

VGS = Constant

ΔID

ΔVGS

VDS

- Also called Drain Resistance rd or rds

- It can be determined graphically fro the output characteristics
- Value of rd range from about 50kΩ to several hundreds kΩ in
pinch off region.

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Input resistance
• JFET operates with its gate – source
reverse biased.

VGS
Rin  where I GSS is the source Reverse saturation current
I GSS

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Small-signal equivalent cct of a
JFET D

D
G
id = gmugs

rd
ugs
G

S S
Common Source
Configuration
id
gm   id  g m u gs  control voltage
u gs
- Voltage controlled current source 49
Fixed bias ac equivalent circuit
VDD

RD

C2
C1

RS
RG
RL Uout
RS

VG

US

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AC equivalent circuit

RS
gmus

ug
RG rd RD RL uout

us

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 uout
Au 
us
But; uout  id rd // RD // RL 
  g m u gs rd // RD // RL 

u s  u gs 
R S
 RG 
RG
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 uout g m u gs rd // RD // RL 
Au  
us
u gs 
 RS  RG 
RG
 RG 
Au      g m   rd // RD // RL 
G  RS 
R
Source Gain

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Metal-Oxide Semiconductor FET
(MOSFET)
• Recall from JFET
• Different from JFET is that has no pn
junction structure.
• The gate is insulated from the channel by
a silicon oxide (SiO2) layer.
• Because of the insulated gate, the devices
are sometimes called IGFETs (Insulated
Gate FET) 54
Metal-Oxide Semiconductor FET
(MOSFET) cont. …
• There are two basic types of MOSFETs;
• Depletion type MOSFET (D-MOSFET)
• Enhanced type MOSFET (E- MOSFET)

55
Depletion MOSFET (D-MOSFET)
• Basic structure:
Drain

SUBSTRATE

N P
Gate (VG)

SiO2
Source

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Depletion MOSFET (D-MOSFET)
cont. …
• The gate and channel form two parallel
plates and the SiO2 as dielectric medium.
• If the gate is made –ve, the –ve charges on
the gate repel.
• Conduction of electrons from the channel,
leaving positive ions, therefore the channel
becomes less conductive (The channel is
depleted of electrons).
57
Depletion MOSFET (D-MOSFET)
cont. …
• With gate made positive conduction
electrons are attracted into the channel
thus increasing (Enhancing) the channel
conductivity.
• Therefore a D-MOSFET can be operated
in Depletion Mode (VG is –ve) and
Enhanced Mode (VG is +ve).

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Circuit symbol

Substrate (SS)

G
S

N-Channel MOSFET

59
 D

Substrate (SS)

G
S

P-Channel MOSFET

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Depletion MOSFET (D-MOSFET)
cont. …
• The substrate (the main body is usually
connected to the source
D D

G G
S S

N-Channel P-Channel

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Enhancement MOSFET (E-
MOSFET)
• Operates only in the enhancement mode,
there is no depletion mode.
• It has no physical channel
D

N SUBSTRATE

P
G (+ve)

SiO2
62
S
Enhancement MOSFET (E-
MOSFET) cont. …
• The substrate extends all the way to the
SiO2 layer.
• With gate made +ve electrons will be
attracted from the substrate to the region
along the insulating layer opposite to the
gate.
• Therefore the gate is converted into an N-
channel between Drain and Source.
63
Enhancement MOSFET (E-
MOSFET) cont. …
• Making the gate more +ve enhances the
conductivity of the channel.
• The induced N-channel does not become
sufficiently conductive to allow drain
correct to flow until VGS reaches certain
Threshold voltage VT which ranges from
1V to 3V.

64
 D D

G G
S S

N-Channel E-MOSFET P-Channel E-MOSFET

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Handling precautions
• All MOS devices are subjected to damage
from electrostatic discharge (ESD).
• Excessive static charge can be
accumulated because of the transistor
input capacitance. This can damage the
transistor.
• Store MOS device in conductive foam.

66
Handling precautions cont. …
• The handler’s wrist should be connected
to earths ground.
• Properly ground instruments and metal be
benches.
• Never remove a MOS device from a circuit
while the power is on.

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