22CS206-DIGITAL COMPUTER ELECTRONICS

SIMULATION OF CONTROL UNIT FUNCTIONALITY

Exp. No. : 9
Date :

AIM:

To Design and simulate the functionality of control unit..

APPARATUS REQUIRED:

Control Design and Simulation Module.

Use the Control Design VIs and functions to construct, analyze, and deploy dynamic system models in
LabVIEW.

The VIs on these palettes can return general LabVIEW error codes or specific control design error
codes.

THEORY:

The control unit (CU) is a component of a computer's central processing unit (CPU) that
directs the operation of the processor. A CU typically uses a binary decoder to convert coded
instructions into timing and control signals that direct the operation of the other units
(memory, arithmetic logic unit and input and output devices, etc.).Most computer resources are
managed by the CU. It directs the flow of data between the CPU and the other devices
The component which receives the input signal/information/instruction from the user and
converts into control signals for the execution in the CPU. It controls and directs the main memory,
arithmetic & logic unit (ALU), input and output devices, and also responsible for the instructions that
are sent to the CPU of a computer. It fetches the instructions from the main memory of a processor and
sent to the processor instruction register, which contains register contents.
 22CS206-DIGITAL COMPUTER ELECTRONICS

PROCEDURE:

Design of Control Unit

The design of this can be done using two types of a control unit which include the following.
● Hardwire based
● Microprogrammed based(single-level and two-level)

Hardwired Control Unit

The basic design of a hardwired control unit is shown above. In this type, the control signals are
generated by a special hardware logic circuit without any change in the structure of the circuit. In this,
the generated signal cannot be modified for execution in the processor.
The basic data of an opcode (operation code of an instruction is sent to the instruction decoder for
decoding. The instruction decoder is the set of decoders to decode different types of data in the
opcode. This results in output signals which contain values of active signals that are given as the input
to the matrix generator to generate control signals for the execution of a program by the processor of
the computer.

The matrix generator provides states of controls unit and the signals out from the processor (interrupt
signals). Matrix is built as the programmable logic array. The control signals generated by the matrix
generator are given as the input to the next generator matrix and combines with the timing signals of
the timing unit that contains rectangular patterns.
For fetching of new instruction, the control unit turns into an initial stage for the execution of new
instruction. The control unit remains in the initial stage or first stage as long as the timing signals,
input signals, and states of instruction of a computer are unchanged. The change in the state of the
control unit can be raised if there any change in any of the generated signals.

When an external signal or interrupt occurs, the control unit goes to the next state and performs the
processing of the interrupt signal. The flags and states are used to select the desired states to perform
the execution cycle of instruction.
 22CS206-DIGITAL COMPUTER ELECTRONICS

In the last state, the control unit fetches the next instruction and sends the output to the program
counter, then to the memory address register, to the buffer register, and then to the instruction register
to read the instruction. Finally, if the last instruction (which is fetched by the control unit) is end
instruction, then it goes to the operating state of the processor and waits until the user directs the next
program.

Micro Programmed Control Unit

In this type, the control store is used to store the control signals which are encoded during the
execution of a program. The control signal is not generated immediately and decoded because the
microprogram stores address field in the control store. The whole process is a single level.

The micro-operations are done for the execution of micro-instructions in the program. The block
diagram of the Micro programmed control unit is shown above. From the diagram, the address of the
micro-instruction is obtained from the control memory address register. All the info of the control unit
is permanently stored in the control memory called ROM.

Microprogrammed based Control Unit

The micro-instruction from the control memory is held by the control register. Since the micro-
instruction is in the form of control word (contains binary control values) that needs 1 or more micro-
operations to be performed for the data processing.

During the execution of micro-instructions, the next address generator computed the next address of
the micro-instruction and then send to the control address register to read the next micro-instruction.
The sequence of micro-operations of a micro-program is performed by the next address generator and
acts as microprogram sequencer to get the sequence address i.e., read from the control memory.
 22CS206-DIGITAL COMPUTER ELECTRONICS

Verilog Code for the Control Unit

`include “prj_definition.v”

module CONTROL_UNIT(MEM_DATA, RF_DATA_W, RF_ADDR_W, RF_ADDR_R1,

RF_ADDR_R2, RF_READ, RF_WRITE, ALU_OP1, ALU_OP2, ALU_OPRN, MEM_ADDR,
MEM_READ, MEM_WRITE, RF_DATA_R1, RF_DATA_R2, ALU_RESULT, ZERO, CLK, RST)

// Output signals
// Outputs for register file

output [`DATA_INDEX_LIMIT:0] RF_DATA_W;

output [`ADDRESS_INDEX_LIMIT:0] RF_ADDR_W, RF_ADDR_R1, RF_ADDR_R2;
output RF_READ, RF_WRITE;

// Outputs for ALU

output [`DATA_INDEX_LIMIT:0] ALU_OP1, ALU_OP2;
output [`ALU_OPRN_INDEX_LIMIT:0] ALU_OPRN;

// Outputs for memory

output [`ADDRESS_INDEX_LIMIT:0] MEM_ADDR;
output MEM_READ, MEM_WRITE;

// Input signals
input [`DATA_INDEX_LIMIT:0] RF_DATA_R1, RF_DATA_R2, ALU_RESULT;
input ZERO, CLK, RST;

// Inout signal
inout [`DATA_INDEX_LIMIT:0] MEM_DATA;

// State nets
wire [2:0] proc_state;

//holds program counter value, stores the current instruction, stack pointer register

reg MEM_READ, MEM_WRITE;

reg MEM_ADDR;
reg ALU_OP1, ALU_OP2;
reg ALU_OPRN;
reg RF_ADDR_W, RF_ADDR_R1, RF_ADDR_R2;
reg RF_DATA_W;
reg [1:0] state, next_state;

PROC_SM state_machine(.STATE(proc_state),.CLK(CLK),.RST(RST));

always @ (posedge CLK)

begin
if (RST)
state <= RST;
else
state <= next_state;
 22CS206-DIGITAL COMPUTER ELECTRONICS

end

always @ (state)
begin

MEM_READ = 1’b0; MEM_WRITE = 1’b0; MEM_ADDR = 1’b0;

ALU_OP1 = 1’b0; ALU_OP2 = 1’b0; ALU_OPRN = 1’b0;
RF_ADDR_R1 = 1’b0; RF_ADDR_R2 = 1’b0; RF_ADDR_W = 1’b0; RF_DATA_W = 1’b0;

case( state )

`PROC_FETCH : begin
next_state = `PROC_DECODE;
MEM_READ = 1’b1;
RF_ADDR_R1 = 1’b0; RF_ADDR_R2 = 1’b0;
RF_ADDR_W = 1’b1;
end

`PROC_DECODE : begin
next_state = `PROC_EXE;
MEM_ADDR = 1’b1;
ALU_OP1 = 1’b1; ALU_OP2 = 1’b1; ALU_OPRN = 1’b1;
MEM_WRITE = 1’b1;
RF_ADDR_R1 = 1’b1; RF_ADDR_R2 = 1’b1;
end

`PROC_EXE : begin
next_state = `PROC_MEM;
ALU_OP1 = 1’b1; ALU_OP2 = 1’b1; ALU_OPRN = 1’b1;
RF_ADDR_R1 = 1’b0;
end

`PROC_MEM: begin
next_state = `PROC_WB;
MEM_READ = 1’b1; MEM_WRITE = 1’b0;
end

`PROC_WB: begin
next_state = `PROC_FETCH;
MEM_READ = 1’b1; MEM_WRITE = 1’b0;
end
endcase

end
endmodule;

module PROC_SM(STATE,CLK,RST);
// list of inputs
input CLK, RST;
// list of outputs
output [2:0] STATE;

// input list
input CLK, RST;
 22CS206-DIGITAL COMPUTER ELECTRONICS

// output list
output STATE;

reg [2:0] STATE;

reg [1:0] state;
reg [1:0] next_state;

reg PC_REG, INST_REG, SP_REF;

`define PROC_FETCH 3’h0

`define PROC_DECODE 3’h1
`define PROC_EXE 3’h2
`define PROC_MEM 3’h3
`define PROC_WB 3’h4

// initiation of state
initial
begin
state = 2’bxx;
next_state = `PROC_FETCH;
end

// reset signal handling

always @ (posedge RST)
begin
state = `PROC_FETCH;
next_state = `PROC_FETCH;
end
always @ (posedge CLK)
begin
state = next_state;
end
always @(state)
begin
if (state === `PROC_FETCH)
begin
next_state = `PROC_DECODE;

print_instruction(INST_REG);
end

if (state === `PROC_DECODE)

begin
next_state = `PROC_EXE;

end

if (state === `PROC_EXE)

begin
next_state = `PROC_MEM;

print_instruction(SP_REF);
end
 22CS206-DIGITAL COMPUTER ELECTRONICS

if (state === `PROC_MEM)

begin
next_state = `PROC_WB;

end

if (state === `PROC_WB)

begin
next_state = `PROC_FETCH;

print_instruction(PC_REG);
end
end

task print_instruction;

input [`DATA_INDEX_LIMIT:0] inst;

reg [5:0] opcode;

reg [4:0] rs;
reg [4:0] rt;
reg [4:0] rd;
reg [4:0] shamt; reg [5:0] funct; reg [15:0] immediate; reg [25:0] address;

begin

// parse the instruction

// R-type

{opcode, rs, rt, rd, shamt, funct} = inst;

// I-type
{opcode, rs, rt, immediate } = inst;
// J-type
{opcode, address} = inst;
$write(“@ %6dns -> [0X%08h] “, $time, inst);
case(opcode) // R-Type
6’h00 : begin
case(funct)

6’h20: $write(“add r[%02d], r[%02d], r[%02d];”, rs, rt, rd);

6’h22: $write(“sub r[%02d], r[%02d], r[%02d];”, rs, rt, rd);
6’h2c: $write(“mul r[%02d], r[%02d], r[%02d];”, rs, rt, rd);
6’h24: $write(“and r[%02d], r[%02d], r[%02d];”, rs, rt, rd);
6’h25: $write(“or r[%02d], r[%02d], r[%02d];”, rs, rt, rd);
6’h27: $write(“nor r[%02d], r[%02d], r[%02d];”, rs, rt, rd);
6’h2a: $write(“slt r[%02d], r[%02d], r[%02d];”, rs, rt, rd);
6’h00: $write(“sll r[%02d], %2d, r[%02d];”, rs, shamt, rd);
6’h02: $write(“srl r[%02d], 0X%02h, r[%02d];”, rs, shamt, rd);
6’h08: $write(“jr r[%02d];”, rs);
default: $write(“”);
endcase
end
 22CS206-DIGITAL COMPUTER ELECTRONICS

// I-type

6’h08 : $write(“addi r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);

6’h1d : $write(“muli r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);
6’h0c : $write(“andi r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);
6’h0d : $write(“ori r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);
6’h0f : $write(“lui r[%02d], 0X%04h;”, rt, immediate);
6’h0a : $write(“slti r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);
6’h04 : $write(“beq r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);
6’h05 : $write(“bne r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);
6’h23 : $write(“lw r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);
6’h2b : $write(“sw r[%02d], r[%02d], 0X%04h;”, rs, rt, immediate);

// J-Type

6’h02 : $write(“jmp 0X%07h;”, address);

6’h03 : $write(“jal 0X%07h;”, address);
6’h1b : $write(“push;”);
6’h1c : $write(“pop;”);
default: $write(“”);
endcase
$write (“\n”);
end
endtask
end module;

RESULT:

Hence Design and Simulation of control unit functionality has been verified.