2023

2. a) Draw and explain the output characteristics of a p-n-p transitor in CE mode.

b) Define β of a transistor.
Ans:

a) Output Characteristics of a p-n-p Transistor in CE Mode

In the Common Emitter configuration, the emitter terminal serves as the common point for both input and
output circuits. For a p-n-p transistor, the current directions are opposite to those in an n-p-n transistor, but
the characteristic curves remain similar in shape.
Circuit Setup:
 Input: Applied between the base and emitter terminals.
 Output: Taken between the collector and emitter terminals
 Biasing: The emitter-base junction is forward-biased, and the collector-base junction is reverse-
biased.Output Characteristics:
The output characteristics depict the relationship between the collector current (I C) and the collector-
emitter voltage (VCE) for various levels of base current (IB). These curves are typically plotted with IC on the
y-axis and VCE on the x-axis.

The graph is divided into three distinct regions:

1. Cut-off Region: In this region, both the emitter-base and collector-base junctions are reverse-
biased. As a result, the transistor is in the "off" state, and the collector current (I C) is nearly zero,
regardless of the collector-emitter voltage (VCE).
2. Active Region: Here, the emitter-base junction is forward-biased, and the collector-base junction is
reverse-biased. The transistor operates as an amplifier in this region. The collector current (I C)
increases with an increase in base current (IB) and remains relatively constant with changes in VCE.
3. Saturation Region: In this region, both the emitter-base and collector-base junctions are forward-
biased. The transistor is in the "on" state, and the collector current (IC) increases rapidly with a small
increase in VCE.
Understanding these regions is crucial for designing and analyzing transistor-based amplifier and switching
circuits.
b) Definition of β (Beta) of a Transistor
The parameter β (beta) of a transistor, also known as the current gain, is a measure of the transistor's
amplification capability. It is defined as the ratio of the collector current (IC) to the base current (IB) in the
active region of operation:
β= Ib/Ic
This means that a small current entering the base terminal controls a much larger current flowing from the
collector to the emitter. For instance, if β = 100, a base current of 20 μA would result in a collector current
of 2 mA. The value of β varies among different transistors and can range from 20 to 200 or more,
depending on the transistor's design and manufacturing.
Understanding β is essential for designing transistor amplifier circuits, as it helps determine the required
base current to achieve a desired collector current.
c) Relationship Between α and β
In a transistor, α (alpha) is the common-base current gain, defined as the ratio of collector current (I C) to
emitter current (IE):
α= IC/ IE
The relationship between α and β is given by
β=α/(1−α)
Conversely,
α=β/(β+1)
These equations show that while α is slightly less than 1, β is much larger, which helps in amplifying signals
in common-emitter configurations.

3. a) Derive the stability factor against ICO of a transistor circuit in fixed-biased condition.
(b) Draw and explain the dc load line of CE transistor amplifier.
a) Derivation of Stability Factor Against ICO in Fixed-Bias Configuration
In a fixed-bias transistor circuit, the base resistor (RB) is connected directly to the supply voltage (VCC),
setting the base current (IB) independent of the collector current (IC).
The collector current is given by:

IC=βIB+(1+β)ICO
To determine the sensitivity of IC to changes in the leakage current ICO, we define the stability factor (S) as:

S=dIC/dICO
=1+β
This indicates that in a fixed-bias configuration, the collector current is highly sensitive to variations in I CO,
leading to poor thermal stability.
3. b) DC Load Line of a CE Transistor Amplifier

The DC load line represents all possible combinations of IC and VCE for a given collector resistor (RC) and
supply voltage (VCC) in a CE amplifier.
Applying Kirchhoff's Voltage Law (KVL) to the collector circuit:

VCC=ICRC+::contentReference[oaicite:60]index=60

4. (a) Write down the difference between Depletion type and Enhancement type MOSFETS.
(b) Explain with a circuit diagram, the working of a MOSFETs switch.
(c) What is CMOS? Discuss the operation of a CMOS inverter with necessary diagram.

(a) Difference between Depletion-type and Enhancement-type MOSFETs

Feature Depletion MOSFET Enhancement MOSFET

A channel already exists between No channel exists initially; induced when VGS
Channel
source and drain. exceeds threshold.

Default State Normally ON when VGS = 0. Normally OFF when VGS = 0.

Can work in both depletion and

Operation Modes Can operate only in enhancement mode.
enhancement modes.

Gate Voltage Negative (to deplete) or positive (to

Only positive gate voltage induces a channel.
Requirement enhance).

A depletion MOSFET can conduct at VGS = 0, whereas enhancement MOSFET requires VGS Vth to conduct.

(b) Working of a MOSFET Switch with Circuit Diagram

MOSFETs, particularly Enhancement-mode NMOS, are extensively used as electronic switches.
Working Principle

 At VGS <Vth (threshold voltage): The MOSFET is OFF, acting as an open switch—no conduction.

 At VGS >Vth : The MOSFET turns ON, creating a low-resistance path between drain and source—
acting as a closed switch.
Circuit Diagram
which shows a MOSFET inverter where the MOSFET acts as a
switch:

 Input Vi is connected to the gate.

 Drain is connected to VDD through a resistor (or active

load).
  Output is taken from the drain.
 Source is grounded.

When Vi is high, the MOSFET conducts, output is low.

When Vi is low, the MOSFET is off, output is high.

(c) What is CMOS? Operation of a CMOS Inverter with Diagram

CMOS (Complementary MOS)
CMOS stands for Complementary Metal-Oxide-Semiconductor. It uses both NMOS and PMOS transistors
on a single chip, offering:
 High speed,
 High noise immunity,
 Extremely low power consumption (almost zero static current).
CMOS Inverter Operation
 Consists of one NMOS and one PMOS transistor connected in series.
 The input Vi is connected to both gates.
 The output Vo is taken from their common drain connection.

 The PMOS source is connected to + VDD, NMOS source is grounded.

Logic Operation

 When Vi is low (0):

o PMOS is ON, NMOS is OFF → Output is high.

 When Vi is high (1):

o NMOS is ON, PMOS is OFF → Output is low.

Hence, the circuit inverts the input logic.
Diagram

Why CMOS is Widely Used

  Extremely low static power dissipation (since only one transistor conducts at a time).
 High density logic gate integration.
 Scalability for LSI, VLSI, and modern microprocessor designs.

5.(a) What do you mean by feedback in amplifier?

b) Explain the voltage shunt feedback amplifier with a neat diagram.
c) Why positive feedback is used? What are the Barkhausen criteria?
(a) What do you mean by feedback in amplifier?
Feedback in an amplifier refers to the process in which a portion of the output signal is returned (or “fed
back”) to the input. This can alter the input signal, and consequently, the performance of the amplifier.
There are two types of feedback:
 Positive (Regenerative) Feedback:
The feedback signal is in phase with the input signal, reinforcing it and increasing the overall gain. If
the loop gain becomes unity, the amplifier can start oscillating—essentially turning into an oscillator.
 Negative (Degenerative) Feedback:
The feedback signal is out of phase with the input signal, thereby reducing the effective input and
hence the overall gain. Although it reduces gain, negative feedback improves amplifier stability,
reduces distortion, increases bandwidth, and modifies input/output impedance favorably.

(b) Voltage Shunt Feedback Amplifier with Diagram

A voltage-shunt feedback amplifier samples the output voltage and feeds a current proportional to it back
into the input in parallel (shunt). It's commonly realized using a common-emitter amplifier.
Working:
 The feedback network is connected in parallel with both the output and the input.
 The feedback current is proportional to the output voltage.
 This current adds to the input signal current at the base of the transistor.
As input signal voltage increases:
 Output voltage increases,
 Which increases the feedback current,
 Which opposes the input signal current,
 Resulting in negative feedback.
Diagram:
which shows the circuit of a voltage-shunt feedback amplifier using a CE configuration.

(c) Why is Positive Feedback Used? What are the Barkhausen Criteria?
Why Positive Feedback is Used:
Positive feedback is not commonly used in amplifiers due to its tendency to cause instability. However, it is
essential in circuits like oscillators, where a signal is needed to sustain continuous oscillation without an
external input.
By reinforcing the signal with a properly phased feedback, the system can generate a periodic waveform
(e.g., sine wave, square wave) from a DC supply.

Barkhausen Criteria for Oscillation

For a feedback amplifier to act as an oscillator, it must satisfy the Barkhausen criteria:
1. Magnitude Condition: The loop gain (|Aβ|) must be equal to 1.
2. Phase Condition: The total phase shift around the loop must be 0° or an integral multiple of 360°.
These conditions ensure that the feedback signal reinforces the input signal in both magnitude and phase,
enabling self-sustained oscillations without any external excitation.
Mathematically, for oscillation:

|Aβ| = 1

6.(a) What do you understand by Class A, Class B and Class C power amplifier? Explain with diagrams.
b) What do you mean by the efficiency of a power amplifier?
(a) Class A, Class B, and Class C Power Amplifiers (with Diagrams)
Power amplifiers are classified into Class A, B, AB, and C based on the conduction angle of the output
current with respect to the input signal.
Class A Amplifier
 Conduction angle: 360° (entire input cycle).
 Biasing: Q-point is placed at the center of the load line.
 Current flows at all times through the output device.
 Linear operation → low distortion.
 Poor efficiency due to continuous power dissipation.
Diagram:

Efficiency: Max 25% with resistive load, improved to 50% with transformer coupling.

Class B Amplifier
 Conduction angle: 180° (half the input cycle).
 Biasing: Q-point is at cut-off.
 Push-pull configuration is typically used:
o One transistor conducts during positive half-cycle.
o The other conducts during negative half-cycle.
 Much higher efficiency, but crossover distortion may occur.
Diagram:

Efficiency: Max theoretical efficiency is 78.5%.

Class C Amplifier
 Conduction angle: <180° (less than half the input cycle).
 Biasing: Transistor is biased well beyond cut-off.
 Current flows in short pulses.
 Highly efficient but introduces strong distortion.
 Used for RF applications with a tuned circuit at the output.
Diagram:

Efficiency: Can reach up to 85% in practice.

6(b) What is the Efficiency of a Power Amplifier?

The efficiency (η) of a power amplifier is the ratio of a.c. output power delivered to the load to the d.c.
input power supplied by the power source.

η= (PAC Output/PDC Input) ×100%

Where:

 PAC Output=Vrms⋅Irms
 PDC Input=VCC⋅IQ
Efficiency is important in determining how much power is usefully converted into signal versus how much
is wasted as heat.
Typical Maximum Efficiencies:
 Class A (resistive load): ~25%
 Class A (transformer coupled): ~50%
 Class B: up to 78.5%
 Class C: up to 85%
2023 Pt-2
2. a) What do you mean by degenerate semiconductor
B) Show the portion of Fermi level in n-type and p-type degenerate semiconductors
c) Explain with a energy band diagram, the dependence of Fermi level in n-type semiconductor due to
change in temperature
(a) What do you mean by a degenerate semiconductor?
A degenerate semiconductor is a heavily doped semiconductor in which the doping concentration is so
high that:
 The Fermi level shifts into the conduction band (for n-type) or into the valence band (for p-type).
 The carrier concentration becomes comparable to or even exceeds the density of quantum states
in the respective band.
 Classical Maxwell-Boltzmann statistics no longer apply; instead, Fermi-Dirac statistics must be used.
 The material exhibits metal-like conduction properties.
Degenerate semiconductors behave similarly to poor metals and are used in specialized devices like tunnel
diodes.
By contrast, a non-degenerate semiconductor has relatively low doping, where the Fermi level lies within
the forbidden energy gap, and the conduction follows classical behavior.

2(b) Fermi Level in n-type and p-type Degenerate Semiconductors

 In an n-type degenerate semiconductor, the Fermi level (EF) lies inside the conduction band.
 In a p-type degenerate semiconductor, the Fermi level lies inside the valence band.

 For high doping (ND> Nc), EF moves above EC.

 For heavy acceptor doping in p-type (NA>> Nv), EF drops below EV.

2(c) Dependence of Fermi Level in n-type Semiconductor on Temperature (with Energy Band Diagram)
At Low Temperature:
 The donor atoms are fully ionized.
 The Fermi level lies close to the conduction band, but still within the gap if doping is moderate.
With Increase in Temperature:
 More intrinsic carriers (electron-hole pairs) are generated thermally.
 Since donor atoms are already ionized, these thermally generated electrons dominate.
 The semiconductor behavior shifts from extrinsic to intrinsic.

The Fermi level moves toward the center of the band gap, i.e., it drops from near EC toward midgap.
At High Temperature:
 The material behaves like an intrinsic semiconductor.
 Fermi level lies approximately in the middle of the forbidden gap.
Energy Band Diagram:
EC ← Conduction band edge
|
| ← Fermi level (moves down with T ↑)
|
|-------------------------- Midgap
|
| ← Valence band edge
EV
Equations:

EF = EC −kT ln(NC/ND)
shows how EF shifts downward with increasing T for n-type semiconductors.

3. (a) What do you mean by drill and diffusion currents? Deduce Einstien's relationship relating to these
currents
(b) Explain the continuity equation in semiconductor
(c) How electron-hole pair recombination takes place in semiconductor?
3(a) What do you mean by Drift and Diffusion Currents? Derive Einstein's Relation
Drift Current:
 Caused by electric field.
 Electrons and holes move in opposite directions due to force exerted by the electric field:

Jdrift=e(nμn+pμp)E
where μn,μp= mobilities of electrons and holes; E = electric field.

Diffusion Current:
 Caused by carrier concentration gradient.
 Carriers move from high to low concentration.
 Electron and hole diffusion current densities are:
where Dn , Dp= diffusion constants.

Einstein’s Relation (Derivation):

 In equilibrium, drift and diffusion currents balance:

 Comparing expressions for drift and diffusion, we get:

This is Einstein's relation: it connects mobility and diffusion constant.

3(b) Continuity Equation in Semiconductors

The continuity equation is based on the conservation of electric charge. It accounts for generation,
recombination, drift, and diffusion.
For holes:

 Jp = hole current density

 Gp = generation rate
 τp = hole lifetime
 p0 = equilibrium hole concentration
Similarly, for electrons:

3(c) Electron-Hole Recombination in Semiconductors

 Recombination is the process where an electron from the conduction band falls into a hole in the
valence band, neutralizing the charge pair.
 Energy ≈ Eg is released as heat or radiation.
 Occurs through:
 o Band-to-band recombination
o Trap-assisted recombination via defect centers
The recombination rate depends on:

This leads to an exponential decay of excess carriers.

4. (a) What is Schottky contact? How does it differ from ohmic contact? What do you mean by ideal
ohmic constant?
(b) In what conditions a metal semiconductor junction is rectifying?
(c) Explain the avalanche breakdown mechanism briefly.

4(a) What is a Schottky Contact? How does it differ from an Ohmic Contact? What is an Ideal Ohmic
Contact?
Schottky Contact:
 A metal-semiconductor junction that forms a rectifying (diode-like) behavior.
 Has a barrier that blocks carrier flow in one direction.
Ohmic Contact:
 A contact that allows easy bidirectional flow of current (non-rectifying).
 Achieved by using heavily doped regions and selecting proper metals to minimize barrier height.
Ideal Ohmic Contact:
 Perfectly linear I–V characteristics (obeys Ohm’s Law).
 Has negligible contact resistance.

4(b) Conditions for a Rectifying Metal-Semiconductor Junction

A metal-semiconductor junction becomes rectifying when:

 The metal work function (ϕm) > semiconductor electron affinity + energy gap, leading to band
bending.

 In an n-type, if ϕm > ϕs → Schottky barrier forms.

 Results in depletion region and diode-like behavior.

4(c) Avalanche Breakdown Mechanism
 Occurs in reverse-biased p-n junctions at high voltages.
 High electric field accelerates minority carriers, giving them energy to ionize lattice atoms →
generates more electron-hole pairs.
 Chain reaction leads to sudden increase in current.
Key points:
 Breakdown is non-destructive if current is limited.
 Used in Zener diodes and avalanche photodiodes.

5. (a) What do you mean by reverse saturation current of a PN junction diode?

b) Discuss the DC equivalent circuit of a real PN junction diode.
(c) What are static and dynamic resistances of a PN junction diode?
(d) Draw and explain the C-V characteristics of varactor diode.

5(a) What do you mean by reverse saturation current of a PN junction diode?

The reverse saturation current I0 is the small constant current that flows through a reverse-biased PN
junction diode due to the minority charge carriers.
 It is independent of the magnitude of the reverse bias (up to breakdown).
 It is strongly temperature-dependent—approximately doubles for every 10°C rise in temperature.
 Mathematically, from Shockley’s equation:

 For silicon diodes, typical values of I0 are nanoamperes, while for germanium diodes it is in
microamperes.

5(b) DC Equivalent Circuit of a Real PN Junction Diode

A real PN junction diode is modeled as:
 An ideal diode (which conducts only in one direction),

 A forward voltage drop Vγ≈0.7 (for Si),

 A series resistance rs due to bulk material resistance.

So, the DC equivalent circuit is:

Ideal Diode → Threshold Voltage Source (Vγ) → Series Resistance (rs)

This is used in practical circuit analysis to account for non-idealities such as internal resistance and
threshold behavior.

5(c) Static and Dynamic Resistances of a PN Junction Diode

Static Resistance Rdc:
 Defined as the ratio of voltage to current at a given operating point:

Rdc =V/I
 It gives the overall slope from the origin to a point on the diode's I-V curve.

Dynamic (AC) Resistance rd:

 Also called incremental resistance.

 It is the slope of the tangent to the I-V curve at the operating point:

Where:
o η≈1 Ge and ≈2for Si,
o at room temperature.
Dynamic resistance decreases with increasing current, making it
crucial for small-signal applications.

5(d) C-V Characteristics of Varactor Diode

What is a Varactor Diode?
 A voltage-variable capacitor, also called varicap.
 Operates under reverse bias only.
 Capacitance depends on depletion layer width, which varies with reverse voltage.
Working Principle:
 As reverse bias VR increases:
o Depletion region widens,

o Capacitance Cr decreases.

C-V Relationship:
  n=1/2 for abrupt junction, 1/3 for diffused junctions.
Applications:
 Tuning circuits in radios, TVs, FM receivers.
 Voltage-controlled oscillators (VCOs), parametric amplifiers.
Diagram:

Shows:
 Reverse bias terminal,

 Variable transition capacitance Cr ,

 Series resistance Rs.

6.) Can two back-to-back PN junction diodes be considered equivalent to a transistor?

(b) Explain with a diagram, the output characteristics of a BJT in CB mode.
(c) An NPN BJT has α=0.95 and base current of 50 µA. Find the emitter current and collector current if the
collector to base leakage current is 4 µA.

6(a) Can two back-to-back PN junction diodes be considered equivalent to a transistor?

No, two discrete PN junction diodes connected back-to-back do not form a working transistor.
Why?
While a BJT physically contains two PN junctions, simply connecting two separate diodes does not create
transistor action, because:
 In a transistor, the middle (base) region is very thin, allowing injected carriers from the emitter to
diffuse across to the collector.
 In discrete diodes, there is no shared base region that can support carrier diffusion.
 The Ebers-Moll model shows that transistor action is dependent on carrier transport across a thin
base, which two independent diodes cannot replicate.
“It is not possible to construct a transistor by simply connecting two isolated diodes back-to-back... carriers
injected across one junction must diffuse across the other junction”.
6(b) Output Characteristics of BJT in Common Base (CB) Mode
Circuit Setup:
 Input is between emitter and base.
 Output is between collector and base.
 Base is common (grounded for AC signals).
Characteristic Curves:

Three Regions:
1. Active Region:
o Emitter junction forward biased, collector junction reverse biased.

o IC≈αIE (almost constant for given IE ).

o Slight increase due to Early effect.
2. Saturation Region:
o Both emitter and collector junctions are forward biased.
o Collector current drops; transistor can't amplify.
3. Cut-off Region:
o Both junctions are reverse biased.

o Collector current is nearly zero (except tiny leakage ICBO).

These regions help in designing amplifiers and switching circuits.

6(c) Numerical: NPN BJT with α = 0.95, IB = 50 μA, ICBO = 4 μA. Find IE and IC
We’ll use the following equations:
Let’s substitute step-by-step:

Step 1: Express IC in terms of IE:

Step 2: Use the identity IE=IB+IC

Substitute into Step 1:

Step 3: Find IE

✅ Final Answer:
 Collector current (IC) = 1.03 mA
 Emitter current (IE ) = 1.08 mA

7. (a) Define pinch-off voltage in a JFET. Mention the parameters which can control the pinch-off voltage.
(b) Draw the cross-sectional view of a JFET showing the depletion region at Pinch off and after Pinch off.
(e) Why n-channel MOSFETs are preferred in high frequency application?

7(a) Define Pinch-Off Voltage in a JFET. What Parameters Control It?

Pinch-off Voltage (VP):
 The pinch-off voltage is the value of reverse gate-source voltage at which the conduction channel
of a JFET just closes, and drain current becomes constant.
 Denoted as VP or VGS(off).
 At this point, the depletion regions from both sides of the gate touch, and no further increase in ID
occurs despite increase in VDS.
“Practically, for certain value of VGS, the drain current is reduced to zero. This voltage is called pinch-off
voltage”.
Parameters Controlling Pinch-Off Voltage:
Pinch-off voltage depends on:
 Doping concentration (ND)
 Gate junction characteristics
 Channel thickness
 Permittivity of semiconductor (ε)
Mathematically :

Where:
 a = channel half-width,
 ND = donor concentration,
 e = electronic charge,
 ε = permittivity of semiconductor material.

7(b) Draw the Cross-sectional View of a JFET Showing the Depletion Region at and After Pinch-Off
At Pinch-Off:
 Depletion regions from gate P-N junctions just touch each other near the drain end.
 The channel is pinched, current becomes saturated.
After Pinch-Off:
 Increasing VDS doesn't increase ID significantly.
 The pinch-off point moves slightly toward the source, but current remains constant.
You’ll see:
 A wedge-shaped channel,
 Wider depletion region at the drain end,
 Complete pinch-off at a critical VGS.
Let me know if you'd like me to redraw this diagram for clarity.

7(c) Why Are N-Channel MOSFETs Preferred in High-Frequency Applications?

N-channel MOSFETs are preferred in high-frequency circuits because:
1. Higher Mobility of Electrons:
o Electron mobility (in n-channel) is about 2–3 times that of holes (in p-channel).
o Higher mobility means faster response, lower ON resistance, and better switching speed.
2. Lower Capacitance:
o Gate-to-source and gate-to-drain capacitances are smaller in n-MOS, leading to lower input
impedance degradation at high frequencies.
3. Better Drive Strength:
o N-MOSFETs can sink more current than P-MOSFETs of the same dimensions.
“At high frequencies, capacitive feedback affects the gain. N-channel devices perform better due to higher
mobility and faster switching”.
These advantages make n-MOS the preferred choice in:
 RF amplifiers
 CMOS logic gates
 VCOs and RF mixers