INTRODUCTION OFINSTRUCTION

SET ARCHITECTURE

Name : saipranaya chepuri

Roll no: 21951A6244
Branch: cyber security
Subject: computer organization and
architecture
 What Is an Instruction Set Architecture

 An Instruction Set Architecture (ISA) is part of the abstract model of

a computer that defines how the CPU is controlled by the software.
The ISA acts as an interface between the hardware and the
software, specifying both what the processor is capable of doing as
well as how it gets done.
 The ISA provides the only way through which a user is able to
interact with the hardware. It can be viewed as a programmer’s
manual because it’s the portion of the machine that’s visible to the
assembly language programmer, the compiler writer, and the
application programmer.
 The ISA defines the supported data types, the registers, how the
hardware manages main memory, key features (such as virtual
memory), which instructions a microprocessor can execute, and the
input/output model of multiple ISA implementations. The ISA can be
extended by adding instructions or other capabilities, or by adding
support for larger addresses and data values.
 Why the ISA Is Important?

 Understanding what the instruction set can do and

how the compiler makes use of those instructions
can help developers write more efficient code. It
can also help them understand the output of the
compiler which can be useful for debugging. Arm
is opening its instruction set architecture for
Cortex M cores. By allowing licensees to build
their own custom instructions, developers are able
to accelerate specialized workloads. The Arm ISA
family allows developers to write software and
firmware that conforms to the Arm specifications,
secure in the knowledge that any Arm-based
processor will execute it in the same way.
 An instruction set architecture is distinguished from a micro architecture, which is
the set of processor design techniques used, in a particular processor, to implement
the instruction set. Processors with different micro architectures can share a
common instruction set. For example, the Intel Pentium and the AMD Athlon
implement nearly identical versions of the x86 instruction set, but they have
radically different internal designs.
 The concept of an architecture, distinct from the design of a specific machine, was
developed by Fred Brooks at IBM during the design phase of System/360.
 Prior to NPL [System/360], the company's computer designers had been free to
honor cost objectives not only by selecting technologies but also by fashioning
functional and architectural refinements. The SPREAD compatibility objective, in
contrast, postulated a single architecture for a series of five processors spanning a
wide range of cost and performance. None of the five engineering design teams
could count on being able to bring about adjustments in architectural specifications
as a way of easing difficulties in achieving cost and performance objectives. [1]: p.137
 Some virtual machines that support byte code as their ISA such as Smalltalk, the
Java virtual machine, and Microsoft's Common Language Runtime, implement this
by translating the byte code for commonly used code paths into native machine
code. In addition, these virtual machines execute less frequently used code paths
by interpretation (see: Just-in-time compilation). Transmeta implemented the x86
instruction set atop VLIW processors in this fashion.
 Classification of ISAs

 An ISA may be classified in a number of different ways. A common

classification is by architectural complexity. A
complex instruction set computer (CISC) has many specialized
instructions, some of which may only be rarely used in practical programs.
A reduced instruction set computer (RISC) simplifies the processor by
efficiently implementing only the instructions that are frequently used in
programs, while the less common operations are implemented as
subroutines, having their resulting additional processor execution time
offset by infrequent use.[2]
 Other types include very long instruction word (VLIW) architectures, and
the closely related long instruction word (LIW) and
explicitly parallel instruction computing (EPIC) architectures. These
architectures seek to exploit instruction-level parallelism with less
hardware than RISC and CISC by making the compiler responsible for
instruction issue and scheduling.
 Architectures with even less complexity have been studied, such as the
minimal instruction set computer (MISC) and one-instruction set computer
(OISC). These are theoretically important types, but have not been
commercialized.
 Instructions

 Machine language is built up from

discrete statements or instructions. On the
processing architecture, a given instruction may
specify:
 opcode (the instruction to be performed) e.g.
add, copy, test
 any explicit operands:
 registersliteral/constant valuesaddressing modes
used to access memoryMore complex operations
are built up by combining these simple
instructions, which are executed sequentially, or
as otherwise directed by control flow instructions.
 Instruction types

 Data handling and memory

operations
 Arithmetic and logic operations
 Control flow operations
 Coprocessor instructions
 Complex instructions
 Data handling and memory operations

 Set a register to a fixed constant value.

 Copy data from a memory location or a
register to a memory location or a register (a
machine instruction is often called move;
however, the term is misleading). They are
used to store the contents of a register, the
contents of another memory location or the
result of a computation, or to retrieve stored
data to perform a computation on it later.
They are often called load and store
operations.
 Read and write data from hardware devices.
Arithmetic and logic operations

 Add, subtract, multiply, or divide the values of two

registers, placing the result in a register, possibly
setting one or more condition codes in a
status register.
 increment, decrement in some ISAs, saving operand fetch
in trivial cases.
 Perform bitwise operations, e.g., taking the
conjunction and disjunction of corresponding bits in a
pair of registers, taking the negation of each bit in a
register.
 Compare two values in registers (for example, to see
if one is less, or if they are equal).
 Floating-point instructions for arithmetic on floating-
point numbers.
 Control flow operations

 Branch to another location in the

program and execute instructions there.
 Conditionally branch to another location
if a certain condition holds.
 Indirectly branch to another location.
 Call another block of code, while saving
the location of the next instruction as a
point to return to.
 Coprocessor instructions

 Load/store data to and from a

coprocessor or exchanging with CPU
registers.
 Perform coprocessor operations.
 Complex instructions

 Processors may include "complex" instructions in their instruction set. A single "complex"
instruction does something that may take many instructions on other computers. Such
instructions are typified by instructions that take multiple steps, control multiple functional
units, or otherwise appear on a larger scale than the bulk of simple instructions
implemented by the given processor. Some examples of "complex" instructions include:
 transferring multiple registers to or from memory (especially the stack) at once
 moving large blocks of memory (e.g. string copy or DMA transfer)
 complicated integer and floating-point arithmetic (e.g. square root, or
transcendental functions such as logarithm, sine, cosine, etc.)
 SIMD instructions, a single instruction performing an operation on many homogeneous
values in parallel, possibly in dedicated SIMD registers
 performing an atomic test-and-set instruction or other read-modify-write atomic instruction
 instructions that perform ALU operations with an operand from memory rather than a
register
 Complex instructions are more common in CISC instruction sets than in RISC instruction
sets, but RISC instruction sets may include them as well. RISC instruction sets generally do
not include ALU operations with memory operands, or instructions to move large blocks of
memory, but most RISC instruction sets include SIMD or vector instructions that perform the
same arithmetic operation on multiple pieces of data at the same time. SIMD instructions
have the ability of manipulating large vectors and matrices in minimal time. SIMD
instructions allow easy parallelization of algorithms commonly involved in sound, image,
and video processing. Various SIMD implementations have been brought to market under
trade names such as MMX, 3DNow!, and AltiVec.
 Instruction encoding

 On traditional architectures, an instruction includes an opcode that specifies the operation to

perform, such as add contents of memory to register—and zero or more operand specifiers,
which may specify registers, memory locations, or literal data. The operand specifiers may
have addressing modes determining their meaning or may be in fixed fields. In
very long instruction word (VLIW) architectures, which include many microcode architectures,
multiple simultaneous opcodes and operands are specified in a single instruction.
 Some exotic instruction sets do not have an opcode field, such as
transport triggered architectures (TTA), only operand(s).
 Most stack machines have "0-operand" instruction sets in which arithmetic and logical
operations lack any operand specifier fields; only instructions that push operands onto the
evaluation stack or that pop operands from the stack into variables have operand specifiers.
The instruction set carries out most ALU actions with postfix (reverse Polish notation)
operations that work only on the expression stack, not on data registers or arbitrary main
memory cells. This can be very convenient for compiling high-level languages, because most
arithmetic expressions can be easily translated into postfix notation. [3]
 Conditional instructions often have a predicate field—a few bits that encode the specific
condition to cause an operation to be performed rather than not performed. For example, a
conditional branch instruction will transfer control if the condition is true, so that execution
proceeds to a different part of the program, and not transfer control if the condition is false, so
that execution continues sequentially. Some instruction sets also have conditional moves, so
that the move will be executed, and the data stored in the target location, if the condition is
true, and not executed, and the target location not modified, if the condition is false. Similarly,
IBM z/Architecture has a conditional store instruction. A few instruction sets include a predicate
field in every instruction; this is called branch predication.
 Number of operands

 0-operand (zero-address machines), so called stack machines: All arithmetic operations take place using
the top one or two positions on the stack: push a, push b, add, pop c.
 C = A+B needs four instructions. For stack machines, the terms "0-operand" and "zero-address" apply to arithmetic
instructions, but not to all instructions, as 1-operand push and pop instructions are used to access memory.
 1-operand (one-address machines), so called accumulator machines, include early computers and many
small microcontrollers: most instructions specify a single right operand (that is, constant, a register, or a
memory location), with the implicit accumulator as the left operand (and the destination if there is
one): load a, add b, store c.
 C = A+B needs three instructions.
 2-operand — many CISC and RISC machines fall under this category:
 CISC — move A to C; then add B to C.
 C = A+B needs two instructions. This effectively 'stores' the result without an explicit store instruction.
 CISC — Often machines are limited to one memory operand per instruction: load a,reg1; add b,reg1; store reg1,c;
This requires a load/store pair for any memory movement regardless of whether the add result is an augmentation
stored to a different place, as in C = A+B, or the same memory location: A = A+B.
 C = A+B needs three instructions.
 RISC — Requiring explicit memory loads, the instructions would be: load a,reg1; load b,reg2; add reg1,reg2; store
reg2,c.
 C = A+B needs four instructions.
 3-operand, allowing better reuse of data:[4]
 CISC — It becomes either a single instruction: add a,b,c
 C = A+B needs one instruction.
 CISC — Or, on machines limited to two memory operands per instruction, move a,reg1; add reg1,b,c;
 C = A+B needs two instructions.
 RISC — arithmetic instructions use registers only, so explicit 2-operand load/store instructions are needed: load
a,reg1; load b,reg2; add reg1+reg2->reg3; store reg3,c;
 C = A+B needs four instructions.
 Unlike 2-operand or 1-operand, this leaves all three values a, b, and c in registers available for further reuse.
 more operands—some CISC machines permit a variety of addressing modes
that allow more than 3 operands (registers or memory accesses), such as the
VAX "POLY" polynomial evaluation instruction.
 Due to the large number of bits needed to encode the three registers of a 3-
operand instruction, RISC architectures that have 16-bit instructions are
invariably 2-operand designs, such as the Atmel AVR, TI MSP430, and some
versions of ARM Thumb. RISC architectures that have 32-bit instructions are
usually 3-operand designs, such as the ARM, AVR32, MIPS, Power ISA, and
SPARC architectures.
 Each instruction specifies some number of operands (registers, memory
locations, or immediate values) explicitly. Some instructions give one or both
operands implicitly, such as by being stored on top of the stack or in an implicit
register. If some of the operands are given implicitly, fewer operands need be
specified in the instruction. When a "destination operand" explicitly specifies
the destination, an additional operand must be supplied. Consequently, the
number of operands encoded in an instruction may differ from the
mathematically necessary number of arguments for a logical or arithmetic
operation (the arity). Operands are either encoded in the "opcode"
representation of the instruction, or else are given as values or addresses
following the opcode.
 Instruction set implementation

 Any given instruction set can be implemented in a variety of ways. All ways of
implementing a particular instruction set provide the same programming model,
and all implementations of that instruction set are able to run the same
executables. The various ways of implementing an instruction set give different
tradeoffs between cost, performance, power consumption, size, etc.
 When designing the microarchitecture of a processor, engineers use blocks of
"hard-wired" electronic circuitry (often designed separately) such as adders,
multiplexers, counters, registers, ALUs, etc. Some kind of
register transfer language is then often used to describe the decoding and
sequencing of each instruction of an ISA using this physical microarchitecture.
There are two basic ways to build a control unit to implement this description
(although many designs use middle ways or compromises):
 Some computer designs "hardwire" the complete instruction set decoding and
sequencing (just like the rest of the microarchitecture).
 Other designs employ microcode routines or tables (or both) to do this—
typically as on-chip ROMs or PLAs or both (although separate RAMs and ROMs
have been used historically). The Western Digital MCP-1600 is an older
example, using a dedicated, separate ROM for microcode.
 Some designs use a combination of hardwired design and microcode for the
control unit.
 Some CPU designs use a writable control store—they compile the instruction
set to a writable RAM or flash inside the CPU (such as the Rekursiv processor
and the Imsys Cjip),[11] or an FPGA (reconfigurable computing).
 An ISA can also be emulated in software by an interpreter. Naturally, due to
the interpretation overhead, this is slower than directly running programs on
the emulated hardware, unless the hardware running the emulator is an
order of magnitude faster. Today, it is common practice for vendors of new
ISAs or microarchitectures to make software emulators available to software
developers before the hardware implementation is ready.
 Often the details of the implementation have a strong influence on the
particular instructions selected for the instruction set. For example, many
implementations of the instruction pipeline only allow a single memory load
or memory store per instruction, leading to a load–store architecture (RISC).
For another example, some early ways of implementing the
instruction pipeline led to a delay slot.
 The demands of high-speed digital signal processing have pushed in the
opposite direction—forcing instructions to be implemented in a particular
way. For example, to perform digital filters fast enough, the MAC instruction
in a typical digital signal processor (DSP) must use a kind of
Harvard architecture that can fetch an instruction and two data words
simultaneously, and it requires a single-cycle multiply–accumulate multiplier.
Thank-you