UNIT II

CORTEX M3 Memory Map

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 Memory Mapping
Fixed default memory map
that provides up to 4GB of
addressable memory

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 Memory Types

memory types

Normal - Processor can Device - Processor

re-order transactions Strongly-ordered -
preserves transaction Processor preserves
for efficiency, or order relative to other
perform speculative transaction order relative
transactions to Device / to all other transactions
reads Strongly-ordered
memory

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 Additional Memory Attributes
 Shareable - Memory system provides data
synchronization between bus masters in a system with
multiple bus masters
 Ex:- a processor with a DMA controller
 Strongly-ordered memory is always shareable. If multiple
bus masters can access a non-shareable memory region,
software must ensure data coherency between the bus
masters.
 Execute Never (XN) - Means the processor prevents
instruction accesses. A fault exception is generated only on
execution of an instruction executed from an XN region.

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 Memory Access Behavior

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 Bit Banding (SRAM)
• A bit-band region maps each word in a bit-band alias region to a single
bit in the bit-band region
• The bit-band regions occupy the lowest 1MB of the SRAM and
peripheral memory regions
SRAM memory bit-banding regions
Address Memory Instruction and Data Accesses
Range Region
0x20000000 - SRAM bit-band Direct accesses to this memory range
0x200FFFFF region behave as SRAM memory accesses, but
this region is also bit addressable through
bit-band alias.
0x22000000 - SRAM bit-band Data accesses to this region are remapped
0x23FFFFFF alias to bit band region. A write operation is
performed as read-modify-write.
Instruction accesses are not remapped.
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 Bit Banding (Peripheral)
Peripherals memory bit-banding regions

Address Range Memory Region Instruction and Data Accesses

0x40000000 - Peripheral bit- Direct accesses to this memory range behave
0x400FFFFF band region as peripheral memory accesses, but this
region is also bit addressable through bit-band
alias.
0x42000000 - Peripheral bit- Data accesses to this region are remapped to
0x43FFFFFF band alias bit band region. A write operation is
performed as read-modify-write. Instruction
accesses are not permitted.

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 Bit Banding Process
 The following formula shows how the alias region maps onto the
bit-band region:
bit_word_addr = bit_band_base + bit_word_offset
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
where:
 Bit_word_addr is the address of the word in the alias memory
region that maps to the targeted bit.
 Bit_band_base is the starting address of the alias region.
 Byte_offset is the number of the byte in the bit-band region that
contains the targeted bit.
 Bit_word_offset is the position of the target bit in the bit-band
memory region.

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 Example
Estimate the bit band alias word to manipulate bit [7] of bit band byte at
0x20000000 in SRAM bit band region.
Given,
Bit number = 7
Target bit address in SRAM bit band region = 0x20000000
WKT, Base addresses of SRAM bit-band region = 0x20000000 &
SRAM alias = 0x22000000
Find, Bit word address in bit band alias region
bit_word_addr = bit_band_base + bit_word_offset
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
Byte offset = target bit address - base address
= 0x20000000 - 0x20000000 = 0
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
= (0 x 32) + (7 x 4) = 0 + 28 = 28d = 0x1C
bit_word_addr = bit_band_base + bit_word_offset
= 0x22000000 + 0x1C
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= 0x2200001CARM CORTEX M3 10
 Bit Banding

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 Example 1
Estimate the bit band alias word to manipulate bit [4] of bit band byte at
0x20000003 in SRAM bit band region.
Given,
Bit number = 4
Target bit address in SRAM bit band region = 0x20000003
WKT, Base addresses of SRAM bit-band region = 0x20000000 &
SRAM alias = 0x22000000
Find, Bit word address in bit band alias region
bit_word_addr = bit_band_base + bit_word_offset
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
Byte offset = target bit address - base address
= 0x20000003 - 0x20000000 = 3
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
= (3 x 32) + (4 x 4) = 96 +16 = 112d = 0x70
bit_word_addr = bit_band_base + bit_word_offset
= 0x22000000 + 0x70
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= 0x22000070ARM CORTEX M3 12
 Example 2
Estimate the bit band alias word to manipulate bit [7] of bit band byte at
0x200FFFFE in SRAM bit band region.
Given,
Bit number = 7
Target bit address in SRAM bit band region = 0x200FFFFE
WKT, Base addresses of SRAM bit-band region = 0x20000000 &
SRAM alias = 0x22000000
Find, Bit word address in bit band alias region
bit_word_addr = bit_band_base + bit_word_offset
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
Byte offset = target bit address - base address
= 0x200FFFFE - 0x20000000 = 0x FFFFE = 1048574d
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
= (1048574 x 32) + (7 x 4) = 33554396d
= 0x1FFFFDC
bit_word_addr = bit_band_base + bit_word_offset
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= 0x22000000 + 0x1FFFFDC
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= 0x23FFFFDC
 Example 3
Estimate the bit band alias word to manipulate bit [3] of bit band byte at
0x40000000 in peripheral bit band region.
Given,
Bit number = 3
Target bit address in peripheral bit band region = 0x40000000
WKT, Base addresses of Peripheral bit-band region = 0x40000000 &
Peripheral alias = 0x42000000
Find, Bit word address in bit band alias region
bit_word_addr = bit_band_base + bit_word_offset
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
Byte offset = target bit address - base address
= 0x40000000 - 0x40000000 = 0
bit_word_offset = (byte_offset x 32) + (bit_number x 4)
= (0 x 32) + (3 x 4) = 0+12 = 12d = 0xC
bit_word_addr = bit_band_base + bit_word_offset
= 0x42000000 + 0xC
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= 0x4200000CARM CORTEX M3 14
 Power Management
• The Cortex-M3 processor sleep modes reduce power
consumption
• They might do one or all of the following:
• sleep mode stops the processor clock
• deep sleep mode stops the system clock and switches off
the PLL and flash memory.
• If your device implements two sleep modes providing
different levels of power saving, the SLEEPDEEP bit of the SCR
selects which sleep mode is used
 Power Management – Entering Sleep Mode
Wait For Interrupt (WFI):
• WFI instruction, causes immediate entry to sleep mode unless the wake-up
condition is true
Wait For Event (WFE):
• WFE instruction, causes entry to sleep mode depending on the value of a
one-bit event register.
checks the value of the event register:
0 - Processor stops executing instructions and enters sleep mode.
1 - Processor clears register to 0 & continues executing instructions
without entering sleep mode.
• Event bit is set when external event signal is asserted, or a processor in the
system has executed an SEV (send event) instruction
• Software cannot access this register directly
Sleep-on-exit:
• If the SLEEPONEXIT bit of the SCR is set to 1, when the processor
completes the execution of all exception handlers it returns to Thread
mode and immediately enters sleep mode.
• Use this mechanism in applications that only require the processor to run
when an exception occurs.
 Power Management – Wakeup from Sleep Mode
The conditions for the processor to wakeup depend on the mechanism that
cause it to enter sleep mode.
Wakeup from WFI or sleep-on-exit:
Normally, the processor wakes up only when it detects an exception with
sufficient priority to cause exception entry
Wakeup from WFE:
The processor wakes up if:
• it detects an exception with sufficient priority to cause exception entry
• it detects an external event signal
• in a multiprocessor system, another processor in the system executes an
SEV instruction.
• The processor, even if the interrupt is disabled or has insufficient addition, if
the SEVONPEND bit in the SCR is set to 1, any new pending interrupt
triggers an event and wakes up nth priority to cause exception entry
Wakeup Interrupt Controller (WIC):
• Optional Peripheral, not programmable, operates from hardware signals
• Device might include a WIC, that can detect an interrupt and wake the
processor from deep sleep mode.
• The WIC is enabled only when the DEEPSLEEP bit in the SCR is set to 1
 Cortex Microcontroller Software Interface Standard (CMSIS)

CMSIS defines:
• a common way to: access peripheral registers & define
exception vectors
• the names of: the registers of the core peripherals & the core
exception vectors
• a device-independent interface for RTOS kernels, including a
debug channel.
 The CMSIS includes address definitions and data structures
for the core peripherals in the Cortex-M3 processor.
 CMSIS simplifies software development by enabling the reuse
of template code and the combination of CMSIS-compliant
software components from various middleware vendors.
 Software vendors can expand the CMSIS to include their
peripheral definitions and access functions for those
peripherals.
 THANK YOU

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