UNIT-1

(2-marks)
1. What is a combinational circuit?
2. Which combinational circuit is otherwise known as data selector?Why?
3. Write down the sum and carry expressions of half adder.
4. How many selection inputs, data inputs and output for 16 X 1 MUX?
5. Construct Half-adder and full adder circuits
6. Evaluate the logic circuit of 2 bit comparator.
7. List the four possible elementary operations simple binary addition consists of.
8. What is a multiplexer?

(13-marks)
1. Present the graphic symbol, algebraic expression and truth table for the following digital
logic gates: AND, OR, Inverter, Buffer, NAND, NOR, Exclusive OR and Exclusive NOR.
2. What is a K-map? Simplify the Boolean function F(w,x,y,z) = ∑(0,1,2,4,5,6,8,9,12,13,14)
Using K-map.
3. (i) How will you design a full adder using two half adders?
(ii) Simplify the function using multiplexer f= ∑(0,1,3,4,8,9,15).
4. (i) Demonstrate 4 bit magnitude comparator with three inputs A>B, A=B, A<B.
(ii) Build a 4 bit priority encoder using gates.
5. Explain a full adder and full subtractor with the help of circuit diagrams.
6. Explain binary to octal decoder and octal to binary encoder with the help of circuit diagrams.
7. Why do we need code conversion? Explain with the conversion of binary to gray code.
8. Identify the combinational circuit that is used to compare the relative magnitude of two
binary numbers. Construct the identified circuit for comparing 2-bit binary numbers.

(15-marks)
1. Outline the design of a three to eight line decoder circuit using “inverters” and “AND” gates.
Also, present the truth table for the same.
2. Implement the following Boolean function using 8x1 multiplexer.
Considering D as the input and A, B, C as selection lines.
f(A, B, C, D) = AB’ + BD + B’CD’.
3. Using K-map, find the sum of products and product of sums for the given function
F= ∑m( 0,2,6,7,8,10,12,14,15)
4. Design 8x1 MUX. Implement the following Boolean function using 8x1 MUX
F(P, Q, R, S) = ∑m(0,1,3,4,8,9,15).
 UNIT-2

(2-marks)
1. Outline the difference between a synchronous sequential circuit and an asynchronous
sequential circuit.
2. Define a latch and a flip-flop.
3. Distinguish sequential logic with combinational logic.
4. Give the excitation table of JK flip flop.
5. How many flip flops are required for designing BCD counter?Justify.
6. List the functional units of a digital computer.
7. Compare Mealy and Moore Models.
8. Write down the characteristic table of T flip flop.

(13-marks)
1. (i) What is an SR latch? Outline the design of SR latch using NOR gates, Also, present the
function table for the same.
(ii) Outline the design of a D flip-flop with two D latches and an inverter with a diagram.
2. (i) Outline the Mealy model and Moore model of sequential circuits with a diagram.
(ii) What is a shift register? Outline the design of a four-bit shift register with a diagram.
3. (i) Realize D flip flop using SR flip flop
(ii) Construct a 4 bit down counter using logic gates.
4. Give the analysis and design of clocked sequential circuits.
5. Describe J-K and D flip flops with the help of block diagrams and characteristic tables.
6. Which counter is called a decade counter? Why? Explain the operation of the same in
asynchronous mode.
7. Which flip flop is called as data flip flop? Explain the operation of the same with its circuit
diagrams, characteristic table and excitation table.

(15-marks)
1. Design a Mod-5 Synchronous counter using JK flip flop
2. Outline the design of a BCD ripple counter using JK flip flops with state diagram and logic
diagram.
3. Explain the functions with the state diagram and characteristic equation of T, D and JK flip
flop. Compare and contrast.
4. Design a Mod-7 Synchronous counter using JK flip flop.
 UNIT-3

(2-marks)
1. What are data transfer instructions? Specify any two data transfer instructions.
2. Outline instruction cycle with a diagram.
3. Draw the stock diagram of Von-Neumann architecture.
4. List the types of addressing mode.
5. List the functional units of a digital computer.
6. Interpret the Instruction Set Architecture.
7. What is the difference between register addressing mode and register indirect addressing
mode?

(13-marks)
1. Explain Von Neumann Architecture with a neat sketch.
2. What is an addressing mode? Outline the types of addressing mode with an example.
3. (i) Explain about functional units in digital computer.
(ii) Discuss about instruction cycle.
4. (i) Explain about encoding in assembly language and types of instructions.
(ii) Discuss the interaction between assembly language and high level language.
5. Describe instruction sequencing and branching with examples.

∑
 UNIT-4

(2-marks)
1. What is a program counter?
2. Define pipelining. List its types.
3. Differentiate data hazards and control hazards.
4. When do data hazards occur in pipelining?
5. Differentiate: Hardwired Control and Microprogrammed Control.

(13-marks)
1. Draw a simple MIPS data path with control unit and explain the execution of ALU
instruction.
2. Describe the methods for avoiding the control hazards.
3. Depict how instruction is being fetched and executed through data path in the processor?
4. Describe data hazards and control hazards. Explain with suitable techniques, how these
hazards can be mitigated?
5. An instruction pipeline has five stages where each stage takes 2 nanoseconds and all
instructions use all five stages, branch instruction are not overlapped (i.e) the instruction
after the branch is not fetched till the branch instruction is completed. Under ideal condition.
Calculate the average instruction execution time assuming that 20% of all instruction
executed are branch instructions. Ignore the fact that some branch instructions maybe be
conditional.
6. (i) What is hazard? Give hazard free realization for the following boolean function
F(A, B, C, D) = ∑m(1,5,6,7) using AND-OR gate network
(ii) Define essential hazards.
7. (i) Outline a control unit with a diagram and state the functions performed by a control unit.
(ii) Outline the difference between hardwired control and microprogrammed control.
8. What are pipeline hazards? Outline the types of pipeline hazards.
 UNIT-5

(2-marks)
1. What is hit time?
2. What is a direct-mapped cache?
3. Why do we need cache memory?
4. Which signal is used to notify the processor that the transfer is completed?Define.
5. What is memory hierarchy?
6. Differentiate write back and write through.
7. Can a computer work without cache? Justify.
8. What is the purpose of SATA?

(13-marks)
1. Present an outline of virtual address, physical address, address translation, segmentation,
page table, swap space and page fault.
2. (i) Present an outline of interrupt driven I/O
(ii) Outline direct memory access with a diagram.
3. (i) Explain in detail about DMA operation
(ii) Give the modes of DMA transfer.
4. Elucidate interconnection standards.
5. Explain how memory mapping techniques are useful for finding the memory blocks in
cache?
6. How virtual addresses are translate into physical addresses? Explain it with the help of
virtual memory organization and page translation.
7. Explain in detail the memory hierarchy with neat diagram.
8. Explain in detail about Direct Memory Access (DMA) with neat diagram.