ntroduction:

PIC is a family of microcontrollers made by Microchip Technology. The original one was the PIC1650 developed
by General Instruments. This device was called PIC for “Programmable Intelligent Computer” although it is now
associated with “Programmable Interface Controller.” Microchip does not use PIC as an acronym. Instead they
prefer the brand name PICmicro. Popular wisdom relates that PIC is a registered brand in Germany and Microchip
is unable to use it internationally.
Overview of PIC Microcontroller:
 PICs use an instruction set that varies in length from about 35 instructions for the low-end PICs to more
than 70 for the high-end devices.
 The accumulator, which is known as the work register in PIC documentation, is part of many instructions
since the PIC contains no other internal registers accessible to the programmer.
 The PICs are programmable in their native Assembly Language, which is straightforward and not difficult
to learn. In addition, C language and BASIC compilers have been developed for the PIC.
 Open-source Pascal, JAL, and Forth compilers are also available for PIC programming.

ALL PIC Microcontrollers offer the following features:

 RISC instruction set with only a handful of instructions to learn.
 Digital I/O ports.
 On-Chip timer with 8-bit prescalar.
 Power-on reset
 Watch dog Timer.
 Power-saving Sleep Mode.
 High Source and Sink Current.
 Direct, indirect and Relative addressing modes.
 External Clock Interface.
 RAM data Memory
 EPROM or Flash Program Memory.

Other additional Features which are offered are:

 Analog input Channels.
 Analog comparators.
 Additional timer Circuits.

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 EEPROM data Memory.
 External and internal interrupts.
 Internal Oscillator.
Clock / instruction cycle

Introduction:
Clock is microcontroller's main starter, and is obtained from an external component called an "oscillator".
Overview of Clock /Instruction cycle:
 If we want to compare a microcontroller with a time clock, our "clock" would then be a ticking sound we
hear from the time clock.
 In that case, oscillator could be compared to a spring that is wound so time clock can run
 Also, force used to wind the time clock can be compared to an electrical supply.
 Clock from the oscillator enters a microcontroller via OSC1 pin where internal circuit of a microcontroller
divides the clock into four even clocks Q1, Q2, Q3, and Q4 which do not overlap.
 These four clocks make up one instruction cycle (also called machine cycle) during which one instruction
is executed.
 Execution of instruction starts by calling an instruction that is next in string. Instruction is called from
program memory on every Q1 and is written in instruction register on Q4.
 Decoding and execution of instruction are done between the next Q1 and Q4 cycles.
 On the following diagram we can see the relationship between instruction cycle and clock of the oscillator
(OSC1) as well as that of internal clocks Q1-Q4.
 Program counter (PC) holds information about the address of the next instruction.

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Pipelining

Introduction:
With Pipelining, each instruction is effectively executed in one cycle. The following section briefly explains the
pipelining in microcontrollers.
Overview of Pipelining:
 Instruction cycle consists of cycles Q1, Q2, Q3 and Q4.
 Cycles of calling and executing instructions are connected in such a way that in order to make a call, one
instruction cycle is needed, and one more is needed for decoding and execution.
 However, due to pipelining, each instruction is effectively executed in one cycle.
 If instruction causes a change on program counter, and PC doesn't point to the following but to some other
address (which can be the case with jumps or with calling subprograms), two cycles are needed for executing an
instruction.
 This is so because instruction must be processed again, but this time from the right address.
 Cycle of calling begins with Q1 clock, by writing into instruction register (IR).
 Decoding and executing begins with Q2, Q3 and Q4 clocks

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Mid-range I/O and Peripheral Modules

Introduction:
Mid-range devices contain special modules to implement peripheral and I/O functions. The more complex the
device the more peripheral modules are likely to be present. Following sections describe the architecture of the most
common peripheral modules.
Peripheral modules:
 A simple mid-range PIC like the 16F84A contains few peripheral modules, specifically, EEPROM data
memory, I/O ports, and a timer module.
 The 16F87x PICs, on the other hand, in addition to I/O ports, EEPROM, and three individual timers, have
a parallel slave port, a WPM (capture and compare) module, an MSSP (master synchronous serial port) module, a
USART (universal asynchronous/synchronous receiver and transmitter) module, and an A/D (analog-to-digital
converter) module.
 Other members of the mid-range family have additional or different peripheral and I/O modules.
 In the
 Implementation of many different functions in a device with a small footprint requires multiplexing many
of the PIC’s access connections.
 Figure shows the pin out of the 16F84A and the 16F877 and the multiple functions of most pins in both
devices.

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Figure 16F84A and 16F877 Pin Diagrams

PIC Architecture

Introduction:
PIC controllers are roughly classified by Microchip into three groups: baseline, mid-range, and high-performance.
Within each of the groups the PICs are classified based on the first two digits of the PIC’s family type. PICs with
16X designations belong to the baseline family and others that belong to the mid-range group. In the following
subsections we describe the basic characteristics of the various subgroups of the three major PIC families with 8-
bit architectures.
 Baseline PIC Family:
 This group includes members of the PIC10, PIC12, and PIC16 families.
 The devices in the Baseline group have 12-bit program words and are supplied in 6- to 28-pin packages.
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 The microcontrollers in the baseline group are described as being suited for battery- operated applications
since they have low power requirements.
 The typical member of the Baseline group has a low pin count, flash program memory, and low power
requirements. The following types are in the Baseline group.
PIC10 Devices:
 The PIC10 devices are low-cost, 8-bit, flash-based CMOS microcontrollers.
 They use 33 single-words, single-cycle instructions (except for program branches, which take two cycles).
 The instructions are 12-bits wide.
 The PIC10 devices feature power-on reset, an internal oscillator mode that saves having to use ports for an
external oscillator.
 They have a power-saving SLEEP mode, a Watchdog Timer, and optional code protection.
 The recommended applications of the PIC10 family range from personal care appliances and security
systems to low-power remote transmitters and receivers.
 The PICs of this family have a small footprint and are manufactured in formats suitable for both through-
hole and surface mount technologies.
 Following Table summarizes the characteristics of PIC10 devices.

Characteristics of the PIC

Introduction:
PIC microcontrollers are unique in many ways. We start by mentioning several general characteristics of the PIC:
Harvard architecture, RISC processor design, single-word instructions, machine and data memory configuration,
and characteristic instruction formats.
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Harvard Architecture:
 The PIC microcontrollers do not use the conventional von Neumann architecture but a different hardware
design often referred to as Harvard architecture.
 Originally, Harvard architecture referred to a computer design in which data and instruction used different
signal paths and storage areas.
 In other words, data and instructions are not located in the same memory area but in separate ones.
 In a machine with Harvard architecture, on the other hand, the processor can read and write instructions
and data to and from memory at the same time.
 This results in a faster, albeit more complex, machine. Figure 8-1 shows the program and data memory space
in a mid-range PIC.

 Several generations of microcontrollers, including the Microchip PICs, have been based on the Harvard
architecture.
 These processors have separate storage for program and data and a reduced instruction set. The midranges
PICs, in particular, have 8-bit data words but either 12-, 14-, or 16-bit program instructions.
 Since the instruction size is much wider than the data size, an instruction can contain a full-size data
constant.
Core Features

Introduction:
Core features refer to the device oscillator, reset mechanism, CPU architecture and operation, Arithmetic-Logic
Unit, memory organization, interrupts, and instruction set. The following section describes the device
oscillator, System Reset features.
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Oscillator:
 Mid-range PICs require an external device to produce the clock cycles required for its operation.
 The PIC executes an instruction every four clock cycles, so the oscillator speed determines the device
performance.

Oscillator Modes:
 Mid-range PICs support up to eight different oscillator modes.
 In the 16F877, any of the eight modes can be used, while in the 16F84 only four oscillator modes are
available.
 The oscillator mode is selected at device programming time and cannot be changed at runtime.
 The configuration bits, which are non-volatile flags set during device programming, determine which
oscillator mode is used by the program, among the following:
1. LP Low Frequency Crystal
2. XT Crystal Resonator
3. HS High Speed Crystal Resonator
4. RC External Resistor/Capacitor
5. EXTRC External Resistor/Capacitor
6. EXTRC External Resistor/Capacitor with CLKOUT
7. INTRC Internal 4 MHz Resistor/Capacitor
8. INTRC Internal 4 MHz Resistor/Capacitor with CLKOUT
 The resistor/capacitor oscillator option is the least expensive to implement, but also the least accurate
one.
 The low-power frequency crystal option is the one with lowest power consumption and can be used in
systems where the power consumption element is important.
 The first three oscillator modes (LP, XT, and HS) allow selecting different frequency ranges.
 The HS option has the highest frequency range and consumes the most power.
 The XT option is based on a standard crystal resonator and has a mid-range power consumption.
 The LP option has low gain and consumes the least power of the three crystal modes.
 The RC mode with EXTRC and CLKOUT features has the same functionality as the straight RC oscillator
option.
PIC 16F877 Pin Out

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Introduction:
The chip can be obtained in different packages, such as conventional 40-pin DIP (Dual In-Line Package),
square surface mount or socket format. The following section gives a Pin out Diagram for mid-range PIC
microcontroller
DIP Version:
 The DIP version is recommended for prototyping, and is shown in following Figure.
 Most of the pins are for input and output, and arranged as 5 ports: A (5), B (8), C (8), D (8) and E (3), giving
a total of 32 I/O pins.
 These can all operate as simple digital I/O pins, but most have more than one function, and the mode of
operation of each is selected by initializing various control registers within the chip.
 In particular, that Ports A and E become ANALOGUE INPUTS by default (on power up or reset), so they
have to set up for digital I/O if required.
 Port B is used for downloading the program to the chip flash ROM (RB6 and RB7), and RB0 and RB4–
RB7 can generate an interrupt.
 Port C gives access to timers and serial ports, while Port D can be used as a slave port, with Port
E providing the control pins for this function. All these options will be explained in detail later.

Figure 1 PIC 16F877 pin out

 The chip has two pairs of power pins (VDD= 5 V nominal and Vss = 0 V), and either pair can be used.
 The chip can actually work down to about 2 V supplies, for battery and power-saving operation.
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 A low-frequency clock circuit using only a capacitor and resistor to set the frequency can be connected
to CLKIN, or a crystal oscillator circuit can be connected across CLKIN and CLKOUT.
 MCLR is the reset input; when cleared to 0, the MCU stops, and restarts when MCLR = 1.
 This input must be tied high allowing the chip to run if an external reset circuit is not connected, but it is
usually a good idea to incorporate a manual reset button in all but the most trivial applications.
PICMicrocontroller Block Diagram

Introduction:
The following Section gives a block Diagram for PIC 16F877 which emphasize the Program execution mechanism.
Overview of the Block Diagram:
 A somewhat simplified version is given in following Figure, which emphasizes the program execution
mechanism.
 The main program memory is flash ROM, which stores a list of 14-bits instructions.
 These are fed to the execution unit, and used to modify the RAM file registers.
 These include special control registers, the port registers and a set of general purpose registers which can be
used to store data temporarily.
 A separate working register (W) is used with the ALU (Arithmetic Logic Unit) to process data. Various
special peripheral modules provide a range of I/O options
 There are 512 RAM File Register addresses (0–1FFh), which are organized in 4 banks (0–3), each bank
containing 128 addresses.

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I/O Ports

Introduction:
The following Section Explains the ports for Mid-Range PIC microcontroller PIC 16F877.
Ports:
 There are five parallel ports in the PIC 16F877, labeled A–E.
 All pins can be used as bit- or byte-oriented digital input or output.
 Their alternate functions are summarized in below Table.
 Many of the port pins have two or more functions, depending on the initialization of the relevant control
registers.
 On power up or reset, the port control register bits adopt a default condition.
 The TRIS (data direction) register bits in bank 1 default to 1, setting the ports B, C and D as inputs
 If this is as required, no further initialization is needed, since other relevant control registers are generally
reset to provide plain digital I/O by default.

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 Ports A and E are set to ANALOGUE INPUT by default, because the analogue control register ADCON1
in bank 1 defaults to 0 - - - 0000.
 To set up these ports for digital I/O, this register must be loaded with the code x - - - 011x (x don’t care),
say 06h.
 If analogue input is required only on selected pins, ADCON1 can be initialized with bit codes that give a
mixture of analogue and digital I/O on Ports A and E.
 Note that ADCON1 is in bank 1 so BANKSEL is needed to access it.

Figure 2 Port alternate functions

Register File Map

Introduction:
The following section will give the Register file map for the PIC microcontroller.

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CPU registers PIC

13
Introduction:
The following section will explain the registers commonly used by the PIC CPU.
Working Register:
 W, the working register, is used by many instructions as the source of an operand.
 This is similar to accumulator in 8051.
 It may also serve as the destination for the result of the instruction execution.
 It is an 8 - bit register.

STATUS Register:
 The STATUS register is an 8-bit register that stores the status of the processor. This also stores carry, zero
and digit carry bits.
STATUS - address 03H, 83H.

C = Carry bit
DC = Digit carry (same as auxiliary carry)
Z = Zero bit
NOT_TO and NOT_PD - Used in conjunction with PIC's sleep mode
RP0- Register bank select bit used in conjunction with direct addressing mode.
FSR Register
(File Selection Register, address = 04H, 84H)
FSR is an 8-bit register used as data memory address pointer. This is used in indirect addressing mode.
INDF Register
(INDirect through FSR, address = 00H, 80H)
INDF is not a physical register. Accessing INDF access is the location pointed to by FSR in indirect addressing
mode.
PCL Register
(Program Counter Low Byte, address = 02H, 82H)
PCL is actually the lower 8-bits of the 13-bit program counter. This is a both readable and writable register.

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STATUS and OPTION Registers

Introduction:
The STATUS register is one of the SFRs in the mid-range PICs. The bits in this register reflect the arithmetic status
of the ALU, the RESET status, and the bits that select which memory bank is currently being accessed. Because the
bank selection bits are in the STATUS register it must be present and at the same relative position in every bank.
 STATUS REGISTER:
Following Figure is a bitmap of the STATUS register.

bit 7 IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (0x100 - 0x1ff)
0 = Bank 0, 1 (0x000 - 0xff)
For devices with only Bank0 and Bank1 the IRP bit is reserved, always
maintain this bit clear.
Bit 6:5 RP1:RP0:
Register Bank Select bits (used for directaddressing)
11 = Bank 3 (0x180 - 0x1ff)
10 = Bank 2 (0x100 - 0xx17f)
01 = Bank 1 (0x80 - 0xff)
00 = Bank 0 (0x00 - 0x7f)
Each bank is 128 bytes. For devices with only Bank0 and Bank1 the IRP bit is reserved, always maintain this bit
clear.
Bit 4 TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
Bit 3 PD Power-down bit
1 = After power-up or by the CLRWDT instruction
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 0 = By execution of the SLEEP instruction
Bit2 Z: Zero bit
1 = The result of an operation is zero
0 = The result of an operation is not zero
Registers Used for Interrupts
 INTCON
 OPTION_REG
 PIE1
 PIR1
 PIE2
 PIR2
INTCON Register
The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0
register overflow, RB port change and external RB0/INT pin interrupt.

GIE: Global Interrupt Enable bit

1-Enables all unmasked interrupts
0-Disables all interrupts
PIE: Peripheral Interrupt Enable bit
1-Enables all unmasked peripheral interrupts
0-Disables all peripheral interrupts
TMR0IE: TMR0 Overflow Interrupt Enable bit
1-Enables the TMR0 interrupt
0-Disables the TMR0 interrupt
INTE: RB0/INT External Interrupt Enable bit
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1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
TMR0IF: TMR0 Overflow Interrupt Flag bit
1-TMR0 register has overflowed (must be cleared in software)
0-TMR0 register did not overflow
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state; a mismatch condition will continue to set the bit. Reading
PORTB will end the mismatch condition and allow the bit to be cleared (must be cleared in software).
0 = None of the RB7:RB4 pins have changed state
OPTION_REG Register
The OPTION_REG Register is a readable and writable register, which contains various control bits to configure
the TMR0 Prescaler/WDT Postscaler (single assignable register known also as the Prescaler), the external INT
interrupt, TMR0, and the weak pull-ups on PORTB.

RBPU: PORTB Pull-up Enable bit (This bit is not used for timers)
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
INTEDG Interrupt Edge Select bit
1 = Interrupt on the rising edge of RB0/INT pin
0 = Interrupt on the falling edge of RB0/INT pin
T0CS: TMR0 Clock Source Select bit
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1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
PS2:PS0: Prescaler Rate Select bits

Note: There is only one Prescaler available which is mutually exclusively shared between the Timer0 module and
the Watchdog Timer. A Prescaler assignment for the Timer0 module means that there is no Prescaler for the
Watchdog Timer and vice versa. This Prescaler is not accessible but can be configured using PS2:PS0 bits
of OPTION_REG.
PIE1 Register
The PIE1 register contains the individual enable bits for the peripheral interrupts.

PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit(1)

1 = Enables the PSP to read/write interrupt
0 = Disables the PSP read/write interrupt
Note (1): PSPIE is reserved on PIC16F873A/876A devices; always maintain this bit clear.
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
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RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART to receive interrupt
0 = Disables the USART receive interrupt
TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART to transmit interrupt
0 = Disables the USART transmit interrupt
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIR1 Register
The PIR1 register contains the individual flag bits for the peripheral interrupts.
Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable
bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear
prior to enabling an interrupt.

PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit(1)

1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
Note (1): PSPIF is reserved on PIC16F873A/876A devices; always maintain this bit clear.
ADIF: A/D Converter Interrupt Flag bit
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1 = An A/D conversion completed
0 = The A/D conversion is not complete
RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
CCP1IF: CCP1 Interrupt Flag bit
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
PIE2 Register
The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision
interrupts, EEPROM writes operation interrupt, and the comparator interrupt.

CMIE: Comparator Interrupt Enable bit

1 = Enables the comparator interrupt
0 = Disable the comparator interrupt
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EEPROM write interrupt
0 = Disable EEPROM write interrupt
BCLIE: Bus Collision Interrupt Enable bit
1 = Enable bus collision interrupt
0 = Disable bus collision interrupt
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CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIR2 Register
The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt, the EEPROM write
operation interrupt, and the comparator interrupt.

CMIF: Comparator Interrupt Flag bit

1 = The comparator input has changed (must be cleared in software)
0 = The comparator input has not changed
EEIF: EEPROM Write Operation Interrupt Flag bit
1 = The write operation completed (must be cleared in software)
0 = The write operation is not complete or has not been started
BCLIF: Bus Collision Interrupt Flag bit
1 = A bus collision has occurred in the SSP when configured for I2C Master mode
0 = No bus collision has occurred
CCP2IF: CCP2 Interrupt Flag bit
A/D Registers

Introduction:
Analog-to-digital registers are used specifically to control the A/D ports. On most A/D equipped PICs, the A/D
ports will be included on Port A only. Some of the larger PICs also add more A/D ports by using Port E.
A/D structure:
The A/D structure in the PIC uses three registers for access and control: the “A/D control register 0” (ADCON0),
the “A/D control register 1” (ADCON1), and the “A/D result register” (ADRES). The ADCON0 register is really
more of a control register while ADCON1 is a setup register.

21
These two bits allow you to pick from four different clock sources. The clock signal is used in the sample and hold
A/D circuitry inside the PIC. The best choice is the internal RC oscillator since it runs independent of the external
crystal/ Resonator.
The other choices are for more precise measurements and require a lot of specific calculations—more calculations
than the average Pic Basic user will want to deal with.

The bit selections are:

00: External Oscillator / 2

01: External Oscillator / 8
10: External Oscillator / 32
11: Internal RC Oscillator

CHS2-0—Analog Channel Select

These bits choose which A/D port you want to read within your program. You will have to select this at the
beginning of your PBC A/D routine. PBPro automatically selects this when you use the ADCIN command.

CHS2-0 select as follows:

000: Channel 0 (A0 pin)

001: Channel 1 (A1 pin)
010: Channel 2 (A2 pin)
011: Channel 3 (A3 pin)
100: Channel 4 (A5 pin)
101: Channel 5 (E0 pin)
110: Channel 6 (E1 pin)

22
111: Channel 7 (E2 pin)
GO/DONE—A/D Conversion Status bit
This bit is really a control bit and an indicator flag. It is used to monitor when the A/D conversion is complete. It
allows your program to check A/D status. When it is set to a “1”, the A/D conversion process starts. This bit is
automatically cleared when the conversion is complete.
Data Memory Organization

Introduction:
The structure and organization of data memory in the PIC hardware also has some unique and interesting
features.The following section explain the different Register and Memory banks
The w Register
 PICs have only one addressable register called the work register or the w register.
The Data Registers
 PIC’s data memory consists of registers, also called file registers.
 These behave more like conventional variables, and can be addressed directly and indirectly.
 All data registers are 8-bits.
 Data registers come in two types: general purpose registers (GPRs) and special function registers
(SFRs).
Memory Banks
 The PIC instruction format devotes seven bits to the address field .
 A 7-bit address allows access to only 128 memory locations.
 Since many PICs of the mid-range family have more than 128 bytes of data memory, an addressing scheme
based on memory banks must be implemented.
 The memory banking mechanism adopted by the PICs is effective, although not very user-friendly.
 The number of banks varies according to the amount of available RAM, always in multiples of 128-bytes.
 All mid-range PICs have banked memory.
 Banking is accomplished through the special bank-select bits in the STATUS register.

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 Not all banking bits are implemented in all devices. For example, the 16F84/16F84A contain two memory
banks; therefore, bank shifting requires a single bank-select bit (RP0).
 In this case the RP1 bit is not implemented.
 In devices with more than two memory banks bank selection is as shown in Table above.

Figure 1 Memory Access in Direct Addressing

EEPROM Data Storage

Introduction:
EEPROM (pronounced double-e PROM or e-squared PROM) stands for electrically- erasable programmable read-
only memory. EEPROM is used in computers and digital devices as non-volatile storage.
Overview of EEPROM:
24
 EEPROM is not RAM, since RAM is volatile and EEPROM retains its data after power is removed.
 EEPROM is found in USB flash drives and in the non-volatile storage of several microcontrollers, including
many PICs.
 One advantage of EEPROM is that it can be erased and written electrically, without removing the chip.
 The predecessor technology, named EPROM, required that the chip be removed from the circuit and placed
under ultraviolet light.
 EEPROM simplifies the erasing and re-writing process.
 EEPROM data memory refers to both on-board EEPROM memory and to EEPROM memory ICs as separate
circuit components. In general, EEPROM elements are classified according to their electrical interfaces into serial
and parallel. Most EEPROM memories used in PICs are serial EEPROMs, also called SEEPROMs.
 The typical use of serial EEPROM on-board memory and EEPROM on ICs is in the storage of passwords,
codes, configuration settings, and other information to be remembered after the system is turned off.
 For example, a PIC-based security system can use EEPROM memory to store the system password.
 Since EEPROM can be written, the user can change this password and the new one will also be remembered.

EEPROM in Mid-Range PICs

 The mid-range PICs is equipped with EEPROM memory in three possible sizes: 64 bytes, 128 bytes, and
256 bytes. EEPROM memory allows read and write operations.
 This memory is not mapped into the processor’s data or program area, but in a separate block that is
addressed through some SFRs. The registers related to EEPROM operations are:
1. EECON1
2. EECON2 (not a physically implemented register)
3. EEDATA
4. EEADR
 EECON1 contains the control bits, and EECON2 is used to initiate the EEPROM read and write operations.
 The 8-bit data item to be written must first be stored in the EEDATA register, while the address of the
location in EEPROM memory is stored in the EEADR register.
 The EEPROM address space always starts at 0x00 and extends linearly to maximum in the device.
 When a write operation is performed, the contents of the EEPROM location are automatically erased.
 The EEPROM memory used in PICs is rated for high erase/write cycles.
Addressing modes

25
Introduction:
RAM memory locations can be accessed directly or indirectly.
Direct Addressing
 Direct Addressing is done through a 9-bit address.
 This address is obtained by connecting 7th bit of direct address of an instruction with two bits (RP1, RP0)
from STATUS register as is shown on the following picture.
 Any access to SFR registers can be an example of direct addressing.

Bsf STATUS, RP0 ; Bankl

movlw 0xFF ; w=0xFF
movwf TRISA ; address of TRISA register is taken from
; instruction movwf

Indirect Addressing

Introduction:
26
The following section explains the indirect addressing in PIC microcontroller in brief.

Mechanism for accessing Operands:

The instruction set of most processors, including the PICs, provides a mechanism for accessing memory operands
indirectly. Indirect addressing is based on the following capabilities:
1. The address of a memory operand is loaded into a register. This register is called the pointer.
2. The pointer register is then used to indirectly access the memory location at the address it “points to.”
3. The value in the pointer register can be modified (usually incremented or decremented) so as to allow access to
other memory operands.

Indirect Addressing:
In the PIC architecture indirect addressing is implemented using two registers:
 INDF and FSR.
 The INDF register, always located at memory address 0x00 and mirrored in all banks, is not a physical
register, in the sense that it cannot be directly accessed by code.
 The FSR register is the pointer register that is initialized to the address of a memory operand.
 Once a memory address is placed in FSR, any action on the INDF register takes place at the memory location
pointed at by FSR.
 For example, if the FSR register is initialized to memory address 0x20, then clearing the INDF register has
the effect of clearing the memory location at address 0x20
 In other words, the action on the INDF register actually takes place at the address contained in the FSR
register.
 Now, if FSR (the pointer register) is incremented and INDF is again cleared, the memory location at address
0x21 is cleared.
Chip Configuration Word

Introduction:
Chip Configuration Word sets up aspects of the chip operation which cannot be subsequently changed without
reprogramming.
Functions of Chip Configuration Word:
 A special area of program memory outside the normal range (address 2007h) stores a chip configuration
word; the clock type, and other MCU options, is set by loading the configuration bits with a suitable binary code.

27
 The function of each bit is shown in the following Table, along with some typical configuration settings.

PIC Microcontroller options

Introduction:
The following section explains the other PIC microcontroller Options which can be setup by loading configuration
bits.
CODE PROTECTION:
 Normally, the program machine code can be read back to the programming host computer, be disassembled
and the original source program recovered.
 This can be prevented if commercial or security considerations require it.
 The code protection bits (CP1:CP0) disable reads from selected program areas
 Program memory may also be written from within the program itself, so that data tables or error checking
data can be modified.
 Data EEPROM may also be protected from external reads in the same way via the CPD bit, while internal
read and write operations are still allowed, regardless of the state-of-the code protection bits.
IN-CIRCUIT DEBUGGING
 In-circuit debugging (ICD) allows the program to be downloaded after the chip has been fitted in the
application circuit, and allows it to be tested with the real hardware.
28
 This is more useful than the previous method, which requires the chip to be programmed in a separate
programmer unit before insertion in its socket on the board.
 With ICD, the chip can be programmed, and reprogrammed during debugging, while avoiding possible
electrical and mechanical damage caused by removal from the circuit.
 The normal debugging techniques of single stepping, breakpoints and tracing can be applied in ICD mode.
 This allows a final stage of debugging in the prototype hardware, where problems with the interaction of the
MCU with the real hardware can be resolved.
LOW VOLTAGE PROGRAMMING
 Normally, when the chip is programmed, a high voltage (12–14 V) is applied to the PGM pin (RB3).
 To avoid the need to supply this voltage during in-circuit programming (e.g. during remote reprogramming),
a low-voltage programming mode is available; however, using this option means that RB3 is not then available for
general I/O functions during normal operation.
POWER-UP TIMER
 When the supply power is applied to the programmed MCU, the start of program execution should be
delayed until the power supply and clock are stable, otherwise the program may not run correctly.
 The power-up timer may therefore be enabled (PWRTE 0) as a matter of routine.
 It avoids the need to reset the MCU manually at start up, or connect an external reset circuit, as is necessary
with some microprocessors.
 An internal oscillator provides a delay between the power coming on and an internal MCU reset of about
72 ms.
 This is followed by an oscillator start up delay of 1024 cycles of the clock before program execution starts.
 At a clock frequency of 4 MHz, this works out to 256 μs.
BROWN-OUT RESET
 Brown out refers to a short dip in the power-supply voltage, caused by mains supply fluctuation, or some
other supply fault, which might disrupt the program execution.
 If the Brown-Out Detect Enable bit (BODEN) is set, a PSU glitch of longer than about 100 μs will cause
the device to be held in reset until the supply recovers, and then wait for the power-up timer to time out, before
restarting.
 The program must be designed to recover automatically.
PIC Instruction Set

Introduction:

29
Each microcontroller family has its own set of instructions, which carry out essentially the same set of operations,
but using different syntax. The PIC uses a minimal set of instructions, which makes it a good choice for learning.
Instruction Set for PIC Microcontroller:
 A version of the PIC instruction set organized by functional groups is listed in the following Table.
 It consists of 35 separate instructions, some with alternate result destinations.
 The default destination for the result of an operation is the file register, but the working register W is
sometimes an option.

Instruction Set Illustrations

1. ANDLW Logic AND W with constant:

30
12.ANDWF Logic AND W with f:

Interrupts

31
Introduction:
The interrupt works like a “tap on the shoulder” on the microcontroller, calling its attention to an event that requires
an action or device that needs servicing. After responding to or ignoring the interrupt, the CPU resumes processing
where it left off. In computer technologies the interrupt mechanism is a complicated hardware/ software system that
often includes programmable interrupt controller ICs. Processors and microprocessors usually support hardware
and software interrupts and maskable and non-maskable interrupts; interrupts originate in practically any device
connected to the system.
PIC and Interrupts:
 In the PICs, the interrupt mechanism is much simpler and varies considerably even among members of the
same PIC family. All PICs of the mid-range family to some degree support interrupts.
 The interrupt source usually originates in one of the hardware modules, although some sources generate
more than one interrupt.
Interrupt Supported by PIC microcontroller:
The following are interrupt sources in the mid-range family, although not all are supported by every PIC.
INT Pin Interrupt (external interrupt)
• TMR0 Overflow Interrupt
• PORTB Change Interrupt
• Comparator Change Interrupt
• Parallel Slave Port Interrupt
• USART Interrupts
• Receive and Transmit Interrupt
• A/D Conversion Complete Interrupt
• LCD Interrupt
• Data EEPROM Write Complete Interrupt
• Timer Overflow Interrupt
• CCP Interrupt
• SSP Interrupt
Several SFRs are related to the interrupt systems. The INTCON register provides interrupt enabling and control and
the PIE1, PIE2, PIR1, and PIR2 registers have specific device-related functions.
Timers

Introduction:

32
The following section explain the Timer for PIC microcontroller PIC 16F877.
PIC 16F877 TIMERS:
 The PIC 16F877 has three hardware timers.
 These are used to carry out timing operations simultaneously with the program, to make the program faster
and more efficient.
 An example would be generating a pulse every second at an output.
 Timer0 uses an 8-bit register, TMR0, file register address 01.
 Its output is an overflow flag, T0IF, bit 2 in the Interrupt Control Register INTCON, address 0B.
 The timer register is incremented via a clock input which is derived either from the MCU oscillator (f OSC)
or an external pulse train at RA4.
 The register counts from 0 to 255d in binary, and then rolls over to 00 again. When the register goes from
FF to 00, T0IF is set. If the internal clock is used, the register acts as a timer.
 Each instruction in the MCU takes four clock cycles to execute, so the instruction clock is fOSC/4.
 The timers are driven from the instruction clock, which can be monitored externally at CLKOUT, if the chip
is operating with an RC clock.
 If preloaded with a value of say, 155d, TMR0 will count 100 clock pulses until T0IF is set.
 If the chip is driven from a crystal of 4 MHz, the instruction clock will be 1 MHz, and the timer will
overflow after 100 usec.
 If this were used to toggle an output, a signal with a period of exactly 2* 100= 200 usec (frequency = 5
kHz) would be obtained.
 Alternatively, a count of external pulses can be made, and read from the register when finished, or the read
triggered by external signal.
 Thus, the timers can also be used as counters.
 Figure in the data sheet shows the full block diagram of Timer0, which shows a pre-scale register and the
watchdog timer.
 The pre-scaler is a divide by N register, where N 2, 4, 8, 16, 32, 64, 128 or 256, meaning that the output
count rate is reduced by this factor.
 This extends the count period or total count by the same ratio, giving a greater range to the measurement.
The watchdog timer interval can also be extended, if this is selected as the clock source.
 The pre-scale select bits and other control bits for Timer0 are found in OPTION_REG. Some typical Timer0
configurations are detailed in following table.
 Timer1 is a 16-bit counter, consisting of TMR1H and TMR1L (0E AND 0F).

33
 When the low byte rolls over from FF to 00, the high byte is incremented.
 The maximum count is therefore 65535d, which allows a higher count without sacrificing accuracy.
 Timer2 is an 8-bit counter (TMR2) with a 4-bit pre-scaler, 4-bit post-scaler and a comparator.
 It can be used to generate Pulse Width Modulated (PWM) output which is useful for driving DC motors
and servos, among other things.
 These timers can also be used in capture and compare modes, which allow external signals to be more easily
measured.
 There will be further detail provided with demonstration programs on timed I/O.
TIMER0 MODULE

Introduction:
The following section explains the TIMER-0 MODULE in details.
Features of TIMER 0:
The Timer0 module timer/counter has the following features:
 8-bit timer/counter
 Readable and writable
 8-bit software programmable prescaler
 Internal or external clock select
 Interrupt on overflow from FFh to 00h
 Edge select for external clock
 Figure is a block diagram of the Timer0 module and the prescaler shared with the WDT.
 Timer mode is selected by clearing bit T0CS (OPTION_REG<5>).
 In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler).
 If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
 The user can work around this by writing an adjusted value to the TMR0 register.
 Counter mode is selected by setting bit T0CS (OPTION_REG<5>).
 In Counter mode, Timer0 will increment either on every rising, or falling edge of pin RA4/T0CKI.
 The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>).
 Clearing bit T0SE selects the rising edge.
 The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer.
 The prescaler is not readable or writable.
Timer0 Interrupt:

34
 The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h.
 This overflow sets bit T0IF (INTCON<2>).
 The interrupt can be masked by clearing bit T0IE (INTCON<5>).
 Bit T0IF must be cleared in software by the Timer0 module Interrupt Service Routine before re-enabling
this interrupt.
 The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut-off during SLEEP.
Using Timer0 with an External Clock
 When no prescaler is used, the external clock input is the same as the prescaler output.
 The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler
output on the Q2 and Q4 cycles of the internal phase clocks.
 Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low
for at least 2Tosc (and a small RC delay of 20 ns).
Prescaler
 There is only one prescaler available, which is mutually exclusively shared between the Timer0 module and
the Watchdog Timer.
 A prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer,
and vice-versa.
 This prescaler is not readable or writable (see Figure).
 The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio.
 When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF
1, BSF 1,x....etc.) will clear the prescaler.
TIMER1 MODULE

Introduction:
The following section explains the TIMER-1 MODULE in details.
Features of TIMER 1:
 The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which
are readable and writable.
 The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h.
 The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF
(PIR1<0>).
 This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

35
 Timer1 can operate in one of two modes:
 As a timer
 As a counter
 The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).
 In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising
edge of the external clock input.
 Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>).
 Timer1 also has an internal “RESET input”.
 This RESET can be generated by either of the two CCP modules (Section 8.0). Register 6-1 shows the
Timer1 control register.
 When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI
pins become inputs.
 That is, the TRISC<1:0> value is ignored, and these pins read as ‘0’.

36
TIMER2 MODULE

Introduction:
The following section explains the TIMER2 MODULE in details.
Features of Timer 2 Module:
 Timer2 is an 8-bit timer with a prescaler, a postscaler, and a period register.
 Using the prescaler and postscaler at their maximum settings, the overflow time is the same as a 16-bit
timer.
 Timer2 is the PWM time-base when the CCP module(s) is used in the PWM mode.
 Figure shows a block diagram of Timer2.
 The postscaler counts the number of times that the TMR2 register matched the PR2 register. This can be
useful in reducing the overhead of the interrupt service routine on the CPU performance.

Figure Timer2 Block Diagram

Control Register
Following Register shows the Timer2 control register.
Register 13-1: T2CON: Timer2 Control Register

37
Bit 7 Unimplemented: Read as '0'
Bit 6:3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
•
•
•
1111 = 1:16 Postscale
ARM ARCHITECTURE

ARM Architecture- ARM Design Philosophy, Registers, Program Status Register, Instruction Pipeline, Interrupts
and Vector Table, Architecture Revision, ARM Processor Families.
1. History of the ARM Processor
 Developed the first ARM Processor (Acorn RISC Machine) in 1985 at AcornComputers Limited.
 Established a new company named Advanced RISC Machine Limited anddeveloped ARM6.
 Continuation of the architecture enhancements from the original architecture
2. Features of the ARM Processor
Incorporate features of Berkeley RISC design
 -a large register file
 -a load/store architecture
 -uniform and fixed length instruction field
 simple addressing mode
 Other ARM architecture features
 -Arithmetic Logic Unit and barrel shifter
 -auto increment and decrement addressing mode
 -conditional execution of instructions
 Based on Von Neumann Architecture or Harvard Architecture

38
3. he Evolution of the ARM architecture:

Figure 1.1 ARM Families

Architecture V1 was implemented only in the ARM1 CPU and was not utilized in a commercial product. Architecture V2
was the basis for the first shipped processors. These two architectures were developed by Acorn Computers before ARM
became a company in 1990.

After that introduced ARM the Architecture V3, which included many changes over its predecessors .These changes
resulted in an extremely small and power-efficient processor suitable for embedded systems .Architecture V4, co-
developed by ARM and Digital Electronics Corporation, resulted in the Strong ARM series of processors. These
processors are very performance-centric and do not include the on chip debug extensions.
This architecture was further developed to include the Thumb 16-bitinstruction set architecture enabling a 32-bit
processor to utilize a 16-bit system. Today, ARM only licenses cores based on Architecture V4T or above.
The latest architectures, version 5TE and 5TEJ, embody added instructions for DSP applications and the Jazelle-
Java extensions, respectively.
Currently, the ARM9E and 10E family of processors are theonly implementations of these architectures. Details
on these architectures and cores will be provided later in the course.

39
4. Architecture basics
ARM cores use a 32-bit, Load-Store RISC architecture. That means that the core cannot directly manipulate the
memory. All data manipulation must be done by loading registers with information located in memory, performing
the data operation and then storing the value back to memory. There are 37 total registers in the processor. However,
that number is split among sevendifferent processor modes. The seven processor modes are used to run user tasks,
an operating system, and to efficiently handle exceptions such as interrupts. Some of the registers with in each mode
are reserved for specific use by the core, while most are available for general use. The reserved registers that are
used by the core for specific functions are r13 is commonly used as thestack pointer (SP), r14 as a link register (LR),
r15as a program counter (PC), the Current ProgramStatus Register (CPSR), and the Saved Program Status Register
(SPSR).
The SPSR and the CPSR contain the status and control bits specific to the properties the processor core is operating
under. These properties define the operating mode, ALU status flags, interrupt disable/enable flags and whether the
core is operating in 32-bit ARM or 16-bit Thumb state.
There are 37 total registers divided among seven different processor modes. Figure 09 shows thebank of registers
visible in each mode .User mode, the only non-privileged mode, has the least number of total registers visible. It
has noSPSR and limited access to the CPSR. FIQ and IRQ are the two interrupt modes of the CPU

Figure 1.2 Different modes of ARM

There are 37 total registers divided among seven different processor modes. Figure 02 shows the bank of registers
visible in each mode. User mode, the only non-privileged mode, has the least number of total registers visible. It
has no SPSR and limited
40
access to the CPSR. FIQ and IRQ are the two interrupt modes of the CPU.Supervisor mode is the default mode of
the processor on start up or reset. Undefined mode traps unknown or illegal instructions when they are passed
through the pipeline. Abort mode traps illegal memory accesses as a result of fetching instructions or accessing
data.
Finally, system mode, which uses the user mode bank of registers, was introduced to provide an additional
privileged mode when dealing with nested interrupts.
Each additional mode offers unique registers that are available for use by exception handling routines. These
additional registers are the minimum number of registers required to preserve the state of the processor, save the
location in code, and switch between modes.
FIQ mode, however, has an additional five banked registers to provide more flexibility and higher performance
when handling critical interrupts.
When the ARM core is in Thumb state, the registers banks are split into low and high register domains. The majority
of instructions in Thumb state have a 3-bit register specifier. As a result, these instructions can only access the low
registers in Thumb, R0 through R7. The high registers,R8through R15, have more restricted use. Only a few
instructions have access to these registers.
TDMI
stands for:

• Thumb, which is a 16-bit instruction set extension to the 32-bit ARM architecture, referred asstates of
the processor.

• "D" and "I" together comprise the on-chip debug facilities offered on all ARM cores.Thesestand for
the Debug signals and EmbeddedICE logic, respectively.

• The M signifies the support for 64-bit results and an enhanced multiplier, resulting inhigherperformance.
This multiplier is now standard on all ARMv4 architectures and\above.
5. Thumb 16-bit Instructions
With growing code and data size, memory contributes to the system cost. The need to reduce memorycost leads to
smaller code size and the use of narrower memory. Therefore ARM developed a modified instruction set to give
market-leading code density for compiled standardC language.
There is also the problem of performance loss due to using a narrow memory path, suchas a 16-bitmemory path
with a 32-bit processor.

41
The processor must take two memory access cycles to fetch an instruction or read and write data. To address this issue,
ARM introduced another set of reduced 16-bit instructions labeled Thumb, based on the standard ARM 32-bit instruction
set.

For Thumb to be used, the processor must go through a change of state from ARM to Thumb in order to begin
executing 16-bit code. This is because the default state of the core is ARM. Therefore, every application must have
code at boot up that is written in ARM. If the application code is to be compiled entirely for Thumb, then the
segment of ARM boot code must change the state of the processor. Once this is done, 16-bit instructions are fetched
seamlessly into the pipeline without any result.
It is important to note that the architecture remains the same. The instruction set is actually a reduced set of the
ARM instruction set and only the instructions are 16-bit; everything else in the core still operates as 32-bit.An
application code compiled in Thumb is 30% smaller on average than the same code compiled in ARM and normally
30% faster when using narrow 16-bit memory systems.

Figure 1.3 Register Bank

Figure 1.3 shows the register bank in the center of the diagram, plus the required address bus and data bus. The
multiplier, in-line barrel shifter, and ALU are also shown. In addition, the diagram illustrates the in-line
decompression process of Thumb instructions while in the decode stage of the pipeline. This process creates a 32-
bit ARM equivalent instruction from the 16-bit Thumb instruction, decodes the instruction, and passes it on to the
execute stage.
42
6. ARM design philosophy
 Small processor for lower power consumption (for embedded system)
 High code density for limited memory and Physical size
restrictions
 The ability to use slow and low-costmemory
 Reduced die sizefor reducing manufacture cost and
accommodatingmore peripherals
6.1 Registers
ARM has 37 registers all of which are 32-bits long. 1 dedicated program counter 1 dedicated current program status
register 5 dedicated saved program status registers 30 general purposeregisters The current processor mode
governs which of several banks is accessible. Each mode can access a particular set of r0-r12 registers a
particular r13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc) the current
program status register, cpsr Privileged modes (except System) can also access a particular spsr (saved program
status reg
The ARM1136JF-S processor has a total of 37 registers:
31 general-purpose 32-bit registers,six 32-bit status registers. These registers are not all accessible at the same time.
The processor state and operating mode determine which registers are available to the programmer
The ARM state register set In ARM state, 16 general registers and one or two status registers are accessible at any
time. In privileged modes, mode-specific banked registers become available.
The ARM state register set contains 16 directly-accessible registers, r0-r15. Another register, the Current Program
Status Register (CPSR), contains condition code flags, status bits, and current mode bits. Registers r0-r13 are
general-purpose registers used to hold either data or address values. Registers r14, r15, and the SPSR have the
following special functions
Link Register Register r14 is used as the subroutine Link Register (LR). Register r14 receives the return address
when a Branch with Link (BL or BLX) instruction is executed. You can treat r14 as a general-purpose register at
all other times. The corresponding banked registers r14_svc, r14_irq, r14_fiq, r14_abt, and r14_und are similarly
used to hold the return values when interrupts and exceptions arise, or when BL or BLX instructions are executed
within interrupt or exception routines.

43
Program Counter Register r15 holds the PC:

• in ARM state this is word-aligned

• in Thumb state this ishalfword-aligned

• in Java state this is byte-aligned. Saved Program Status Register

In privileged modes, another register, the Saved Program Status Register (SPSR), is accessible. This contains the
condition code flags, status bits, and current mode bits saved as a result of the exception that caused entry to the
current mode.
Banked registers have a mode identifier that indicates which mode they relate to. These mode identifiers are listed
in Table Register mode identifiers

FIQ mode has seven banked registers mapped to r8–r14 (r8_fiq– r14_fiq). As a result many FIQhandlers do not
have to save any registers. The Supervisor, Abort, IRQ, and Undefined modes each have alternative mode-specific
registers mapped to r13 and r14, permitting a private stack pointer and link register for each mode.

44
Figure 1.4 register set showing banked registers

45
 Figure 1.5 ARM register
7. Thumb state register set
The Thumb state register set is a subset of the ARM state set. The programmer has direct accessto:

• Eight general registers, r0–r7

• The PC

• A stack pointer, SP (ARM r13)

• An LR (ARM r14)

• The CPSR.
There are banked SPs, LRs, and SPSRs for each privileged mode.

46
 Figure 1.6 THUMB register
7.1 Accessing high registers in Thumb state
In Thumb state, the high registers, r8–r15, are not part of the standard register set. You can use special variants of
the MOV instruction to transfer a value from a low register, in the range r0– r7, to a high register, and from a high
register to a low register. The CMP instruction enables youto compare high register values with low register values.
The ADD instruction enables you to add high register values to low register values.
.ARM state and Thumb state registers relationship
Figure1. 2-1.6 shows the relationships between the Thumb state and ARM state registers

47
Registers r0–r7 are known as the low registers. Registers r8–r15 areknown as the high registers.
7.2 The program status registers
program status registers:

• hold the condition code flags

• control the enabling and disabling of interrupts

• set the processor operating mode.

The arrangement of bits is shown in Figure

48
 Figure 1.7 program status registers
The condition code flags
The N, Z, C, and V bits are the condition code flags, You can set these bits by arithmeticand logical operations.
The flags can also be set by MSR and LDM instructions.
TheARM7TDMI-S tests these flags to determine whether to execute an instruction.
All instructions can execute conditionally in ARM state. In Thumb state, only the Branchinstruction can be
executed conditionally
7.3 The control bits
The bottom eight bits of a PSR are known collectively as thecontrol bits. They are the:

• Interrupt disable bits

• T bit

• Mode bits.
The control bits change when an exception occurs. When the processor is operating in aprivileged mode, software
can manipulate these bits.
7.4 Interrupt disable bits
The I and F bits are the interrupt disable bits:

• when the I bit is set, IRQ interrupts are disabled

• when the F bit is set, FIQ interrupts are disabled.

7.5 T bit
The T bit reflects the operating state:

• when the T bit is set, the processor is executing in Thumb state

• when the T bit is clear, the processor executing in ARMstate. The operating state isreflected by the
CPTBIT external signal.

49
7.6 Mode bits
The M4, M3, M2, M1, and M0 bits (M[4:0]) are the mode bits. These bits determine the processor operating mode
. Not all combinations of the mode bits define a valid processor mode, so take care to use only the bit combinations
shown
7.7 Reserved bits
The remaining bits in the PSRs are unused but are reserved. When changing a PSR flag or control bits make sure
that these reserved bits are not altered. Also, make sure that your program does not rely on reserved bits containing
specific values because future processors might have these bits set to one or zero
The ARM7TDMI-S is a member of the ARM family of general- purpose 32-bit microprocessors. The ARM family
offers high performance for very low power consumption and gate count. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles. The RISC instruction set, and related decode mechanism are
much simpler than those of Complex Instruction Set Computer (CISC) designs. This simplicity gives:
• a high Instruction throughput
• an excellent real-time interrupt response
• a small, cost-effective, processor macrocell.

8. The instruction pipeline

The ARM7TDMI-S uses a pipeline to increase the speed of the flow of instructions to the processor. This allows
several operations to take place simultaneously, and the processing, and memory systems to operate continuously.
A three-stage pipeline is used, so instructions are executed in three stages:

• Fetch

• Decode

• Execute.
The three-stage pipeline is shown in Figure .

50
8.1 The Program Counter (PC) points to the instruction being fetched rather than to the instruction being
executed.During normal operation, while one instruction is being executed, its successor is being decoded, and a third
instruction is being fetched from memory
9. The ARM Processor Families (I)

The ARM7 Family

32-bit RISC Processor. Support three-stage pipeline
Uses Von Neumann Architecture.

Figure 1.8 ARM7TDMI Figure 1.9 ARM7EJ-S

51
Widely used in many applications such as palmtop computers, portable instruments, smart card.
9.1 The ARM Processor Families (II)
The ARM9 Family
32-bit RISC Processor with ARM and Thumb instruction sets Supports five-stage pipelineUses harvard architecture

Uses Harvard architecture

ETM Mtsñae

ARM920T

Figure 1.10 ARM920T Processor Figure 1.11 ARM946E-S Processor

Characteristics of ARM9 Thumb Family

52
 Cache size(Inst/Data) Tightly Coupled Memory Mgmt Thumb DSP Jazelle
Wemoy

ARMD20T 6hl6k \1\1U Yes No No

ARMD22T 8W8f \1\1U Yes No No

Characteristics of ARM9E Family

Cache Tightly Memor y Thumb DSP Jazelle

size(Inst/ Coupled Mgmt
Data) Memory

ARI\1926EJ Variable Yes Yes Yes Yes

-S
ARL1946E-S Variable Yes MPU Yes Yes No

ARL1966E-S Yes Yes Yes No

ARL1968E— N.!a Yes DMA Yes Yes No

S
ARL1996H-S MPU Yes Yes No

Widely used in mobile phones, PDAs, digital cameras, automotive systems,industrial control systems.

9.2 ARM Processor Families (III)

The ARM10 Family
32-bit RISC processor with ARM, Thumb and DSP
instruction sets.
Supports six-stage Pipelines UsesHarvard Architecture

53
 Figure 1.11 ARM1020E Processor

Widely used in videophone, PDAs, set-top boxes, game console, digital video cameras, automotive and industrial
control systems.
9.4 ARM PROCESSOR FAMILIES (IV)
The ARM11 Family
32-bit RISC processor with ARM, Thumb and DSP instruction sets. Uses Harvard Architecture.
Supports eight-stage Pipelines except ARM1156T2 uses nine-stage
pipeline.
Widely used in automotive and industrial control systems, 3D graphics, security criticalapplications

54
10. Characteristics of ARM11 family
10.1 ARM Pipelines
Pipeline mechanism to increase execution speed
The pipeline design of each processor family is different
10.2 ARM Processor Modes
Unprivileged mode
User mode Privileged mode Abort modeFast Interrupt Request mode Interrupt Request mode Supervisor mode
System mode Undefined mode
10.3 Exceptions
Exceptions are taken whenever the normal flow of a program must temporarily halt, for example, to service an
interrupt from a peripheral. Before attempting to handle an exception, the processor preserves the critical parts of
the current processor state so that the original program can resume when the handler routine has finished
10.4 Exceptions and Interrupts
The ARM processor can work in one of many operating modes. So far we have only considereduser mode, which
is the "normal" mode of operation.
The processor can also enter "privileged" operating modeswhich are used to handle exceptions and SWIs
The Current Processor Status Register CPSR has 5 bits [bit4:0] to indicate which mode theprocessor is in:-

55
10.5 How are exceptions generated
By default, the processor is usually in user mode
It enters one of the exception modes when unexpected eventsoccur.
There are three different types of exceptions (some are called interrupts):-
 As a direct result of executing an instruction, suchas: Software Interrupt Instruction (SWI)
Undefined or illegal instruction
Memory error during fetching an instruction
 As a side-effect of an instruction, such as: Memory fault duringdata read/write frommemory
Arithmetic error (e.g. divide by zero)
 As a result of external hardware signals, such as: Reset Fast Interrupt (FIQ) Normal
Interrupt (IRQ)
10.6 Shadow Registers
As the processor enters an exception mode, some new registers are automatically switched in:- For example, an
external event (such as movement of the mouse) occurs that generates a
Fast Interrupt (on the FIQ pin), the processor enters FIQ operating mode. It sees the same r0 -r7 as before, but sees
a new set of r8 - r14, and in addition, an extra register called the Saved Processor Status Register (SPSR) stores the
value of the CPSR. By swapping to some new registers, it makes it easier for the programmer to preserve the state
of the processor.
For example, during FIQ mode, r8 - r14 can be used freely. On returning back to user mode, the original values of
r8 - r14 will be automatically restored.
10.7 What happens when an exception occurs
ARM completes current instruction as best it can. It departs from current instruction sequence to handle the
exception by performing the following steps:-

1. It changes the operating mode corresponding to the particular exception.

2. It saves the current PC in the r14 corresponding to the new mode. For example, if FIQoccurs,
the PC value is stored in r14(FIQ).

3. It saves the old value of CPSR in the Saved Processor Status Register of the new mode.

4. It disables exceptions of lower priority (to be considered later).

5. It forces the PC to a new value corresponding to the exception. This is effectively a forced jump to
the Exception Handler or Interrupt Service Routine.

56
10.8 Where is the exception handler routine
Exceptions can be viewed as "forced" subroutine calls. When and if an exception occurs is not predictable (unless
it is a SWI exception). A unique address is pre-defined for each exception handler (IRQ, FIQ, etc), and a branch is
made to this address. The address to which the processor is forced to branch to is called the exception/interrupt
vector.
10.9 Exception vector addresses
Each vector (except FIQ) is 4 bytes long (i.e. one instruction) You put a branch instruction at this address: B
exception handler FIQ is special in two ways:-

1. You can put the actual FIQ handler (also called Fast Interrupt Service Routine) at 0x0000001C
onwards, because FIQ vector occupies the highest address

2. FIQ has many more shadow registers. So you don‟t have to save as many registers on the stack as
other exceptions -faster.

10.10 Exception Return

Once the exception has been handled (by the exception handler),the user task is resumed.
The handler program (or Interrupt Service Routine) must restore the user state exactly as it was before the exception
occurred:

1. Anymodifieduserregisters must be restored from thehandlers stack

2. The CPSR must be restored from the appropriate SPSR

3. PC must be changed back to the instruction address in theuser instruction stream

Steps 1 and 3 are done by user, step 2 by the processor Restoring registers from the stack would be the same as in
the case of subroutine Restoring PC value is more complicated. The exact wayto do it
depends on which exception you are returning from.
10.11 Exception Return
Once the exception has been handled (by the exception handler), the user task is resumed. The handler program (or

57
Interrupt Service Routine) must restore the user state exactly as it was before the exception occurred
1. Any modified user registers must be restored from the handler‟s stack
2. The CPSR must be restored from the appropriate SPSR
.PC must be changed back to the instruction address in the user instruction stream Steps 1 and 3 are done by user, step 2
by the processor
Restoring registers from the stack would be the same as in the case of subroutines Restoring PC value is more
complicated. The exact way to do it depends on which exception you are returning from.
Remember that the return address was saved in r14 before entering the exception handler. To return from a SWI or
undefined instruction trap, use: MOVS pc, r14
To return from an IRQ, FIQ or prefetch abort, use: SUBS pc, r14, #4
To return from a data abort to retry the data access, use: SUBS pc, r14, #8 If the destinationregister is the PC,
the „S‟ modifier does NOT mean ―set the flags‖, but ―restore the CPSR‖
The differences between these three methods of return is due to the pipeline architecture of the ARM processor.
The PC value stored in r14 can be one or two instructions ahead due to the instruction prefetch pipeline.
10.12 Exception Priorities
Since exceptions can arise at the same time, a priority order has to be clearly defined. For theARM processor this
is:
Reset (highest priority)
Data abort (i.e. Memory fault in read/write data) Fast Interrupt Request (FIQ)
Normal Interrupt Request (IRQ) Prefetchabort
10.13 Software Interrupt (SWI), undefined instruction
Consider the case of a FIQ and an IRQ occurring at the same time. The processor will process the FIQ handler first
and ―remember‖ that there is IRQ pending. On return from FIQ, the process will immediately go to the IRQ handler.
11. Interrupts
The processor has two interrupt inputs, for normal interrupts (nIRQ) and fast interrupts (nFIQ). Each interrupt pin,
when asserted and not masked, causes the processor to take the appropriate type of interrupt exception..The CPSR.F
and CPSR.I bits control masking of fast and normal interrupts respectively.
A number of features exist to improve the interrupt latency, that is, the time taken between the assertion of the
interrupt input and the execution of the interrupt handler. By default, the processor uses the Low Interrupt Latency
(LIL) behaviors introduced in version 6

58
and later of the ARM architecture. The processor also has a port for connection of a Vectored
Interrupt Controller (VIC), and supports Non-Maskable Fast Interrupts (NMFI).
The following subsections describe interrupts:
 Interrupt request
 Fast interrupt request
 Non-maskable fast interrupts
 Low interrupt latency
 Interrupt controller.
11.1 Interrupt request
The IRQ exception is a normal interrupt caused by a LOW level on the nIRQ input. An IRQ
has a lower priority than an FIQ, and is masked on entry to an FIQ sequence. You must ensure
that the nIRQ input is held LOW until the processor acknowledges the interrupt request, either
from the VIC interface or the software handler.
Irrespective of whether the exception is taken from ARM state or Thumb state, an IRQ handler
returns from the interrupt by executing:
SUBS PC, R14_irq, #4 You can disable IRQ exceptions within a Privileged mode by setting
the CPSR.I bit to b1. See Program status registers. IRQ interrupts are automatically disabled
when an IRQ occurs, by setting the CPSR.I bit. You can use nested interrupts but it is up to
you to save any corruptible registers and to re-enable IRQs by clearing the CPSR.I bit.
11.2 Fast interrupt request
The Fast Interrupt Request (FIQ) reduces the execution time of the exception handler relative
to a normal interrupt. FIQ mode has eight private registers to reduce, or even remove the
requirement for register saving (minimizing the overhead of context switching).
An FIQ is externally generated by taking the nFIQ input signal LOW. You must ensure that
the nFIQ input is held LOW until the processor acknowledges the interrupt request from the
software handler.
Irrespective of whether exception entry is from ARM state or Thumb state, an FIQ handler
returns from the interrupt by executing:
SUBS PC, R14_fiq, #4 If Non-Maskable Fast Interrupts (NMFIs) are not enabled, you can
mask FIQ exceptions by setting the CPSR.F bit to b1. For more information see:
 Program status registers
 Non-maskable fast interrupts.
FIQ and IRQ interrupts are automatically masked by setting the CPSR.F and CPSR.I bits when 59

an FIQ occurs. You can use nested interrupts but it is up to you to save any corruptible registers
and to re-enable interrupts.

11.3 Non-maskable fast interrupts

When NMFI behavior is enabled, FIQ interrupts cannot be masked by software. Enabling
NMFI behavior ensures that when the FIQ mask, that is, the CPSR.F bit, is cleared by the reset
handler, fast interrupts are always taken as quickly as possible, except during handling of a fast
interrupt. This makes the fast interrupt suitable for signaling critical events. NMFI behavior is
controlled by a configuration input signal CFGNMFI, that is asserted HIGH to enable NMFI
operation. There is no software control of NMFI.
Software can detect whether NMFI operation is enabled by reading the NMFI bit of the SCTLR:
NMFI == 0
Software can mask FIQs by setting the CPSR.F bit to b1.
NMFI == 1
Software cannot mask FIQs.
For more information see c1, System Control Register. When the NMFI bit inthe SCTLR is b1:
 an instruction writing b0 to the CPSR.F bit clears it tob0
 an instruction writing b1 to the CPSR.F bit
leavesitunchanged
 the CPSR.F bit can be set to b1 only by an FIQ or reset exception entry.
11.4 Low interrupt latency
Low Interrupt Latency (LIL) is a set of behaviors that reduce the interrupt latency for the
processor, and is enabled by default. That is, the FI bit [21] in the SCTLR is Read-as-One.
LIL behavior enables accesses to Normal memory, including multiword accesses and external
accesses, to be abandoned part-way through execution so that the processor can react to a
pending interrupt faster than would otherwise be the case. When an instruction is abandoned
in this way, the processor behaves as if the instruction was not executed at all. If, after handling
the interrupt, the interrupt handler returns to the program in the normal way using instruction
SUBS pc, r14, #4, the abandoned instruction is re-executed. This means that some of the
memory accesses generated by the instruction are performed twice.
Memory that is marked as Strongly-ordered or Device type is typically sensitive to the number
of reads or writes performed. Because of this, instructions that access Strongly-ordered or
Device memory are never abandoned when they have started accessing memory. These
60
instructions always complete either all or none of their memory accesses. Therefore, to
minimize the interrupt latency, you must avoid the use of multiword load/store instructions to
memory locations that are marked as Strongly- ordered or Device.
11. Interrupt controller
The processor includes a VIC port for connection of a Vectored Interrupt Controller (VIC).
An interrupt controller is a peripheral that handles multiple interrupt sources. Features usually
found in an interrupt controller are
 Multiple interrupt request inputs, one for each interrupt source, and one or more
amalgamated interrupt request outputs to the processor
 The ability to mask out particular interrupt requests
 Prioritization of interrupt sources for interrupt nesting.
 Ina system with an interrupt controller with these
features,software is still required to:
 Determine from the interrupt controller which interrupt source is requesting service
 Determine where the service routine for that interrupt source is loaded
 Mask or clear that interrupt source, before re-enabling processor
interrupts to permit another interrupt to be taken.
A VIC does all these in hardware to reduce the interrupt latency. It supplies the starting
addressof the service routine corresponding to the highest priority asserted interrupt source
directly to the processor. When the processor has accepted this address, it masks the interrupt
so that the processor can re-enable interrupts without clearing the source. The PL192 VIC is
an AMBA compliant, SoC peripheral that is developed, tested, and licensed by ARM.You can
use the VIC port to connect a PL192 VIC to the processor. See the ARM PrimeCell Vectored
Interrupt Controller (PL192) Technical Reference Manual for more information about the
PL192 VIC. You can enable the VIC port by setting the VE bit in the SCTLR. When the VIC
port is enabled and an IRQ occurs, the processor performs an handshake over the VIC interface
to obtain the address of the handling routine for the IRQ.

11.6 Exception when processor in the Thumb mode

Vector table
The vector table All ARM systems have a vector table. The vector table does not form part of
the initialization sequence, but it must be present for any exception to be serviced. It must be 61

placed at a specific address, usually 0x0.

 Setting up an embedded development environment using the Micro-C compiler and Keil IDE
involves several steps, including the installation of necessary software components and
configurations. Below is a general guide to help you set up the development environment:

1. Install Keil IDE:

 Download the Keil MDK (Microcontroller Development Kit) from the official Keil website.
 Run the installer and follow the on-screen instructions.
 During installation, you can choose the components you want to install, including the Keil
µVision IDE, debugger, and other tools.
2. Install Micro-C Compiler:
 Keil MDK typically comes with the ARM Compiler integrated, so a separate installation of the
Micro-C compiler might not be necessary.
 Verify the installed toolchain versions in Keil to ensure compatibility with your target
microcontroller.
3. Configure Keil µVision:
 Open Keil µVision IDE.
 Configure the IDE settings:
 Select the target microcontroller device: Project -> Manage -> Device.
 Configure target options like the oscillator frequency, memory model, etc.: Project ->
Options for Target.
 Set up the debug interface: Debug -> Settings.
 Specify the output directory and file names: Project -> Options for Target -> Output.
4. Create a New Project:
 Create a new project: Project -> New µVision Project.
 Choose a project name and location.
 Select your microcontroller device from the list.
5. Configure Project Settings:
 Configure the project settings:
 Set up C/C++ compiler options: Project -> Options for Target -> C/C++.
 Specify include paths, defines, and other compiler options.
 Configure linker options: Project -> Options for Target -> Linker.
 Specify memory regions, stack/heap sizes, etc.
6. Write and Import Code:
 Write your embedded C code or import existing source files into the project.
 Add source files to the project: Project -> Add Files to Project.
7. Build the Project:
 Build the project: Project -> Build Target or use the toolbar icon.
 Check the build output window for any errors or warnings.
8. Debugging:
 Configure and start the debugger:
 Set breakpoints, watch variables, and configure other debugging options.
 Debug -> Start/Stop Debug Session.
9. Flash Programming:
 If you have a target board with a debugger or flash programmer, configure flash programming
settings.
 Program the microcontroller: Flash -> Download. 62
 10. Verify and Debug:
 Verify the code execution on the target hardware.
 Use the debugging features to inspect variables, step through code, and diagnose issues.
Additional Tips:
 Ensure that you have the appropriate device support pack installed for your microcontroller.
Keil provides these packs for various microcontroller families, and you can download and
install them through the Pack Installer.
 Refer to the specific documentation for your microcontroller and Keil version for any platform-
specific considerations or configurations.
Common Issues and Troubleshooting:
 Compiler/Toolchain Issues:
 Ensure the Micro-C compiler and Keil MDK versions are compatible.
 Check for updates and patches on the Keil website.
 Target Hardware Connection:
 Ensure that your target hardware is properly connected to the debugger.
 Check the device and connection settings in Keil.
 Memory Configuration:
 Verify that the memory regions and sizes are correctly configured in the project
settings.
 Include Paths and Libraries:
 Confirm that the necessary include paths and libraries are specified in the project
settings.
 Startup Code and System Initialization:
 Check the correctness of the startup code and system initialization in your project.

Embedded C applications using Micro-C and Keil compilers:

Developing and deploying embedded C applications using Micro-C and Keil compilers
involves a series of steps, from writing code to flashing the program onto the target
microcontroller. Below is a typical workflow for embedded C application development with
Micro-C and Keil compilers:

1. Project Setup:
 Create a new project in Keil µVision IDE.
 Select the target microcontroller device for your project.
 Configure project settings, including memory model, stack size, and peripheral configurations.
2. Write Embedded C Code:
 Write the embedded C code for your application using the Keil µVision IDE.
 Organize code into source files, and include any necessary libraries.
 Implement initialization routines for peripherals, system clocks, and other hardware-specific
configurations.
3. Configure Compiler Options:
 Set compiler options in Keil µVision for your project:
 Specify include paths for header files.
 Define preprocessor macros and constants.
 Configure compiler optimization levels.
4. Build the Project: 63
 Build the project to compile the source code into machine code:
 Click on Project -> Build Target or use the toolbar icon.
  Check the build output window for any errors or warnings.
5. Debugging and Testing:
 Configure the debugger settings:
 Set up breakpoints and watchpoints.
 Configure variable and memory views.
 Start a debug session to test and debug your application:
 Click on Debug -> Start/Stop Debug Session.
 Use debugging features like stepping through code, inspecting variables, and
monitoring peripherals.
6. Flash Programming:
 Configure flash programming settings to specify the programming algorithm and memory
regions.
 Connect the debugger to the target hardware.
 Program the microcontroller with the compiled code:
 Click on Flash -> Download or use the appropriate programming command.
7. Verify Operation on Hardware:
 Power up the target hardware with the flashed code.
 Verify the correct execution of the application on the hardware.
 Use debugging features to troubleshoot and fix any issues encountered during runtime.
8. Optimization and Refinement:
 Fine-tune your code for performance and efficiency.
 Optimize critical sections of code.
 Refactor and improve code structure and readability.
9. Documentation:
 Document your code, including comments and explanations of key functions.
 Create a README file detailing the project, hardware setup, and any specific instructions for
other developers or users.
10. Version Control:
 Use a version control system (e.g., Git) to track changes in your project.
 Commit code changes with meaningful messages.
11. Release and Deployment:
 Package your embedded C application for deployment:
 Ensure that all necessary files (binary, configuration files, etc.) are ready.
 Create a release build if necessary, ensuring that optimizations are applied.
12. Testing in Different Environments:
 If applicable, test your embedded C application on various hardware configurations or
environments.
 Ensure compatibility with different microcontroller models and configurations.
13. Documentation and User Guides:
 Provide comprehensive documentation for your embedded C application.
 Include user guides, installation instructions, and troubleshooting tips.
14. Maintenance and Updates:
 Monitor your project for bug reports and user feedback.
 Address issues and release updates as needed.
15. Collaboration and Teamwork:
 If working in a team, collaborate through version control and communicate effectively. 64
 Share knowledge and best practices among team members.
 Note:
 The specifics of the workflow may vary based on the project requirements, the microcontroller
architecture, and the features provided by the Keil µVision IDE.

65