Unit 1

PIC microcontroller Architecture

Q.1 Compare RISC and CISC Architecture.

RISC CISC

1. Reduced instruction set computers 1. Complex instruction set computer

2. Fixed instruction length 2. Variable instruction length

3. Multiple register set 3. Single register set

4. Instructions are executed by micro-
4. Instructions are executed by hardware
program

5. It requires single cycles for execution 5. It requires multiple cycles for execution

6. No. of instructions less than 100 6. No. of instructions 120 to 350

7. Highly pipelined 7. Less pipelined

8. High chip regularity 8. Low chip regularity

9. Example: MCS-51 microcontroller, PIC
9. Example: MC68HC11
microcontroller

Q.2 Compare Von-Neumann and Harvard Architecture.

Von-Neumann architecture Harvard architecture

2. A single set of address/data buses between 2. Two sets of address/data buses between
CPU and memory CPU and memory

3. Same memory holds data and instructions 3. Separate memories for data and instructions

4. Von-Neumann architectures are called CISC 4. Harvard architecture are called RISC
microcontrollers microcontrollers

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5. It has more instructions than Harvard 5. It has less instructions than Von-Neumann
architecture architectures

6. Needs multiple fetches for processing 6.Instruction can be prefetched and decoded while
instruction. multiple data are being fetched and processed.

7. Example: MCS-51 microcontroller, PIC

7.Example: MC68HC11
microcontroller

Q.3 Comparison of features of PIC10, PIC12, PIC16 and PIC18 families.

Features PIC10 PIC12 PIC16 PIC18

1.size 8 bit 8bit 8bit 8bit
2. no. of 33 35 49 83
instructions
3.Timers 1 1 3 4
4.performance 5 MIPS 5 MIPS 8 MIPS Up to 16 MIPS
5.Stack 2 level 8 level 16 level 32 level
6.Other Features  Comparator  Comparator  Comparator  Comparator
 8 bit ADC  8 bit ADC  8 bit ADC  8 bit ADC
 Data memory  Data memory  Data memory  Data memory
 Internal  Internal  Internal  Internal
oscillator oscillator oscillator oscillator
 UART  UART  UART
 LCD  LCD  LCD
 10 bit ADC  10 bit ADC  10 bit ADC
 PWMs  PWMs  PWMs
 SPI/I2C  SPI/I2C  8*8 multiplier
 CAN,USB
 Ethernet

Q.4 what are the features of PIC microcontroller?

1. Peripheral Features:

• High current sink/source 25 mA/25 mA

• Three external interrupt pins

• Timer0module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler

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• Timer1module: 16-bit timer/counter

• Timer2module: 8-bit timer/counter with 8-bit period register (time base for PWM)

• Timer3module: 16-bit timer/counter

• Secondary oscillator clock option – Timer1/Timer3

 It supports master synchronous serial port module that supports two operating modes:

1. SPI 2. I2C

2. High-Performance RISC CPU:

• Linear program memory addressing up to 2 Mbytes

• Linear data memory addressing to 4 Kbytes

• Up to 10 MIPS operation

• DC – 40 MHz clock input

• 4 MHz-10 MHz oscillator/clock input with PLL active

• 16-bit wide instructions, 8-bit wide data path

• Priority levels for interrupts

• 8 x 8 Single-Cycle Hardware Multiplier

3. Advanced Analog Features:

• 10-bit, up to 8-channel Analog-to-Digital Converter module (A/D) with:

- Conversion available during Sleep

- Up to 8 channels available

• Analog Comparator module:

- Programmable input and output multiplexing

• Comparator Voltage Reference module

• Programmable Low-Voltage Detection (LVD) module:

- Supports interrupt-on-Low-Voltage Detection

• Programmable Brown-out Reset (BOR)

4. Special Microcontroller Features:

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

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• Watchdog Timer (WDT) with its own on-chip RC oscillator

• Programmable code protection

• Power-saving Sleep mode

• Selectable oscillator options, including:

- 4x Phase Lock Loop (PLL) of primary oscillator

- Secondary Oscillator (32 kHz) clock input

• In-Circuit Serial Programming via two pins

5. Flash Technology:

• Low-power, high-speed Enhanced Flash technology

• Fully static design

• Wide operating voltage range (2.0V to 5.5V)

• Industrial and Extended temperature ranges

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Q.5 Draw and explain architecture of PIC 18Fxx microcontroller.

Ans:- Architecture of PIC 18Fxx microcontroller

1. ALU:

 It is 8 bit unit.
 It is used to perform arithmetic and logical operations.
 In case of instructions with two operands one operand is in the WREG and
other operand is in file register or immediate constant.

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  In multiplication and division operations one of the 8 bit operand should
present in accumulator.
 ALU can affect the status register bits depending on instruction execution.

2. Working register (WREG):

 It is 8 bit register used to stored data temporarily.

 It is used in ALU operation.
 It is not addressable register.

3. Instruction decode and control:

Instruction decode and control unit decodes the instruction means

convert it into machine code.
4. Program counter (PC):

 Program counter is 21-bit register.

 It holds the address of instruction in memory.
 Its function is to keep the track of program execution.
 The program instruction bytes are fetched from location in
memory that are addressed by the program counter.
 The data bytes in program memory are accessed by the PC.

5. 5 I/O ports: port A,B.C,D and E:

 PIC microcontroller has 5 input output ports.

 All ports are bidirectional.
 Port A to D are 8-bit ports. And port E is 4 bit port.
 TRISx signal is to define the direction of ports

6. 32 level stack

 PIC has 32 levels of stack. Stack memory uses SRAM

 Operation of a stack:
 When a function is called, the return address (location of the next step in
a program) is pushed onto the stack.
For example: Stack number 1 will have value= 0x0x1F0000
 When the return occurs within the function, the return address is
retrieved from the stack and placed into the program counter.

7. Instruction register:

 Instruction register (IR) is the part of a CPU's control unit that stores the
instruction currently being executed or decoded.

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 8. Timer0 to Timer 3:

1. Timer 0:
 Software selectable as an 8-bit or 16-bit timer/counter
• Readable and writable
• Dedicated 8-bit software programmable prescaler
• Clock source selectable to be external or internal
• Interrupt-on-overflow from FFh to 00h in 8-bit mode, and FFFFh
to 0000h in 16-bit mode
• Edge select for external clock
2. Timer 1:
• 16-bit timer/counter
• (Two 8-bit registers: TMR1H and TMR1L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h

3. Timer 2:
 8-bit timer (TMR2 register)
• 8-bit period register (PR2)
• Readable and writable (both registers)
• Software programmable prescaler
• Software programmable postscaler
• Interrupt on TMR2 match of PR2
• SSP module optional use of TMR2 output to generate clock shift.

4. Timer 3:
• 16-bit timer/counter
• (Two 8-bit registers: TMR3H and TMR3L)
• Readable and writable (both registers)
• Internal or external clock select
• Interrupt-on-overflow from FFFFh to 0000h
• RESET from CCP module trigger

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9. 10 bit ADC:

 PIC microcontroller has 10 bit ADC having 8 analog channels. The A/D
module has four registers. They are
1. ADRESH (A/D result high register)
2. ADRESL (A/D result low register)
3. A/D control register 0 (ADCON0)
4. A/D control register 1 (ADCON1)

10. UART:

 UART is universal asynchronous reception and transmission used

for serial communication.

11. CCP (Capture, compare, PWM) and ECCP module

 The CCP (Capture/Compare/PWM) module contains a 16-bit register that can

operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM
Duty Cycle register.

12. 8x8 hardware multiplier: -

 An 8 x 8 hardware multiplier is included in the ALU of the PIC18FXX8
devices.
 By making the multiply a hardware operation, it completes in a single
instruction cycle.
 This is an unsigned multiply that gives a 16-bit result. The result is stored into
the 16bit product register pair (PRODH: PRODL).
 The multiplier does not affect any flags in the STATUS register.

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 Pin diagram of PIC 18f458 microcontroller

Q.6 Write short note on PC and Stack pointer

1. PROGRAM COUNTER

 Program counter is 21-bit register.

 It holds the address of instruction in memory.

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  Its function is to keep the track of program execution.
 The program instruction bytes are fetched from location in memory that
are addressed by the program counter.
 The data bytes in program memory are accessed by the PC.

PC format:
PCLATU PCLATH

Reserved PCU PCH PCL

23 21 20 16 15 8 7 0

 From figure lower byte of PC i.e. PCL is 8 bit register. This is readable
and writable register.
 The higher byte of PC is called PCH register. It is 8 bit register. This
register is not directly readable or writable.
 PCLATH register is used to do updates on PCH register.
 PCU is upper byte of 21 bi program counter. It is not directly readable
and writable.
 The PCLATU register is used for doing updates on PCU register.

2. STACK and STACK POINTER

PIC stack

A20 STACK A0

21-bit

11111 – Top of the stack

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Function:-

 The stack is reserved RAM area of memory where temporary data and address can be
stored.

 The size of the stack is 21 bit.

 The 5 bit stack pointer is used to hold the address of the most recent entry.

 The 5 bit stack pointer can access 2^5=32 locations making the stack 32 level deep stack.

 The information is written on the stack using PUSH instruction.

 The information is read from the stack using POP instruction.

Q.7 Draw and explain structure of memory map of PIC.

PIC microcontroller based on Harvard architecture having separate program memory and
separate data memory.

Figure below shows memory mapping of PIC microcontroller.

Program memory:-

1. The PIC18F258/458 devices have a 21-bit program counter that is capable of addressing
the 2Mbyte program memory space.
2. Program memory is 16-bits wide accessed through a separate program Data bus and
address bus inside the PIC18.
3. Program memory stores the program and also static data in the system.
 On-chip
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  External
4. On-chip program memory is either PROM or EEPROM.
 The PROM version is called OTP (one-time programmable) (PIC18C)
 The EEPROM version is called Flash memory (PIC18F).
5. Maximum size for program memory is 2M
 Program memory addresses are 21-bit address starting at location
0x000000rogram Memory.
6. The PIC18 contains a program stack that stores up to 31 return addresses from functions.
 31-deep
 The program stack is 21 bits in width as is the program address
7. Stack memory uses SRAM
8. Operation of a stack
 When a function is called, the return address (location of the next step in a program) is
pushed onto the stack.
For example: Stack number 1 will have value= 0x0x1F0000
 When the return occurs within the function, the return address is retrieved from the stack
and placed into the program counter.

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 Fig. Program memory map

Data memory:

1. Data memory is implemented as static RAM.

2. Every location in the data memory is called as a File register or register.

3. 4 KB of data memory. Data register map - with 12-bit address bus 000-FFF

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4. From data memory organization it is seen that PIC 18 has two types of registers

 General purpose register

 Special function register

5. General purpose registers (GPRs) are used storing the data for different program modules
and applications.

6. Special function register (SFRs) are used to control the device operation.

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7. Bank 0 to Bank 14 is allocated for GPRs. Bank 15 is allocated to SFRs.

8. Access Bank:

 Access bank is made up of Bank 0 GPR lower part and Bank 15 SFR higher part.
 Access bank is of 256 bytes.
 Out of 256 bytes of Access bank 128 bytes are allocated to GPRs and 128 bytes are
allocated to SFRs.
9. Bank Select Register (BSR):
 BSR is 8 bit SFR.
 The lower 4 bits are used for selecting the bank and remaining 4 bits are zero.
 “A” bit (access bit) in the instruction indicated whether the operation will takes
place in Access bank or the BSR.
If A= 1 then BSR is used for selecting the desired bank.

Q.8 Registers of PIC 18F458 microcontroller.

Two types of registers

1. General purpose register

2. Special function registers.

1. General purpose register (GPR):-

 GPRs are group of RAM locations in the file register.

 GPRs are mainly used for storing the data.

 GPRs are 8 bit registers.

 The register file can be accessed either directly or indirectly. Indirect addressing is
done with File Select Registers (FSR).

2. Special Function registers (SFR):-

 The SFRs are registers used by the CPU and peripherals for controlling the desired
operation of the device.

e.g. Serial communication, timers, counters, PWM etc.

 The SFRs are implemented as static RAM.

 Every SFRs are 8 bit register.

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16
Q.9 Status registers in PIC microcontroller.

Q.10 Explain Reset control register (RCON) register:

Reset control register

1. IPEN:- Interrupt Priority Enable bit.

1= interrupt priority enable

0= interrupt priority disable

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 2. RI #:- Reset instruction flag

1=set instruction flag

0=reset instruction flag

3. TO#:- Watchdog time out flag

1= after power up, CLRWDT or SLEEP instruction

0= WDT time out occurred

4. PD#:- Power down detection flag

1=after power up or by CLREDT instruction

0= by execution of SLEEP instruction

5. POR#:- Power on reset bit

1= power on reset has not occurred

0= power on reset has occurred

6. BOR#:- Brown out reset

1=Brown out reset has not occurred

0= Brown out reset has occurred

Q.11 What are the various oscillator options?

The PIC18FXX8 can be operated in one of eight oscillator modes, programmable by three
configuration bits (FOSC2, FOSC1, and FOSC0).

1. LP: - Low Power Crystal

2. XT: - Crystal/Resonator

3. HS:-High Speed Crystal/Resonator

4. HS4:- High Speed Crystal/Resonator with PLL enabled

5. RC: -External Resistor/Capacitor

6. RCIO:-External Resistor/Capacitor with I/O pin enabled

7. EC: - External Clock

8. ECIO: -External Clock with I/O pin enabled

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There are three oscillator types uses 8 oscillator modes.

1. Crystal Oscillator/Ceramic Resonators

 In XT, LP, HS or HS4 (PLL) oscillator modes, a crystal or ceramic resonator is connected
to the OSC1 and OSC2 pins to establish oscillation. Figure shows the pin connections. An
external clock source may also be connected to the OSC1 pin, as shown in Figure.

2. RC Oscillator

 For timing insensitive applications, the “RC” and "RCIO" device options offer additional
cost savings.
 The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and
capacitor (CEXT) values and the operating temperature.
 In addition to this, the oscillator frequency will vary from unit to unit due to normal
process parameter variation. Furthermore, the difference in lead frame capacitance
between package types will also affect the oscillation frequency.
 The user also needs to take into account variation due to tolerance of external R and C
components used. Figure shows how the RC combination is connected.
 In the RC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2
pin. This signal may be used for test purposes or to synchronize other logic.

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3. External Clock Input
1. The EC and ECIO oscillator modes require an external clock source to be connected to the
OSC1 pin.
2. The feedback device between OSC1 and OSC2 is turned off in these modes to save
current. There is no oscillator start-up time required after a Power-on Reset or after a
recovery from SLEEP mode.
3. In the EC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2
pin. This signal may be used for test purposes or to synchronize other logic. Figure shows the
pin connections for the EC oscillator mode.

Oscillator control registers:

OSCCON register:
OSC control register controls the clock switching between main oscillator and timer 1
oscillator.
7 6 5 4 3 2 1 0

------- ------ ------ ------ ------ ------ ------- SCS

Bit 7 to 1: Unimplemented
Bit 0 : SCS:- System clock switch bit
If SCS=1 Switch to timer 1 oscillator/clock pin
SCS=0 Use primary oscillator/clock pin.

Q.12 Explain RESET

PIC 18 supports different types of RESET:

1. Power on Reset
2. MCLR# reset during normal and sleep
3. Brown out Reset (BOR)
4. Stack full Reset
5. RESET instruction
6. Watchdog Timer(WDT)
7. Stack underflow Reset.

Block diagram of RESET circuit:

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1. Power-on Reset (POR):

 A Power-on Reset pulse is generated on-chip when a VDD rise is detected. To take
advantage of the POR circuitry, connect the MCLR pin directly (or through a
resistor) to VDD.

 This eliminates external RC components usually needed to create a Power-on

Reset delay.

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  A minimum rise rate for VDD is specified.

 When the device starts normal operation (exits the RESET condition), device
operating parameters (voltage, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device must be held in RESET until
the operating conditions are met.

External Power On reset circuit:

2. Power-up Timer (PWRT):

 The Power-up Timer provides a fixed nominal time-out, only on power-up from the

POR.

 The Power-up Timer operates on an internal RC oscillator.

 The chip is kept in RESET as long as the PWRT is active. The PWRT’s time delay
allows VDD to rise to an acceptable level.

 A configuration bit (PWRTEN in CONFIG2L register) is provided to

enable/disable the PWRT.

3. Oscillator Start-up Timer (OST):

 The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from
OSC1 input) delay after the PWRT delay is over.

 This additional delay ensures that the crystal oscillator or resonator has started
and stabilized.

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  The OST time-out is invoked only for XT, LP, HS and HS4 modes and only on

Power-on Reset or wake-up from SLEEP.

4. PLL Lock Time-out:

 With the PLL enabled, the time-out sequence following a Power-on Reset is
different from other oscillator modes.

 A portion of the Power-up Timer is used to provide a fixed time-out that is

sufficient for the PLL to lock to the main oscillator frequency.

 This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start
up time-out (OST).

5. Brown-out Reset (BOR):

 A configuration bit, BOREN, can disable or enable the Brown-out Reset circuitry.

 If VDD falls below the desired parameter, brown-out situation resets the chip.

 A RESET may not occur if VDD falls below desired parameter.

 The chip will remain in Brown-out Reset until VDD rises above BVDD.

 The Power-up Timer will then be invoked and will keep the chip in RESET
an additional time delay.

 If VDD drops below BVDD while the Power-up Timer is running, the chip will
go back into a Brown-out Reset and the Power-up Timer will be initialized.

6. Watchdog timer:

 The watchdog timer (WDT) can be used for doing microcontroller RESET.

 This feature improves and enhances the overall microcontroller system operation.

 The watchdog timer is free running, on-chip RC oscillator.

 Even if the system clock oscillator has stopped WDT will run, even if SLEEP

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 instruction is executed by microcontroller.

 When WDT is in SLEEP mode and if time out occurs then the microcontroller
wakes up and continues normal operation.

 When WDT time out occurs, the TO# bit in the RCON register is cleared.

 WDTEN configuration bit can be used for enabling/disabling the watchdog timer.

WDTCON register: - Watchdog timer control register

------------ ------------ ------------- ------------- -------------- --------- ------- SWDTEN

7 6 5 4 3 2 1 0

Bit 7 to 1:- Unimplemented

Bit 0:- SWDTEN: - software controlled Watchdog Timer enable bit

1= Watchdog timer is on

0= Watchdog timer is turned off

Watchdog timer:

7. Power-down Mode (SLEEP mode):

 Power-down mode is entered by executing a SLEEP instruction.

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  If enabled, the Watchdog Timer will be cleared, but keeps running, the PD
bit is cleared, the TO bit is set, and the oscillator driver is turned off.
 The I/O ports maintain the status they had before the SLEEP instruction
was executed.
 For lowest current consumption in this mode, place all I/O pins at either
VDD or VSS, ensure no external circuitry is drawing current from the I/O
pin, power-down the A/D and disable external clocks.
 Pull all I/O pins that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs.
 The T0CKI input should also be at VDD or VSS for lowest current
consumption. The contribution from on-chip pull-ups on PORTB should be
considered.

WAKE-UP FROM SLEEP

 The device can wake-up from SLEEP through one of the following events:
1. External RESET input on MCLR pin.
2. Watchdog Timer Wake-up (if WDT was enabled).
3. Interrupt from INT pin, RB port change or a Peripheral Interrupt.

 The following peripheral interrupts can wake the device from SLEEP:
1. PSP read or writes.
2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter.
3. TMR3 interrupt. Timer3 must be operating as an asynchronous counter.
4. CCP Capture mode interrupt.
5. Special event trigger (Timer1 in Asynchronous mode using an external clock).
6. MSSP (START/STOP) bit detect interrupt.
7. MSSP transmit or receive in Slave mode (SPI/I2C).
8. USART RX or TX (Synchronous Slave mode).
9. A/D conversion (when A/D clock source is RC).
10. EEPROM write operation complete.
11. LVD interrupt.

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Q.13 Write short note on EEPROM memory of PIC 18F458

 The EEPROM data memory is readable and writable during normal operation (full
VDD range).
 This memory is not directly mapped in the register file space. Instead it is indirectly
addressed through the Special Function Registers.
 There are four SFRs used to read and write this memory.
 These registers are:
• EECON1
• EECON2 (not a physically implemented register)
• EEDATA
• EEADR
 EEDATA holds the 8-bit data for read/write, and EEADR holds the address of the
EEPROM location being accessed.
 The 8-bit EEADR register can access up to 256 locations of Data EEPROM.
 The EEADR register can be thought of as the indirect addressing register of the Data
EEPROM
 EECON1 contains the control bits, while EECON2 is the register used to initiate the
read/write.
EECON1 Control register

7 6 5 4 3 2 1 0

EEPGD EEFS ------ FREE WRERR WREN WR RD

Bit 7 EEPGD: FLASH Program or Data EEPROM Memory Select bit

1 = Access Program Flash memory

0 = Access Data EEPROM memory

bit 6 EEFS: FLASH Program/Data EE or Configuration Select bit

1 = Access configuration registers

0 = Access Program FLASH or Data EEPROM memory

bit 5 Unimplemented: Read as '0'

bit 4 FREE: FLASH Row Erase Enable bit

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1 = Erase the program memory row addressed by TBLPTR on the next WR command (reset
by hardware)

0 = Perform write only

bit 3 WRERR: Write Error Flag bit

1 = A write operation is prematurely terminated (any MCLR or any WDT Reset during self-
timed programming in normal operation)

0 = The write operation completed Note: When a WRERR occurs, the EEPGD or FREE bits
are not cleared. This allows tracing of the error condition.

bit 2 WREN: Write Enable bit

1 = Allows write cycles

0 = Inhibits write to the EEPROM or FLASH memory

bit 1 WR: Write Control bit

1 = Initiates a data EEPROM erase/write cycle or a program memory erase cycle or write
cycle (The operation is self-timed and the bit is cleared by hardware once write is complete.
The WR bit can only be set (not cleared) in software.)

0 = Write cycle is complete

bit 0 RD: Read Control bit

1 = Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit
can only be set (not cleared) in software. RD bit cannot be set when EEPGD = 1.)

0 = Does not initiate an EEPROM read.

 Reading the Data EEPROM Memory

To read a data memory location, the user must write the address to the EEADR register, clear
the EEPGD control bit (EECON1) and then set control bit RD (EECON1). The data is
available in the very next instruction cycle of the EEDATA register, therefore, it can be read
by the next instruction. EEDATA will hold this value until another read operation, or until it
is written to by the user (during a write operation).

 Writing to the Data EEPROM Memory

To write an EEPROM data location, the address must first be written to the EEADR register
and the data written to the EEDATA register.

Then the sequence in Example 5-2 must be followed to initiate the write cycle. The write will
not initiate if the above sequence is not exactly followed (write 55h to EECON2, write AAh
to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be

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disabled during this code segment. Additionally, the WREN bit in EECON1 must be set to
enable writes. This mechanism prevents accidental writes to data EEPROM due to
unexpected code execution (i.e., runaway programs).

The WREN bit should be kept clear at all times, except when updating the EEPROM. The
WREN bit is not cleared by hardware. After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle.

The WR bit will be inhibited from being set unless the WREN bit is set. The WREN bit must
be set on a previous instruction. Both WR and WREN cannot be set with the same
instruction. At the completion of the write cycle, the WR bit is cleared in hardware and the
EEPROM Write Complete Interrupt Flag bit (EEIF) is set. The user may either enable this
interrupt, or roll this bit. EEIF must be cleared by software.

Q.14 Write short note on Flash memory of PIC 18f458 microcontroller.

 The FLASH Program Memory is readable, writable, and erasable during normal
operation over the entire VDD range.
 A read from program memory is executed on one byte at a time.
 A write to program memory is executed on blocks of 8 bytes at a time.
 Program memory is erased in blocks of 64 bytes at a time.
 There are two operations that allow the processor to move bytes between the program
memory space and the data RAM:
• Table Read (TBLRD)
• Table Write (TBLWT)
 The program memory space is 16-bits wide, while the data RAM space is 8-bits wide.
 Table Reads and Table Writes move data between these two memory spaces through
an 8-bit register (TABLAT).
 Table Read operations retrieve data from program memory and places it into the data
RAM space.
 Figure shows the operation of a Table Read with program memory and data RAM.
Table Write operations store data from the data memory space into holding registers
in program memory.
 TABLE READ OPERATION

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 TABLE WRITE OPERATION

 TABLAT - TABLE LATCH REGISTER

 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space.
 The Table Latch is used to hold 8- bit data during data transfers between program
memory and data RAM.

 TBLPTR - TABLE POINTER REGISTER

 The Table Pointer (TBLPTR) addresses a byte within the program memory.
 The TBLPTR is comprised of three SFR registers: Table Pointer Upper Byte, Table
Pointer High Byte and Table Pointer Low Byte (TBLPTRU: TBLPTRH: TBLPTRL).
 These three registers join to form a 22-bit wide pointer.
 The low order 21 bits allow the device to address up to 2 Mbytes of program memory
space. The 22nd bit allows access to the Device ID, the User ID and the Configuration
bits.
 The table pointer, TBLPTR, is used by the TBLRD and TBLWT instructions. These
instructions can update the TBLPTR in one of four ways based on the table operation.
 These operations on the TBLPTR only affect the low order 21 bits.

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