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TPS54302
SLVSDG6A – MAY 2016 – REVISED MAY 2016

TPS54302 4.5-V to 28-V Input, 3-A Output, EMI Friendly

Synchronous Step-Down Converter
1 Features 3 Description
•
1 4.5-V to 28-V Wide Input Voltage Range The TPS54302 is a 4.5-V to 28-V input voltage range,
3-A synchronous buck converter. The device includes
• Integrated 85-mΩ and 40-mΩ MOSFETs for 3-A, two integrated switching FETs, internal loop
Continuous Output Current compensation and 5-ms internal soft start to reduce
• Low 2-μA Shutdown, 45-μA Quiescent Current component count.
• Internal 5-mS Soft-Start By integrating the MOSFETs and employing the SOT-
• Fixed 400-kHz Switching Frequency 23 package, the TPS54302 achieves the high power
• Frequency Spread Spectrum to Reduce EMI density and offers a small footprint on the PCB.
• Advanced Eco-mode™ Pulse Skip Advanced Eco-mode implementation maximizes the
• Peak Current Mode Control light load efficiency and reduces the power loss.
• Internal Loop Compensation In the TPS54302, the frequency spread spectrum
• Overcurrent Protection for Both MOSFETs with operation is introduced for EMI reduction.
Hiccup Mode Protection Cycle-by-cycle current limit in both high-side
• Over Voltage Protection MOSFET protects the converter in an overload
condition and is enhanced by a low-side MOSFET
• Thermal Shutdown
freewheeling current limit which prevents current
• SOT-23 (6) Package runaway. Hiccup mode protection is triggered if the
overcurrent condition has persisted for longer than
2 Applications the present time.
• 12-V, 24-V Distributed Power-Bus Supply
Device Information(1)
• Industry Application PART NUMBER PACKAGE BODY SIZE (NOM)
– White Goods TPS54302 SOT-23(6) 1.60 mm × 2.90 mm
• Consumer Application
(1) For all available packages, see the orderable addendum at
– Audio the end of the data sheet.
– STB, DTV
– Printer
Simplified Schematic
TPS54302
Efficiency vs Output Current
3 6 100
VIN VIN BOOT
Cin Cboot 90
Lo
1 2
GND SW VOUT 80
Rfb1 70
5 4
Efficiency (%)

EN EN FB 60
Co
Rfb2
50
40
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30
VIN = 12 V, VOUT = 5 V
20 VIN = 12 V, VOUT = 3.3 V
10 VIN = 24 V, VOUT = 5 V
VIN = 24 V, VOUT = 3.3 V
0
0.001 0.01 0.1 1
Output Current (A) D100

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................... 9
2 Applications ........................................................... 1 7.4 Device Functional Modes........................................ 12
3 Description ............................................................. 1 8 Application and Implementation ........................ 13
4 Revision History..................................................... 2 8.1 Application Information............................................ 13
8.2 Typical Application ................................................. 13
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 20
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 21
6.2 ESD Ratings.............................................................. 4 10.1 Layout Guidelines ................................................. 21
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 21
6.4 Thermal Information .................................................. 4 11 Device and Documentation Support ................. 22
6.5 Electrical Characteristics........................................... 5 11.1 Community Resources.......................................... 22
6.6 Timing Requirements ................................................ 5 11.2 Trademarks ........................................................... 22
6.7 Typical Characteristics .............................................. 6 11.3 Electrostatic Discharge Caution ............................ 22
7 Detailed Description .............................................. 8 11.4 Glossary ................................................................ 22
7.1 Overview ................................................................... 8 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ......................................... 8 Information ........................................................... 22

4 Revision History
Changes from Original (May 2016) to Revision A Page

• Changed from Product Preview to Production Data .............................................................................................................. 1

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5 Pin Configuration and Functions

DDC Package
6-Pin SOT-23
Top View

GND 1 6 BOOT

SW 2 5 EN

VIN 3 4 FB

Pin Functions
PIN
TYPE (1) DESCRIPTION
NAME NO.
Supply input for the high-side NFET gate drive circuit. Connect a 0.1-μF capacitor between BOOT and
BOOT 6 O
SW pins.
EN 5 I This pin is the enable pin. Float the EN pin to enable.
FB 4 I Converter feedback input. Connect to output voltage with feedback resistor divider.
Ground pin Source terminal of low-side power NFET as well as the ground terminal for controller
GND 1 –
circuit. Connect sensitive VFB to this GND at a single point.
SW 2 O Switch node connection between high-side NFET and low-side NFET.
VIN 3 – Input voltage supply pin. The drain terminal of high-side power NFET.

(1) O = Output; I = Input

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VIN –0.3 30 V
Input voltage range, VI EN –0.3 7 V
FB –0.3 7 V
BOOT-SW –0.3 7 V
Output voltage range, VO SW –0.3 30 V
SW (20 ns transient) –5 30 V
Operating junction temperature, TJ –40 150 °C
Storage temperature range, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
(1)
Electrostatic Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±4000
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VIN 4.5 28 V
VI Input voltage range EN –0.1 7 V
FB –0.1 7 V
BOOT-SW –0.1 7 V
VO Output voltage range
SW –0.1 28 V
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

TPS54302
THERMAL METRIC (1) DDC (SOT-23) UNIT
6 PINS
RθJA Junction-to-ambient thermal resistance 87.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 35.5 °C/W
RθJB Junction-to-board thermal resistance 14.4 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 14.2 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

The electrical ratings specified in this section apply to all specifications in this document, unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the device parametric or functional specifications for the life of
the product containing it. TJ = –40°C to +125°C, VIN = 4.5 V to 28 V, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Input voltage range 4.5 28 V
IQ Non switching quiescent current EN =5 V, VFB = 1 V 45 µA
IOFF Shut down current EN = GND 2 µA
Rising VIN 3.8 4.1 4.4 V
VIN under voltage lockout
VIN(UVLO) Falling VIN 3.3 3.6 3.9 V
Hysteresis 400 480 560 mV
ENABLE (EN PIN)
V(EN_RISING) Rising 1.21 1.28 V
Enable threshold
V(EN_FALLING) Falling 1.1 1.19 V
I(EN_INPUT) Input current VEN = 1 V 0.7 μA
I(EN_HYS) Hysteresis current VEN = 1.5 V 1.55 μA
FEEDBACK AND ERROR AMPLIFIER
VFB Feedback Voltage VIN = 12 V 0.581 0.596 0.611 V
PULSE SKIP MODE
I(SKIP) (1) Pulse skip mode peak inductor current threshold VIN = 12 V, VOUT = 5 V, L = 10 µH 500 mA
POWER STAGE
R(HSD) High-side FET on resistance TA = 25°C, VBST – SW = 6 V 85 mΩ
R(LSD) Low-side FET on resistance TA = 25°C, VIN = 12 40 mΩ
CURRENT LIMIT
I(LIM_HS) High side current limit Maximum inductor peak current 4 5 5.9 A
I(LIM_LS) Low side source current limit Maximum inductor valley current 3.1 4 5.5 A
OSCILLATOR
Fsw Centre switching frequency 290 400 510 kHz
OVER TEMPERATURE PROTECTION
Rising temperature 165 °C
Thermal
Hysteresis 10 °C
Shutdown (1)
Hiccup time 32768 Cycles

(1) Not production tested

6.6 Timing Requirements

MIN TYP MAX UNIT
OVER CURRENT PROTECTION
tHIC_WAIT Hiccup wait time 512 Cycles
tHIC_RESTART Hiccup time before restart 16384 Cycles
tSS Soft-start time 5 ms
ON TIME CONTROL
tMIN_ON (1) Minimum on time, measured at 90% to 90% and 1-A loading 110 ns

(1) Not production tested

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6.7 Typical Characteristics

VIN = 12, unless otherwise specified

Non-Switching Operating Quiescent Current (PA)

2.5
80
Shutdown Quiescent Current (PA)

60
1.5

1
40

0.5

0 20
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Junction Temperature (qC) D001 Junction Temperature (qC) D002

Figure 1. Shutdown Quiescent Current vs Junction Figure 2. Non-Switching Operating Quiescent Current vs
Temperature Junction Temperature
240 80
220
70
200
High side FET Rds(on) (m:)

Low side FET Rds(on) (m:)

180
60
160
140 50
120
40
100
80
30
60
40 20
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Junction Temperature (qC) D003
Junction Temperature (qC) D004

Figure 3. High-Side Resistance vs Junction Temperature Figure 4. Low-Side FET On Resistance vs Junction
Temperature
0.600 420

415
0.598
Switching Frequency (kHz)
Reference Voltage (mV)

410

405
0.596
400
0.594 395

390
0.592
385

0.590 380
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Junction Temperature (qC) D005
Junction Temperature (qC) D006

Figure 5. Reference Voltage vs Junction Temperature Figure 6. Centre Switching Frequency vs Junction
Temperature

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Typical Characteristics (continued)

5.8 4.3

5.3 4.1
High Side Current Limit (A)

Low Side Current Limit (A)

4.8 3.9

4.3 3.7

3.8 3.5

3.3 3.3

2.8 3.1
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Junction Temperature (qC) D007
Junction Temperature (qC) D008

Figure 7. High-Side Current Limit Threshold vs Junction Figure 8. Low-Side Current Limit Threshold vs Junction
Temperature Temperature
2.20 4.5

4.3
BOOT UVLO Threshold (V)

VIN UVLO Threshold (V)

2.15
4.1

2.10 3.9

3.7
2.05
3.5
L->H
H->L
2.00 3.3
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Junction Temperature (qC) D009
Junction Temperature (qC) D010

Figure 9. BOOT-SW UVLO Threshold vs Junction Figure 10. VIN UVLO Threshold vs Junction Temperature
Temperature
1.3 1.70

1.65
1.26
EN Hysteresis Current (PA)
EN UVLO Threshold (V)

1.60
1.22
1.55
1.18
1.50

1.14
1.45
L->H
H->L
1.1 1.40
-50 -25 0 25 50 75 100 125 -50 -25 0 25 50 75 100 125
Junction Temperature (qC) D011
Junction Temperature (qC) D012

Figure 11. EN Threshold vs Junction Temperature Figure 12. EN Hysteresis Current vs Junction Temperature

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7 Detailed Description

7.1 Overview
The device is a 28-V, 3-A, synchronous step-down (buck) converter with two integrated n-channel MOSFETs. To
improve performance during line and load transients the device implements a constant-frequency, peak current
mode control which reduces output capacitance. The optimized internal compensation network minimizes the
external component counts and simplifies the control loop design.
The TPS54302’s switching frequency is fixed to 400 kHz.
The TPS54302 starts switching at VIN equal to 4.5 V. The operating current is 45 μA typically when not switching
and under no load. When the device is disabled, the supply current is 2 µA typically.
The integrated 85-mΩ high-side MOSFET and 40-mΩ low-side MOSFET allow for high efficiency power supply
designs with continuous output currents up to 3 A.
The TPS54302 reduces the external component count by integrating the boot recharge diode. The bias voltage
for the integrated high-side MOSFET is supplied by an external capacitor on the BOOT to PH pins. The boot
capacitor voltage is monitored by an UVLO circuit and will turn the high-side MOSFET off when the voltage falls
below a preset threshold of 2.1 V typically.
The device minimizes excessive output overvoltage transients by taking advantage of the overvoltage
comparator. When the regulated output voltage is greater than 108% of the nominal voltage, the overvoltage
comparator is activated, and the high-side MOSFET is turned off and masked from turning on until the output
voltage is lower than 104%.
The TPS54302 device has internal 5-ms soft-start time to minimize inrush currents.

7.2 Functional Block Diagram

EN VIN

Thermal
UVLO
Hiccup
Ip Ih
OV comparator
-
Shutdown Hiccup
Logic Shutdown
+
EN Compatator
Boot Charge Current
Sense

Minimum Clamp BOOT

Boot UVLO
Pulse Skip
FB -

+ ERROR AMPLIFIER

HS MOSFET
+ Current
Comparator
Power Stage
SW
And
Dead time VIN
20kohm
0.596V Control
Voltage 2pF
Reference Logic Regulator

2.04nF
Slope
Compensation
Soft Start

Current
Overload Sense
Maximum Oscillator LS MOSFET
Hiccup Recovery Clamp Current Limit
Shutdown

GND
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7.3 Feature Description

7.3.1 Fixed-Frequency PWM Control
The device uses a fixed-frequency, peak current-mode control. The output voltage is compared through external
resistors on the FB pin to an internal voltage reference by an error amplifier. An internal oscillator initiates the
turn on of the high-side power switch. The error amplifier output is compared to the current of the high-side
power switch. When the power-switch current reaches the error amplifier output voltage level, the high side
power switch is turned off and the low-side power switch is turned on. The error amplifier output voltage
increases and decreases as the output current increases and decreases. The device implements a current-limit
by clamping the error amplifier voltage to a maximum level and also implements a minimum clamp for improved
transient-response performance.

7.3.2 Pulse Skip Mode

The TPS54302 is designed to operate in pulse skipping mode at light load currents to boost light load efficiency.
When the peak inductor current is lower than 500 mA typically, the device enters pulse skipping mode. When the
device is in pulse skipping mode, the error amplifier output voltage is clamped which prevents the high side
integrated MOSFET from switching. The peak inductor current must rise above 500 mA and exit pulse skip
mode. Since the integrated current comparator catches the peak inductor current only, the average load current
entering pulse skipping mode varies with the applications and external output filters.

7.3.3 Error Amplifier

The device has a trans-conductance amplifier as the error amplifier. The error amplifier compares the FB voltage
to the lower of the internal soft-start voltage or the internal 0.596-V voltage reference. The transconductance of
the error amplifier is 240 µA/V typically. The frequency compensation components are placed internal between
the output of the error amplifier and ground.

7.3.4 Slope Compensation and Output Current

The device adds a compensating ramp to the signal of the switch current. This slope compensation prevents
sub-harmonic oscillations as the duty cycle increases. The available peak inductor current remains constant over
the full duty-cycle range.

7.3.5 Enable and Adjusting Undervoltage Lockout

The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the device begins operation. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters the low-quiescent (IQ) state.
The EN pin has an internal pullup-current source which allows the user to float the EN pin to enable the device. If
an application requires control of the EN pin, use open-drain or open-collector output logic to interface with the
pin.
The device implements internal undervoltage-lockout (UVLO) circuitry on the VIN pin. The device is disabled
when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold has a
hysteresis of 480 mV.
If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown
in Figure 13. When using the external UVLO function, setting the hysteresis at a value greater than 500 mV is
recommended.
The EN pin has a small pull-up current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pull-up current is also used to control the voltage hysteresis for the UVLO
function because it increases by Ih when the EN pin crosses the enable threshold. Use Equation 1 and
Equation 2 to calculate the values of R4 and R5 for a specified UVLO threshold.

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Feature Description (continued)

VIN Device

R4
Ip Ih

EN
R5

Figure 13. Adjustable VIN Undervoltage Lockout

æ VENfalling ö
VSTART ç ÷ - VSTOP
ç VENri sin g ÷
R4 = è ø
æ VENfalling ö
Ip ç 1 - ÷ +I
ç VENri sin g ÷ø h
è (1)
Where:
Ip = 0.7 µA
Ih = 1.55 µA
VENfalling = 1.19 V
VENrising = 1.22 V
R4 ´ VENfalling
R5 =
(
VSTOP - VENfalling + R4 Ip + Ih ) (2)

7.3.6 Safe Startup into Pre-Biased Outputs

The device has been designed to prevent the low-side MOSFET from discharging a pre-biased output. During
monotonic pre-biased startup, both high-side and low-side MOSFETs are not allowed to be turned on until the
internal soft-start voltage is higher than FB pin voltage.

7.3.7 Voltage Reference

The voltage reference system produces a precise ±2.5% voltage-reference over temperature by scaling the
output of a temperature stable bandgap circuit. The typical voltage reference is designed at 0.596 V.

7.3.8 Adjusting Output Voltage

The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use
divider resistors with 1% tolerance or better. Start with 100 kΩ for the upper resistor divider, use Equation 3 to
calculate the output voltage. To improve efficiency at light loads consider using larger value resistors. If the
values are too high the regulator is more susceptible to noise and voltage errors from the FB input current are
noticeable.
é R2 ù
Vout = Vref ´ ê + 1ú
ë R3 û (3)

7.3.9 Internal Soft-Start

The TPS54302 device uses the internal soft-start function. The internal soft start time is set to 5 ms typically.

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Feature Description (continued)

7.3.10 Bootstrap Voltage (BOOT)
The TPS54302 has an integrated boot regulator and requires a 0.1-µF ceramic capacitor between the BOOT and
SW pins to provide the gate drive voltage for the high-side MOSFET. A ceramic capacitor with an X7R or X5R
grade dielectric is recommended because of the stable characteristics over temperature and voltage. To improve
drop out, the TPS54302 is designed to operate at 100% duty cycle as long as the BOOT to SW pin voltage is
greater than 2.1 V typically.

7.3.11 Overcurrent Protection

The device is protected from overcurrent conditions by cycle-by-cycle current limiting on both the high-side
MOSFET and the low-side MOSFET.

7.3.11.1 High-Side MOSFET Overcurrent Protection

The device implements current mode control which uses the internal COMP voltage to control the turn off of the
high-side MOSFET and the turn on of the low-side MOSFET on a cycle-by-cycle basis. During each cycle, the
switch current and the current reference generated by the internal COMP voltage are compared. When the peak
switch current intersects the current reference the high-side switch turns off.

7.3.11.2 Low-Side MOSFET Overcurrent Protection

While the low-side MOSFET is turned on, the conduction current is monitored by the internal circuitry. During
normal operation the low-side MOSFET sources current to the load. At the end of every clock cycle, the low-side
MOSFET sourcing current is compared to the internally set low-side sourcing current-limit. The inductor valley
current is exceeded the low-side source current limit, the high-side MOSFET does not turn on and the low-side
MOSFET stays on for the next cycle. The high-side MOSFET turns on again when the inductor valley current is
below the low-side sourcing current-limit at the start of a cycle as shown in Figure 14.
IL
ILIM_HS

ILIM_LS

High-Side
MOS FET
Skip pulse when IL is Skip pulse when IL is
higher than ILIM_LS higher than ILIM_LS

Low-Side
MOS FET

T T T T

Note: T=1/Fsw

Figure 14. Overcurrent Protection for Both MOSFETs

Furthermore, if an output overload condition occurs for more than the hiccup wait time, which is programmed for
512 switching cycles, the device shuts down and restarts after the hiccup time of 16384 cycles. The hiccup mode
helps to reduce the device power dissipation under severe overcurrent conditions.
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Feature Description (continued)

7.3.12 Spread Spectrum
In order to reduce EMI, the TPS54302 introduces frequency spread spectrum. The jittering span is ±6% of the
switching frequency with 1/512 swing frequency.

7.3.13 Output Overvoltage Protection (OVP)

The TPS54302 incorporates an overvoltage transient protection (OVTP) circuit to minimize output voltage
overshoot when recovering from output fault conditions or strong unload transients. The OVTP circuit includes an
overvoltage comparator to compare the FB pin voltage and internal thresholds. When the FB pin voltage goes
above 108% × Vref, the high-side MOSFET is forced off. When the FB pin voltage falls below 104% × Vref, the
high-side MOSFET is enabled again.

7.3.14 Thermal Shutdown

The internal thermal-shutdown circuitry forces the device to stop switching if the junction temperature exceeds
165°C typically. When the junction temperature drops below 155°C typically, the internal thermal-hiccup timer
begins to count. The device reinitiates the power-up sequence after the built-in thermal-shutdown hiccup time
(32768 cycles) is over.

7.4 Device Functional Modes

7.4.1 Normal Operation
When the input voltage is above the UVLO threshold, the TPS54302 can operate in their normal switching
modes. Normal continuous conduction mode (CCM) occurs when inductor peak current is above 0 A. In CCM,
the TPS54302 operates at a fixed frequency.

7.4.2 Eco-mode™ Operation

The device is designed to operate in high-efficiency pulse-skipping mode under light load conditions. Pulse
skipping initiates when the switch current falls to 500 mA typically. During pulse skipping, the low-side FET turns
off when the switch current falls to 0 A. The switching node (the SW pin) waveform takes on the characteristics
of discontinuous conduction mode (DCM) operation and the apparent switching frequency decreases. As the
output current decreases, the perceived time between switching pulses increases.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The TPS54302 is typically used as a step down converter, which converts an input voltage from 8 V - 28 V to a
fixed output voltage of 5 V.

8.2 Typical Application

8.2.1 TPS54302 8-V to 28-V Input, 5-V Output Converter
U1
TPS54302
VIN= 8V ~ 28V C3
3 VIN 6
VIN BOOT
0.1uF L1 10uH
R4 1 2 VOUT=5V,3A
C1 C2 GND SW VOUT
511l Q R1
10uF 0.1uF C4 C5
49.9 Q
22uF 22uF
5 EN FB 4
R2
C6
100l Q
75pF
R5
105l Q R3
13.3l Q

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Figure 15. 5-V, 3-A Reference Design

8.2.2 Design Requirements

For this design example, use the parameters in Table 1.

Table 1. Design Parameters

PARAMETER VALUE
Input voltage range 8 V to 28 V
Output voltage 5V
Output current 3A
Transient response, 1.5-A load step ΔVOUT = ±5 %
Input ripple voltage 400 mV
Output voltage ripple 30 mVpp
Switching frequency 400 kHz

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8.2.3 Detailed Design Procedure

8.2.3.1 Input Capacitor Selection

The device requires an input decoupling capacitor and a bulk capacitor is needed depending on the application.
A ceramic capacitor over 10 µF is recommended for the decoupling capacitor. An additional 0.1-µF capacitor
(C2) from VIN to GND is optional to provide additional high frequency filtering. The capacitor voltage rating needs
to be greater than the maximum input voltage.
Use Equation 4 to calculate the input ripple voltage (ΔVIN).
IOUT(MAX ) ´0.25
DVIN =
CBULK ´ fsw
(
+ IOUT(MAX ) ´ ESRMAX ) (4)
where:
CBULK is the bulk capacitor value
fSW is the switching frequency
IOUT(MAX) is the maximum loading current
ESRMAX is maximum series resistance of the bulk capacitor
The maximum RMS (root mean square) ripple current must also be checked. For worst case conditions, use
Equation 5 to calculate ICIN(RMS).
IO(MAX)
ICIN(RMS) =
2 (5)
The actual input-voltage ripple is greatly affected by parasitic associated with the layout and the output
impedance of the voltage source. Design Requirements show the actual input voltage ripple for this circuit which
is larger than the calculated value. This measured value is still below the specified input limit of 400 mV. The
maximum voltage across the input capacitors is VIN (MAX) + ΔVIN/2. The selected bypass capacitor is rated for
35 V and the ripple current capacity is greater than 2 A. Both values provide ample margin. The maximum
ratings for voltage and current must not be exceeded under any circumstance.

8.2.3.2 Bootstrap Capacitor Selection

A 0.1-µF ceramic capacitor must be connected between the BOOT to SW pin for proper operation. It is
recommended to use a ceramic capacitor.

8.2.3.3 Output Voltage Set Point

The output voltage of the TPS54302 device is externally adjustable using a resistor divider network. In the
application circuit of Figure 15, this divider network is comprised of R2 and R3. Use Equation 6 and Equation 7
to calculate the relationship of the output voltage to the resistor divider.
R2 ´ Vref
R3 =
VOUT - Vref (6)
é R2 ù
Vout = Vref ´ ê + 1ú
ë R3 û (7)
Select a value of R2 to be approximately 100 kΩ. Slightly increasing or decreasing R3 can result in closer output
voltage matching when using standard value resistors. In this design, R2 = 100 kΩ and R3 = 13.3 kΩ which
results in a 5-V output voltage. The 49.9-Ω resistor, R1, is provided as a convenient location to break the control
loop for stability testing.

8.2.3.4 Undervoltage Lockout Set Point

The undervoltage lockout (UVLO) set point can be adjusted using the external-voltage divider network of R4 and
R5. R4 is connected between the VIN and EN pins of the TPS54302 device. R5 is connected between the EN
and GND pins. The UVLO has two thresholds, one for power up when he input voltage is rising and one for
power down or brown outs when the input voltage is falling. For the example design, the minimum input voltage
is 8 V, so the start voltage threshold is set to 6.74 V and the stop voltage threshold is set to 5.83 V. Use
Equation 1 and Equation 2 to calculate the values for the upper and lower resistor values of R4 and R5.

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8.2.3.5 Output Filter Components

Two components must be selected for the output filter, the output inductor (LO) and CO.

8.2.3.5.1 Inductor Selection

Use Equation 8 to calculate the minimum value of the output inductor (LMIN).

LMIN =
(
VOUT ´ VIN(MAX ) - VOUT )
VIN(MAX ) ´ KIND ´ IOUT ´ fsw
(8)
Where:
KIND is a coefficient that represents the amount of inductor ripple current relative to the maximum output
current.
In general, the value of KIND is at the discretion of the designer; however, the following guidelines may be used.
For designs using low-ESR output capacitors, such as ceramics, a higher KIND can be used. When using higher
ESR output capacitors, KIND = 0.2 yields better results.
For this design example, use KIND = 0.35. The minimum inductor value is calculated as 9.78 μH. For this design,
a close standard value of 10 μH was selected for LMIN.
For the output filter inductor, the RMS current and saturation current ratings must not be exceeded. Use
Equation 9 to calculate the RMS inductor current (IL(RMS)).

( )
2
æ ö
2 1 ç VOUT ´ VIN(MAX ) - VOUT ÷
IL(MAX) = IOUT + ´
(MAX ) 12 ç V ÷
ç IN(MAX ) ´ LOUT ´ fSW ´ 0.8 ÷
è ø (9)
Use Equation 10 to calculate the peak inductor current (IL(PK)).

IL(PK ) = IOUT(MAX ) +
(
VOUT ´ VIN(MAX ) - VOUT )
1.6 ´ VIN(MAX ) ´ LOUT ´ fSW
(10)
Smaller or larger inductor values can be used depending on the amount of ripple current the designer wants to
allow so long as the other design requirements are met. Larger value inductors have lower AC current and result
in lower output voltage ripple. Smaller inductor values increase AC current and output voltage ripple.

8.2.3.5.2 Output Capacitor Selection

Consider three primary factors when selecting the value of the output capacitor. The output capacitor determines
the modulator pole, the output voltage ripple, and how the regulator responds to a large change in load current.
The output capacitance must be selected based on the more stringent of these three criteria.
The desired response to a large change in the load current is the first criterion. The output capacitor must supply
the load with current when the regulator cannot. This situation occurs if the desired hold-up times are present for
the regulator. In this case, the output capacitor must hold the output voltage above a certain level for a specified
amount of time after the input power is removed. The regulator is also temporarily unable to supply sufficient
output current if a large, fast increase occurs affecting the current requirements of the load, such as a transition
from no load to full load. The regulator usually requires two or more clock cycles for the control loop to notice the
change in load current and output voltage and to adjust the duty cycle to react to the change. The output
capacitor must be sized to supply the extra current to the load until the control loop responds to the load change.
The output capacitance must be large enough to supply the difference in current for 2 clock cycles while only
allowing a tolerable amount of drop in the output voltage. Use Equation 11 to calculate the minimum required
output capacitance.

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2 ´ DIOUT
CO >
ƒ sw ´ DVOUT (11)
where:
∆IOUT is the change in output current
ƒSW is the switching frequency of the regulator
∆V(OUT )b is the allowable change in the output voltage
For this example, the transient load response is specified as a 5% change in the output voltage, VOUT, for a load
step of 1.5 A. For this example, ΔIOUT = 1.5 A and ΔVOUT = 0.05 × 5 = 0.25 V. Using these values results in a
minimum capacitance of 30 μF. This value does not consider the ESR of the output capacitor in the output
voltage change. For ceramic capacitors, the ESR is usually small enough to ignore in this calculation.
Equation 12 calculates the minimum output capacitance required to meet the output voltage ripple specification.
In this case, the maximum output voltage ripple is 30 mV. Under this requirement, Equation 12 yields 10.7 μF.
1 1
CO > ´
8 ´ fSW VOUTripple
Iripple (12)
where:
ƒSW is the switching frequency
V(OUTripple) is the maximum allowable output voltage ripple
I(ripple) is the inductor ripple current
Use Equation 13 to calculate the maximum ESR an output capacitor can have to meet the output-voltage ripple
specification. Equation 13 indicates the ESR should be less than 29.2 mΩ. In this case, the ESR of the ceramic
capacitor is much smaller than 29.2 mΩ.
VOUTripple
RESR <
Iripple (13)
The output capacitor can affect the crossover frequency ƒo. Considering to the loop stability and effect of the
internal parasitic parameters, choose the crossover frequency less than 40 kHz without considering the feed
forward capacitor. A simple estimation for the crossover frequency without feed forward capacitor C6 is shown in
Equation 14, assuming COUT has small ESR.
5.1
fo =
VOUT u COUT (14)
Additional capacitance deratings for aging, temperature, and DC bias should be considered which increases this
minimum value. For this example, two 22-uF 25-V, X7R ceramic capacitors are used. Capacitors generally have
limits to the amount of ripple current they can handle without failing or producing excess heat. An output
capacitor that can support the inductor ripple current must be specified. Some capacitor data sheets specify the
RMS value of the maximum ripple current. Use Equation 15 to calculate the RMS ripple current that the output
capacitor must support. For this application, Equation 15 yields 296 mA for each capacitor.

ICOUT(RMS ) =
1
´ç
æ V
(
ç OUT ´ VIN(MAX ) - VOUT ÷ )
ö
÷
12 ç VIN(MAX ) ´ LOUT ´ fSW ´ NC ÷
è ø (15)

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8.2.3.5.3 Feed-Forward Capacitor

The TPS54302 is internally compensated and the internal compensation network is composed of two capacitors
and one resister shown on the block diagram. Depending on the VOUT, if the output capacitor COUT is dominated
by low ESR (ceramic types) capacitors, it could result in low phase margin. To improve the phase boost an
external feedforward capacitor C6 can be added in parallel with R2. C6 is chosen such that phase margin is
boosted at the crossover frequency.
Equation 16 for C6 was tested:
1 1
C6 = u
2Sf o R2 (16)
For this design, C6 = 75 pF. C6 is not needed when COUT has high ESR, and C6 calculated from Equation 16
should be reduced with medium ESR. Table 2 can be used as a starting point.

Table 2. Recommended Component Values

VOUT (V) L (µH) COUT (µF) R2 (kΩ) R3 (kΩ) C8 (pF)
1.8 4.7 66 100 49.9 33
2.5 5.6 66 100 31.6 47
3.3 6.8 44 100 22.1 47
5 10 44 100 13.3 75
12 15 44 100 5.23 100

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8.2.4 Application Curves

100 0.5
90 0.4
80 0.3

Line Regulation (%)

70 0.2
Efficiency (%)

60 0.1
50 0
40 -0.1
30 -0.2
20 -0.3
10 VIN = 24 V, VOUT = 5 V -0.4
VIN = 12 V, VOUT = 5 V
0 -0.5
0.001 0.01 0.1 1 6 8 10 12 14 16 18 20 22 24 26 28
Output Current (A) D013
Input Voltage (V) D014

Figure 16. Efficiency Figure 17. Line Regulation

0.8

0.6 VIN = 200 mV/div (ac coupled)

0.4
Load Regulation (%)

0.2

0
PH = 10 V/div
-0.2

-0.4

-0.6 VIN = 24 V
VIN = 12 V
-0.8
0.1 0.6 1.1 1.6 2.1 2.6 3.1
Output Current (A) D015 Time - 2 ms/div

Figure 18. Load Regulation Figure 19. Input Voltage Ripple

VOUT = 20 mV/div (ac coupled)

VOUT = 20 mV/div (ac coupled)

PH = 10 V/div PH = 10 V/div

Time - 4 ms/div Time - 40 ms/div

IOUT = 0 A IOUT = 10 mA

Figure 20. Output Voltage Ripple Figure 21. Output Voltage Ripple

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VOUT = 20 mV/div (ac coupled)

VOUT = 20 mV/div (ac coupled)

PH = 10 V/div PH = 10 V/div

Time - 4 ms/div Time - 2 ms/div

IOUT = 100 mA IOUT = 1.5 A

Figure 22. Output Voltage Ripple Figure 23. Output Voltage Ripple

VOUT - 20 mV/div (ac coupled)

VOUT = 100 mV/div (ac coupled)

PH = 10 V/div
IOUT = 1 A/div

Time - 200 ms/div Time - 200 ms/div

IOUT = 3 A 0.75 to 2.25-A load step, slew rate = 250 mA/μsec
Figure 24. Transient Response Figure 25. Transient Response

Vin = 10 V/div
Vin = 10 V/div

EN = 2 V/div EN = 2 V/div

Vout = 2 V/div

Vout = 2 V/div

Time - 4 ms/div
Time - 2 ms/div

Figure 26. Start-Up Relative to VIN Figure 27. Shutdown Relative to VIN

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Vin = 10 V/div Vin = 10 V/div

EN = 2 V/div EN = 2 V/div

Vout = 2 V/div

Vout = 2 V/div

Time - 2 ms/div Time - 2 ms/div

Figure 28. Start-Up Relative to EN Figure 29. Shutdown Relative to EN

9 Power Supply Recommendations

The device is designed to operate from an input voltage supply range between 4.5 V and 28 V. This input supply
must be well regulated. If the input supply is located more than a few inches from the device or converter,
additional bulk capacitance may be required in addition to the ceramic bypass capacitors. An electrolytic
capacitor with a value of 47 µF is a typical choice.

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10 Layout

10.1 Layout Guidelines

• VIN and GND traces should be as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation.
• The input capacitor and output capacitor should be placed as close to the device as possible to minimize
trace impedance.
• Provide sufficient vias for the input capacitor and output capacitor.
• Keep the SW trace as physically short and wide as practical to minimize radiated emissions.
• Do not allow switching current to flow under the device.
• A separate VOUT path should be connected to the upper feedback resistor.
• Make a Kelvin connection to the GND pin for the feedback path.
• Voltage feedback loop should be placed away from the high-voltage switching trace, and preferably has
ground shield.
• The trace of the VFB node should be as small as possible to avoid noise coupling.
• The GND trace between the output capacitor and the GND pin should be as wide as possible to minimize its
trace impedance.

10.2 Layout Example

VOUT
GND
Additional
Vias to the Vias to the
OUTPUT
GND plane internal SW
CAPACITOR BOOST
node copper
CAPACITOR

OUTPUT
INDUCTOR

GND VBST
FEEDBACK
TO ENABLE RESISTORS
SW EN CONTROL

Vias to the VFB

VIN VIN
internal SW
node copper INPUT BYPAS
CAPACITOR

SW node copper
pour area on internal
or bottom layer

Figure 30. Board Layout

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11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.2 Trademarks
Eco-mode, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS54302DDCR ACTIVE SOT-23-THIN DDC 6 3000 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 4302
& no Sb/Br)
TPS54302DDCT ACTIVE SOT-23-THIN DDC 6 250 Green (RoHS SN Level-1-260C-UNLIM -40 to 125 4302
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54302DDCR SOT- DDC 6 3000 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
23-THIN
TPS54302DDCT SOT- DDC 6 250 180.0 9.5 3.17 3.1 1.1 4.0 8.0 Q3
23-THIN

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 24-Jul-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54302DDCR SOT-23-THIN DDC 6 3000 184.0 184.0 19.0
TPS54302DDCT SOT-23-THIN DDC 6 250 184.0 184.0 19.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DDC0006A SCALE 4.000
SOT - 1.1 max height
SOT

3.05 1.100
2.55 0.847
1.75 0.1 C
B A
1.45
PIN 1
INDEX AREA

1
6

4X 0.95

3.05
1.9
2.75

4
3

0.5 0.1
6X TYP
0.3 0.0
0.2 C A B

C
0 -8 TYP

SEATING PLANE 0.25

0.20
TYP GAGE PLANE
0.12
0.6
TYP
0.3

4214841/B 11/2020

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC MO-193.

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 EXAMPLE BOARD LAYOUT
DDC0006A SOT - 1.1 max height
SOT

SYMM
6X (1.1)
1

6X (0.6) 6

SYMM

4X (0.95)

4
3

(R0.05) TYP
(2.7)

LAND PATTERN EXAMPLE

EXPLOSED METAL SHOWN
SCALE:15X

METAL UNDER SOLDER MASK

SOLDER MASK METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL

EXPOSED METAL

0.07 MAX 0.07 MIN

ARROUND ARROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDERMASK DETAILS

4214841/B 11/2020

NOTES: (continued)

4. Publication IPC-7351 may have alternate designs.

5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DDC0006A SOT - 1.1 max height
SOT

SYMM
6X (1.1)
1

6X (0.6) 6

SYMM

4X(0.95)

4
3

(R0.05) TYP
(2.7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 THICK STENCIL
SCALE:15X

4214841/B 11/2020

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.

www.ti.com
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