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Day 6

The document provides Verilog HDL code for a module named 'mod_a' that computes two outputs based on four inputs using logical operations. It also includes a testbench for the 'RTL_D6' module, which instantiates 'mod_a' and tests it with various input combinations while monitoring the outputs. The testbench simulates the functionality of the design over a series of time steps.

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gireshramg
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3 views2 pages

Day 6

The document provides Verilog HDL code for a module named 'mod_a' that computes two outputs based on four inputs using logical operations. It also includes a testbench for the 'RTL_D6' module, which instantiates 'mod_a' and tests it with various input combinations while monitoring the outputs. The testbench simulates the functionality of the design over a series of time steps.

Uploaded by

gireshramg
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Day 6:

Verilog HDL Code:

module mod_a (

output out1, out2,

input a, b, c, d

);

assign out1 = (a & b) | (c & d);

assign out2 = (a | b) & (c | d);

endmodule

module RTL_D6 (

input a, b, c, d,

output out1, out2

);

mod_a my_instance (out1, out2, a, b, c, d);

endmodule

Verilog HDL testbench code:

module RTL_D6_tb;

reg a, b, c, d;

wire out1, out2;

RTL_D6 uut (

.a(a), .b(b), .c(c), .d(d),

.out1(out1), .out2(out2)

);

initial begin
$monitor("Time=%0t | a=%b b=%b c=%b d=%b | out1=%b out2=%b", $time, a, b, c, d,
out1,

out2);

a = 0; b = 0; c = 0; d = 0; #10;

a = 0; b = 0; c = 0; d = 1; #10;

a = 0; b = 1; c = 1; d = 1; #10;

a = 1; b = 1; c = 0; d = 0; #10;

a = 1; b = 1; c = 1; d = 1; #10;

$finish;

end

endmodule

Functional Simulation:

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