● List of experiments using gate-level modeling:

1. write a verilog hdl code and its testbench for half-adder

2. write a verilog hdl code and its testbench for 1-bit full-adder
3. write a verilog hdl code and its testbench for half-subtractor
4. write a verilog hdl code and its testbench for 1-bit full-subtractor
5. write a verilog hdl code and its testbench for MUX 2x1
6. write a verilog hdl code and its testbench for 4-to-2 encoder
7. write a verilog hdl code and its testbench for 2-to-4 decoder
8. write a verilog hdl code and its testbench for de-MUX 1x2
9. write a verilog hdl code and its testbench for 1-bit comparator

CODE and TESTBENCH using gate-level modeling:

1. write a verilog hdl code and its testbench for half-adder:

// Half-Adder Module
module half_adder(input a, b, output sum, carry);
xor(sum, a, b);
and(carry, a,
b); endmodule

// Testbench for Half-

Adder module
half_adder_tb;
reg a, b;
wire sum, carry;
 // Instantiate the Half-Adder module
half_adder dut(a, b, sum, carry);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, sum, carry);
$display("A B | Sum Carry");
$display("---------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

Output Waveforms:

RTL Schematic:
2.write a verilog hdl code and its testbench for 1-bit full-adder:

// Full-Adder Module
module full_adder(input a, b, cin, output sum, cout);
wire s1, c1, c2;
xor(s1, a, b);
xor(sum, s1, cin);
and(c1, a, b);
and(c2, s1, cin);
or(cout, c1, c2);
endmodule

// Testbench for Full-

Adder module
full_adder_tb;
reg a, b, cin;
wire sum, cout;

// Instantiate the Full-Adder module

full_adder dut(a, b, cin, sum, cout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, cin, sum, cout);
$display("A B Cin | Sum Cout");
$display("-----------------");
a = 0; b = 0; cin = 0; #10;
a = 0; b = 0; cin = 1; #10;
 a = 0; b = 1; cin = 0; #10;
a = 0; b = 1; cin = 1; #10;
a = 1; b = 0; cin = 0; #10;
a = 1; b = 0; cin = 1; #10;
a = 1; b = 1; cin = 0; #10;
a = 1; b = 1; cin = 1; #10;
$finish;
end
endmodule

Waveforms:

RTL Schematic:
2. write a verilog hdl code and its testbench for half-subtractor:

// Half-Subtractor Module
module half_subtractor(input a, b, output diff, bout);
wire n1, n2;
not(n1, a);
xor(diff, a, b);
and(bout, n1, b);
endmodule

// Testbench for Half-Subtractor

module half_subtractor_tb;
reg a, b;
wire diff, bout;

// Instantiate the Half-Subtractor module

half_subtractor dut(a, b, diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, diff, bout);
$display("A B | Diff Bout");
$display("---------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule
Waveforms:

RTL Schematic:
3. write a verilog hdl code and its testbench for 1-bit full-subtractor:

// Full-Subtractor Module
module full_subtractor(input a, b, bin, output diff, bout);
xor(diff,a,b,bin);
xnor(y1,a,b);
and(y2,bin,y1);
not(y3,a);
and(y4,y3,b);
or(bout,y2,y4);
endmodule
// Testbench for Full-Subtractor
module full_subtractor_tb;
reg a, b, bin;
wire diff, bout;

// Instantiate the Full-Subtractor module

full_subtractor dut(a, b, bin, diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, bin, diff, bout);
$display("A B Bin | Diff Bout");
$display("---------------------");
a = 0; b = 0; bin = 0; #10;
a = 0; b = 0; bin = 1; #10;
a = 0; b = 1; bin = 0; #10;
 a = 0; b = 1; bin = 1; #10;
a = 1; b = 0; bin = 0; #10;
a = 1; b = 0; bin = 1; #10;
a = 1; b = 1; bin = 0; #10;
a = 1; b = 1; bin = 1; #10;
$finish;
end
endmodule
Output:

RTL Schematic:
4. write a verilog hdl code and its testbench for MUX 2x1

// 2x1 Multiplexer (MUX) Module

module mux_2x1(input a, b, sel, output y);
wire w1, w2;

and(w1, a, ~sel);
and(w2, b, sel);
or(y, w1,
w2);
endmodule

// Testbench for 2x1 Multiplexer

module mux_2x1_tb;
reg a, b, sel;
wire y;

// Instantiate the 2x1 Multiplexer module

mux_2x1 dut(a, b, sel, y);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b", a, b, sel, y);
$display("A B Sel | Y");
$display("-----------");
a = 0; b = 0; sel = 0; #10;
a = 0; b = 0; sel = 1; #10;
a = 0; b = 1; sel = 0; #10;
a = 0; b = 1; sel = 1; #10;
 a = 1; b = 0; sel = 0; #10;
a = 1; b = 0; sel = 1; #10;
a = 1; b = 1; sel = 0; #10;
a = 1; b = 1; sel = 1; #10;
$finish;
end
endmodule

Output waveforms:

RTL Schematic:
5. write a verilog hdl code and its testbench for 4-to-2 encoder:

// 4-to-2 Encoder Module

module encoder_4to2(input [3:0] data, output [1:0] y);
or(y[0],data[1],data[3]);
or(y[1],data[2],data[3]);
endmodule

//Testbench module
module encoder_4to2_tb;
reg [3:0] data;
wire [1:0] y;

// Instantiate the 4-to-2 Encoder module

encoder_4to2 dut(data, y);

// Apply stimulus
initial begin
$monitor("%b | %b", data, y);
$display("Data | Y");
$display("-----------");
data = 4'b0000; #10;
data = 4'b0001; #10;
data = 4'b0010; #10;
data = 4'b0011; #10;
data = 4'b0100; #10;
data = 4'b0101; #10;
data = 4'b0110; #10;
data = 4'b0111; #10;
data = 4'b1000; #10;
data = 4'b1001; #10;
data = 4'b1010; #10;
data = 4'b1011; #10;
data = 4'b1100; #10;
 data = 4'b1101; #10;
data = 4'b1110; #10;
data = 4'b1111; #10;
$finish;
end
endmodule
6. write a verilog hdl code and its testbench for 2-to-4 decoder:

// 2-to-4 Decoder Module

module decoder_2to4(din [1:0] data, dout [3:0] y); wire w1, w2;

not (w1, data[0]);

not (w2, data[1]);

and (y[0], w1, w2);

and (y[1], data[0], w2);
and (y[2], w1, data[1]);
and (y[3], data[0], data[1]);

endmodule

// Testbench for 2-to-4 Decoder

`timescale 1ns/1ns
module decoder_2to4_tb;
reg [1:0] data;
wire [3:0] y;

// Instantiate the 2-to-4 Decoder module

decoder_2to4 dut(data, y);

// Apply stimulus
initial begin
$monitor("%b | %b", data, y);
$display("Data | Y");
$display("-----------");
data = 2'b00; #10;
 data = 2'b01; #10;
data = 2'b10; #10;
data = 2'b11; #10;
$finish;
end
endmodule

Out Waveforms:

RTL Schematic
7. write a verilog hdl code and its testbench for de-MUX 1x2:

// 1x2 Demultiplexer (deMUX) Module

module demux_1x2(input a, sel, output y0, y1);
wire w1;
not(w1, sel);
and(y0, a, w1);
and(y1, a, sel);
endmodule

// Testbench
for 1x2 Demultiplexer module
demux_1x2_tb;
reg a, sel;
wire y0, y1;

// Instantiate the 1x2 Demultiplexer module

demux_1x2 dut(a, sel, y0, y1);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, sel, y0, y1);
$display("A Sel | Y0 Y1");
$display("-------------");
a = 0; sel = 0; #10;
a = 0; sel = 1; #10;
a = 1; sel = 0; #10;
a = 1; sel = 1; #10;
$finish;
end
endmodule

8. write a verilog hdl code and its testbench for 1-bit comparator:

// 1-bit Comparator Module

module comparator_1bit(input a, input b, output equal, output greater, output
less); xnor(equal, a, b);
not(bbar,b);
and(greater,a,bbar);
not(abar,a);
and(less,abar,b);
endmodule

// Testbench for 1-bit

Comparator module
comparator_1bit_tb;
reg a, b;
wire equal, greater, less;

// Instantiate the 1-bit Comparator module

comparator_1bit dut(a, b, equal, greater,
less);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b %b", a, b, equal, greater, less);
$display("A B | Equal Greater Less");
$display("-----------------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

● List of experiments using dataflow level modeling:

1. write a verilog hdl code and its testbench for half-adder

2. write a verilog hdl code and its testbench for 1-bit full-adder
3. write a verilog hdl code and its testbench for half-subtractor
4. write a verilog hdl code and its testbench for 1-bit full-subtractor
5. write a verilog hdl code and its testbench for MUX 2x1
6. write a verilog hdl code and its testbench for 4-to-2 encoder
7. write a verilog hdl code and its testbench for 2-to-4 decoder
8. write a verilog hdl code and its testbench for de-MUX 1x2
9. write a verilog hdl code and its testbench for 1-bit comparator

CODE and TESTBENCH using dataflow level modeling:

1. write a verilog hdl code and its testbench for half-adder:

// Half-Adder module
module half_adder(input a, b, output sum, carry);
assign sum = a ^ b;
assign carry = a & b;
endmodule

// Testbench for Half-

Adder module
half_adder_tb;
reg a, b;
wire sum, carry;
 // Instantiate the Half-Adder module
half_adder dut(a, b, sum, carry);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, sum, carry);
$display("A B | Sum Carry");
$display("---------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule

2. write a verilog hdl code and its testbench for 1-bit full-adder:

//1-bit full-adder module

module full_adder(input a, b, cin, output sum, cout);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule

// Testbench for Full-

Adder module
full_adder_tb;
reg a, b, cin;
wire sum, cout;
// Instantiate the Full-Adder module
full_adder dut(a, b, cin, sum, cout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, cin, sum, cout);
$display("A B Cin | Sum Cout");
$display("-----------------");
a = 0; b = 0; cin = 0; #10;
a = 0; b = 0; cin = 1; #10;
a = 0; b = 1; cin = 0; #10;
a = 0; b = 1; cin = 1; #10;
a = 1; b = 0; cin = 0; #10;
a = 1; b = 0; cin = 1; #10;
a = 1; b = 1; cin = 0; #10;
a = 1; b = 1; cin = 1; #10;
$finish;
end
endmodule
 3. write a verilog hdl code and its testbench for half-subtractor:

//Half_subtractor module
module half_subtractor(input a, b, output diff, borrow);
assign diff = a ^ b;
assign borrow = (~a) &
b; endmodule

// Testbench for Half-Subtractor

module half_subtractor_tb;
reg a, b;
wire diff, bout;

// Instantiate the Half-Subtractor module

half_subtractor dut(a, b, diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, b, diff, bout);
$display("A B | Diff Bout");
$display("---------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule
 4. write a verilog hdl code and its testbench for 1-bit full-subtractor:

//1-bit full-subtractor module

module full_subtractor(input a, b, bin, output diff, bout);

assign diff = a ^ b ^ bin;
assign bout = (~a & b) | (~a & bin) | (b & bin);
endmodule

// Testbench for Full-

Subtractor module
full_subtractor_tb;
reg a, b, bin;
wire diff, bout;

// Instantiate the Full-Subtractor module

full_subtractor dut(a, b, bin, diff, bout);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b %b", a, b, bin, diff, bout);
$display("A B Bin | Diff Bout");
$display("--------------------");
a = 0; b = 0; bin = 0; #10;
a = 0; b = 0; bin = 1; #10;
a = 0; b = 1; bin = 0; #10;
a = 0; b = 1; bin = 1; #10;
a = 1; b = 0; bin = 0; #10;
a = 1; b = 0; bin = 1; #10;
a = 1; b = 1; bin = 0; #10;
a = 1; b = 1; bin = 1; #10;
$finish;
end
endmodule
 5. write a verilog hdl code and its testbench for MUX 2x1:

//MUX 2x1 module

module mux_2x1(input d0, d1, sel, output y);
assign y = sel ? d1 : d0;
endmodule

// Testbench for 2x1

Multiplexer module
mux_2x1_tb;
reg a, b, sel;
wire y;

// Instantiate the 2x1 Multiplexer module

mux_2x1 dut(a, b, sel, y);

// Apply stimulus
initial begin
$monitor("%b %b %b | %b", a, b, sel, y);
$display("A B Sel | Y");
$display("----------");
a = 0; b = 0; sel = 0; #10;
a = 0; b = 0; sel = 1; #10;
a = 0; b = 1; sel = 0; #10;
a = 0; b = 1; sel = 1; #10;
a = 1; b = 0; sel = 0; #10;
a = 1; b = 0; sel = 1; #10;
a = 1; b = 1; sel = 0; #10;
a = 1; b = 1; sel = 1; #10;
$finish;
end
endmodule
 6. write a verilog hdl code and its testbench for 4-to-2 encoder:

//encoder_4to2 module
module encoder_4to2(input [3:0] data, output [1:0] y);
assign y[0] = data[1] | data[3] ;
assign y[1] = data[2] | data[3] ;
endmodule

//Testbench module
module encoder_4to2_tb;
reg [3:0] data;
wire [1:0] y;

// Instantiate the 4-to-2 Encoder module

encoder_4to2 dut(data, y);

// Apply stimulus
initial begin
$monitor("%b | %b", data, y);
$display("Data | Y");
$display("------------");
data = 4'b0000; #10;
data = 4'b0001; #10;
data = 4'b0010; #10;
data = 4'b0011; #10;
data = 4'b0100; #10;
data = 4'b0101; #10;
 data = 4'b0110; #10;
data = 4'b0111; #10;
data = 4'b1000; #10;
data = 4'b1001; #10;
data = 4'b1010; #10;
data = 4'b1011; #10;
data = 4'b1100; #10;
data = 4'b1101; #10;
data = 4'b1110; #10;
data = 4'b1111; #10;
$finish;
end
endmodule

7. write a verilog hdl code and its testbench for 2-to-4 decoder:
//decoder_2to4 module
module decoder_2to4(input [1:0] sel, output [3:0] y);
assign y[0] = (~sel[0] & ~sel[1]);
assign y[1] = (sel[0] & ~sel[1]);
assign y[2] = (~sel[0] & sel[1]) ;
assign y[3] = (sel[0] & sel[1]) ;
endmodule

// Testbench for 2-to-4 Decoder

`timescale 1ns/1ns
module decoder_2to4_tb;
reg [1:0] data;
 wire [3:0] y;

// Instantiate the 2-to-4 Decoder module

decoder_2to4 dut(data, y);

// Apply stimulus
initial begin
$monitor("%b | %b", data, y);
$display("Data | Y");
$display("-----------");
data = 2'b00; #10;
data = 2'b01; #10;
data = 2'b10; #10;
data = 2'b11; #10;
$finish;
end
endmodule

8. write a verilog hdl code and its testbench for de-MUX 1x2:

//de-mux 1x2 module

module demux_1x2(input d, sel, output y0, y1);
assign y0 = sel ? 1'b0 : d;
assign y1 = sel ? d : 1'b0;
endmodule
// Testbench for 1x2 Demultiplexer
module demux_1x2_tb;
reg a, sel;
wire y0, y1;

// Instantiate the 1x2 Demultiplexer module

demux_1x2 dut(a, sel, y0, y1);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b", a, sel, y0, y1);
$display("A Sel | Y0 Y1");
$display("-------------");
a = 0; sel = 0; #10;
a = 0; sel = 1; #10;
a = 1; sel = 0; #10;
a = 1; sel = 1; #10;
$finish;
end
endmodule
9. write a verilog hdl code and its testbench for 1-bit comparator:
//comparator_1bit module
module comparator_1bit(input a, b, output less, equal,
greater); assign less = (a < b) ? 1'b1 : 1'b0;
assign equal = (a == b) ? 1'b1 : 1'b0;
assign greater = (a > b) ? 1'b1 : 1'b0;
endmodule
// Testbench for 1-bit Comparator
module comparator_1bit_tb;
reg a, b;
wire equal, greater, less;

// Instantiate the 1-bit Comparator module

comparator_1bit dut(a, b, equal, greater, less);

// Apply stimulus
initial begin
$monitor("%b %b | %b %b %b", a, b, equal, greater, less);
$display("A B | Equal Greater Less");
$display("------------------------");
a = 0; b = 0; #10;
a = 0; b = 1; #10;
a = 1; b = 0; #10;
a = 1; b = 1; #10;
$finish;
end
endmodule