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Abstract

The document presents an FPGA-based digital payment system designed using Verilog, focusing on secure and offline transaction capabilities without reliance on cloud infrastructure. It simulates core UPI functionalities through Finite State Machines for user authentication, fund transfers, balance inquiries, and administrative tasks. This project aims to provide a reliable payment solution, particularly in rural or educational settings, highlighting the importance of decentralized financial systems.

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Siddardha P
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3 views1 page

Abstract

The document presents an FPGA-based digital payment system designed using Verilog, focusing on secure and offline transaction capabilities without reliance on cloud infrastructure. It simulates core UPI functionalities through Finite State Machines for user authentication, fund transfers, balance inquiries, and administrative tasks. This project aims to provide a reliable payment solution, particularly in rural or educational settings, highlighting the importance of decentralized financial systems.

Uploaded by

Siddardha P
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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FPGA-Based Digital Payment System Using Verilog

Abstract:
In an era increasingly dominated by digital finance, the development of secure, accessible, and
hardware-efficient transaction systems is essential. Unlike conventional digital payment solutions that
rely on cloud infrastructure, mobile connectivity, and centralized databases that pose latency, privacy,
and accessibility limitation but, FPGA-based systems offer deterministic execution, offline operation,
and real-time responsiveness. Field-Programmable Gate Arrays (FPGAs) enable hardware-level
customization, high parallelism, and low-power operation, making them ideal for embedded
applications in resource-constrained or connectivity-limited environments. This project leverages
these advantages to present the design and implementation of a PhonePe-inspired digital payment
system using Verilog Hardware Description Language (HDL) on an FPGA platform.

Motivated by the growing need for decentralized and infrastructure-independent transaction system
especially in rural or educational settings, the project simulates core UPI-based functionalities
completely in hardware. According to the Reserve Bank of India, over 14 billion digital payment
transactions were recorded in a single month in 2024, underscoring the critical societal role of such
systems. Our implementation eliminates the need for internet connectivity, smartphones, or cloud
dependencies, thereby providing a reliable and secure offline payment platform.

The architecture is centered around Finite State Machines (FSMs) that manage the complete
transaction pipeline. The system includes:

• User Login FSM: Facilitates secure user authentication through switch-based inputs mapped
to predefined IDs.

• Transfer FSM: Oversees balance validation and inter-user fund transfer, dynamically updating
account values stored in on-chip RAM.

• Balance Inquiry FSM: Accesses and displays current balances using Binary-to-BCD logic for
output on a 4-digit 7-segment display.

• Admin FSM: Supports administrative operations like balance top-ups, debug controls, and
account resets, enhancing maintainability.

Inputs are processed via switches and push buttons, while outputs are displayed in real-time through
a 7-segment interface capable of both numeric and scrolling alphanumeric display that can be Fully
synthesizable and implemented on the Boolean Board.

In conclusion, this project demonstrates a viable alternative to traditional digital payment


architectures by offering a standalone, secure, and offline transaction system grounded in digital
design theory. It showcases the practical integration of FSM modeling, memory interfacing, BCD
conversion, and FPGA-based synthesis, contributing both to embedded systems innovation and
educational enrichment.

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