Design and Analysis of NAND, NOR&XOR Circuits Using

Modified Feedback Sleeper Stack Technique

A Major Project Report
Submitted to

Jawaharlal Nehru Technological University Hyderabad

In partial fulfillment of the requirements for the

award of the degree of

BACHELOR OF TECHNOLOGY
in

ELECTRONICS & COMMUNICATION ENGINEERING

By
BUKHYA BHAVANI (21VE1A0476)
JAKKULA MAHESH (21VE1A0491)
ELKANTI SRITEJA (21VE1A04C2)
Under the Guidance of

Ms.M.Bhavana
Asst Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Approved by AICTE, New Delhi | Affiliated to JNTUH, Hyderabad | Accredited by NAAC “A” Grade & NBA
|Hyderabad | PIN: 500068
(2021 – 2025)
 Design and Analysis of NAND, NOR&XOR Circuits Using
Modified Feedback Sleeper Stack Technique
A Major Project Report
Submitted to

Jawaharlal Nehru Technological University Hyderabad

In partial fulfillment of the requirements for the

award of the degree of

BACHELOR OF TECHNOLOGY
in

ELECTRONICS & COMMUNICATION ENGINEERING

By
BUKHYA BHAVANI (21VE1A0476)
JAKKULA MAHESH (21VE1A0491)
ELKANTI SRITEJA (21VE1A04C2)
Under the Guidance of
Ms.M.Bhavana
Asst Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Approved by AICTE, New Delhi | Affiliated to JNTUH, Hyderabad | Accredited by NAAC “A” Grade & NBA|
Hyderabad | PIN: 500068
(2021 – 2025)
 DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Approved by AICTE, New Delhi | Affiliated to JNTUH, Hyderabad | Accredited by NAAC “A” Grade & NBA|
Hyderabad | PIN: 500068

Certificate
This is to certify that the Major Project Report on “Design and Analysis of NAND,

NOR&XOR Circuits Using Modified Feedback Sleeper Stack Technique”

submitted by Bukhya Bhavani, Jakkula Mahesh, Elkanti Sriteja bearing Hall Ticket
No’s 21VE1A0476, 21VE1A0491, 21VE1A04C2 in partial fulfilment of the requirements for
the award of the degree of Bachelor of Technology in Electronics & Communication
Engineering from Jawaharlal Nehru Technological University, Kukatpally, Hyderabad
for the academic year 2024-25 is a record of bonafide work carried out by her under our
guidance and Supervision.

Guide Head of the Department

Ms.M.Bhavana

Project Coordinator Signature of the External Examiner

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Approved by AICTE, New Delhi | Affiliated to JNTUH, Hyderabad | Accredited by NAAC “A” Grade & NBA|
Hyderabad | PIN: 500068

DECLARATION

We, BUKHYA BHAVANI, JAKKULA MAHESH, ELKANTI SRITEJA bearing Roll

No’s 21VE1A0476, 21VE1A0491, 21VE1A04C2 hereby declare that the Project titled
“DESIGN AND ANALYSIS OF NAND, NOR &XOR CIRCUITS USING MODIFIED
FEEDBACK SLEEPER STACK TECHNIQUE” done by us under the guidance of

Ms.M.Bhavana, which is submitted in the partial fulfillment of the requirement for

the award of the B.Tech degree in Electronics & Communication Engineering at
Sreyas Institute of Engineering & Technology for Jawaharlal Nehru Technological
University, Hyderabad is our original work.

BUKHYA BHAVANI(21VE1A0476)
JAKKULA MAHESH (21VE1A0491)
ELKANTI SRITEJA(21VE1A04C2)
 ACKNOWLEDGEMENT

The successful completion of any task would be incomplete without mention of the
people who made it possible through their guidance and encouragement crowns all the
efforts with success.

We take this opportunity to acknowledge with thanks and deep sense of gratitude
to Ms.M.Bhavana , Asst Professor, and Department of ECE for her constant
encouragement and valuable guidance during this work.

A Special note of Thanks to Mr. Ch S V Maruthi Rao, Associate Professor and

Head of the Department, who has been a source of Continuous motivation and support
in the completion of this project. He had taken time and effort to guide and correct us all
through the span of this work.

We owe very much to the Department Faculty, Principal and the Management
who made our term at Sreyas a Stepping stone for our career. We treasure every moment
we had spent in the college.

Last but not least, our heartiest gratitude to our parents and friends for their
continuous encouragement and blessings. Without their support this work would not have
been possible.

BUKHYA BHAVANI (21VE1A0476)

JAKKULA MAHESH (21VE1A0491)

ELKANTI SRITEJA (21VE1A04C2)

 i
ABSTRACT

The growing demand for energy-efficient electronic devices

continues to surge, low power VLSI design has become prominent
in modern semiconductor technology. One of the most significant
challenges in achieving low power consumption is mitigating
leakage currents, which have become a substantial contributor to
power dissipation in nanoscale CMOS circuits. This project
introduces a novel approach for leakage reduction in VLSI designs
by using NAND logic gates. This is also possible by using NOR and
XOR logic gates. The technique builds upon the principles of
traditional stackbased sleep transistors to suppress leakage
currents in standby mode but introduces innovative modifications
for enhanced efficiency. By strategically combining feedback
mechanisms with sleep transistors, this method will achieve
significant leakage reduction while maintaining excellent area and
performance characteristics. These logic circuits implemented
using 18nm technology in microwind tool. The design matrics like
area delay, power and power delay product will be compared for
NAND, NOR, XOR logic circuits.

Keywords: Low power VLSI design, Leakage power reduction,

Modified feedback sleeper stack technique, Sleep transistor, Area
efficiency, Performance optimization
 ii
LIST OF FIGURES

Fig. 3.1: DSCH default window ................................. ………….16

Fig. 3.2: CMOS inverter without connections....... ………………17

Fig. 3.3: CMOS inverter with connections................................17

Fig. 3.4: Circuit with led glow ...................... …………………….18

Fig. 3.5: Functionality of the circuit…………………………………18

Fig. 3.6: Timing diagram......................... …………………………19

Fig. 3.7: Microwind default window..................... ………………19

Fig. 3.8: Design rule file.... ……………………………………………20

Fig. 3.9: NMOS&PMOS transistors……………………….…………20

Fig. 3.10: Interconnections of metal layer………………………….21

Fig. 3.11: Layers with contact cut....................................…….21

Fig. 3.12: Adding input to ploy layer………………………………..22

Fig. 3.13: Simulation result………………………………………… 22

Fig. 3.14: r510 minimum metal area......................... …………23

Fig. 5.1: Circuit Diagram Of Proposed MFSS technique……….28

Fig. 5.2: NAND 3 Gate Using MFSS…………………………………32

Fig. 5.3: NOR Gate Using MFSS……………………………………..34

Fig. 5.4: XOR Gate Using MFSS……………………………………. 35

Fig. 7.1: Schematic of NAND gate…………………………………..39
Fig. 7.2: Timing diagram of NAND gate……………………………40
Fig. 7.3: Truth table of NAND gate………………………………….41
Fig. 7.4: Schematic of NOR gate…………………………………….42
Fig. 7.5: Timing diagram of NOR gate……………………………..43
Fig. 7.6: Truth table of NOR gate……………………………………44
Fig. 7.7: Schematic of XOR gate…………………………………….45
Fig. 7.8: Timing diagram of XOR gate……………………………..46
Fig. 7.9: Truth table of XOR gate……………………………………46
Fig. 7.10: Simulation of NAND gate………………………………….47
Fig. 7.11: Simulation of NOR gate…………………………………..48
Fig. 7.12: Simulation of XOR gate…………………………………..48
Fig. 7.13: Values of power& delay with MFSS technique………49
Fig. 7.14: Values of power& delay without MFSS technique….49
 1
CHAPTER 1

INTRODUCTION

1.1 INTRODUCTION

The rapid advancement of Very Large Scale Integration (VLSI)

technology has enabled the development of smaller, faster, and
more power-efficient electronic devices. However, as transistor
sizes continue to shrink, leakage current has emerged as a
significant concern in modern VLSI designs. Leakage current,
which flows through transistors even when they are turned off,
can account for up to 50% of total power consumption in some
designs.
The increasing importance of leakage current reduction can be
attributed to several factors. Firstly, leakage current contributes
significantly to power consumption, leading to reduced battery
life, increased heat generation, and higher energy costs. Secondly,
excessive leakage current can cause reliability issues, such as
transistor wear-out, oxide breakdown, and electro- migration.
Finally, leakage current can also impact circuit performance,
causing delays, glitches, and errors.
To mitigate these issues, various leakage reduction techniques
have been proposed, including transistor sizing, threshold voltage
adjustment, and sleep transistor insertion. However, these
techniques often come with significant area, delay, and power
overheads, making them less effective in modern VLSI designs.
Recently, the feedback sleeper stack approach has gained
attention as a promising solution for leakage current reduction.
This approach leverages a feedback mechanism to monitor and
control leakage current, while a sleeper stack is used to
disconnect power supply during standby modes.
The feedback sleeper stack approach offers several advantages,
including reduced leakage current, improved power efficiency,
and increased reliability.
 2
Leakage current reduction refers to the process of minimizing or
eliminating unwanted electric current that flows through
unintended paths in electronic devices, circuits, or systems.
This current, often called leakage current, occurs in components
like transistors, diodes, capacitors, and insulating materials,
even when they are supposed to be in an "off" state.
Leakage current is often a consequence of physical properties of
materials, defects in components, or imperfect isolation between
conductive elements.
Key Points of Leakage Current Reduction Power
Consumption: Leakage currents contribute to power loss,
impacting the energy efficiency of devices, particularly in low-
power applications such as mobile devices and battery- operated
systems.
Heat Generation: Leakage currents can lead to unnecessary heat
generation, reducing the overall performance and lifespan of
electronic systems.
Signal Integrity: In sensitive circuits, leakage currents can
distort signals and affect the accuracy of operations, leading to
errors or malfunctions.

KEY FEATURES

Feedback Mechanism:
The approach uses a feedback mechanism to monitor and
control leakage current. The feedback mechanism is designed
to detect changes in leakage current and adjust the sleeper stack
accordingly.
Sleeper Stack:
The approach uses a sleeper stack to disconnect power supply
during standby modes. The sleeper stack is designed to reduce
leakage current by disconnecting power supply to idle circuits.
 3
Leakage Current Monitoring:
The approach monitors leakage current in real-time, allowing for
dynamic adjustment of the sleeper stack. This ensures that
leakage current is minimized during standby modes.
Low Power Consumption:
The approach reduces power consumption during standby modes
by disconnecting power supply to idle circuits.
Improved Reliability:
The approach improves reliability by reducing leakage current
during standby modes. This reduces the risk of transistor wear-
out, oxide breakdown, and electro-migration.
Scalability:
The approach is scalable and can be applied to large-scale VLSI
designs.
Area Efficiency:
The approach is area-efficient and does not require significant
additional area.
Delay Efficiency:
The approach is delay-efficient and does not introduce significant
delay.
Low Overhead:
The approach has low overhead in terms of area, delay, and power
consumption.
High Accuracy:
The approach has high accuracy in terms of leakage current
monitoring and reduction.

1.2 OBJECTIVE

Minimize Leakage Current:

Reduce the leakage current in VLSI circuits to decrease power
consumption and heat generation.
 4
Improve Power Efficiency:
Enhance the power efficiency of VLSI circuits by reducing
leakage current and minimizing power waste.
Increase Circuit Reliability:
Improve the reliability of VLSI circuits by reducing leakage
current, which can cause transistor wear-out and oxide
breakdown.
Reduce Standby Power Consumption:
Minimize standby power consumption in VLSI circuits by using
the feedback sleeper stack approach.
Decrease Active Power Consumption:
Reduce active power consumption in VLSI circuits by optimizing
the feedback sleeper stack approach.
Improve Circuit Performance:
Enhance the performance of VLSI circuits by reducing leakage
current and minimizing delay.
Reduce Area Overhead:
Minimize the area overhead of the feedback sleeper stack
approach to reduce the overall area of VLSI circuits.
Develop a Design Flow:
Develop a design flow for implementing the feedback sleeper stack
approach in VLSI circuits.
Evaluate the Performance:
Evaluate the performance of the feedback sleeper stack approach
in reducing leakage current and improving power efficiency.

1.3 SCOPE

Increasing Demand for Energy-Efficient Systems:

As the demand for energy-efficient systems continues to grow, the
MFSS technique will play a crucial role in reducing power
consumption and heat generation in VLSI circuits.
 5
Emergence of New Technologies:
The MFSS technique will be essential for the development of new
technologies such as quantum computing, nanotechnology, and
synthetic biology, which require highly efficient and reliable VLSI
circuits.
Growing Importance of IoT and AI:
The MFSS technique will be critical for the development of IoT and
AI systems, which require low-power and high-performance VLSI
circuits to process and analyze large amounts of data.
Increasing Complexity of VLSI Circuits:
As VLSI circuits become increasingly complex, the MFSS
technique will be necessary to reduce power consumption and
heat generation, while improving performance and reliability.
Growing Demand for Autonomous Systems:
The MFSS technique will be critical for the development of
autonomous systems, such as self-driving cars and drones, which
require low-power and high-performance VLSI circuits to process
and analyze large amounts of data.
Need for High-Temperature Operating VLSI Circuits:
The MFSS technique will be essential for the development of high-
temperature operating VLSI circuits, which are critical for
applications such as aerospace and automotive.
Growing Demand for Neuromorphic Computing:
The MFSS technique will be critical for the development of
neuromorphic computing systems, which require low-power and
high-performance VLSI circuits to mimic the behavior of biological
neurons.

1.4 MOTIVATION

The increasing demand for smaller, faster, and more power-

efficient electronic devices has led to a significant reduction in
transistor sizes, resulting in a substantial increase in leakage
current.
 6
This, in turn, has become a major concern for Very Large Scale
Integration (VLSI) circuit designers, as it not only leads to
increased power consumption but also affects the reliability and
performance of the circuit.
The motivation behind reducing leakage current is driven by the
growing demand for energy-efficient electronics, especially in
mobile and portable devices, where battery life and heat
management are crucial.
Additionally, minimizing leakage current helps in improving
system reliability, reducing energy waste, and enhancing the
environmental sustainability of electronic technologies. As
components continue to shrink and devices become more
powerful, controlling leakage current is essential for maintaining
the desired performance levels in nextgeneration electronics. The
motivation for reducing leakage current in electronic devices
stems from several key factors:

Environmental Impact:
As global energy consumption increases, there is growing
pressure to design energy-efficient electronic systems.
Reducing leakage currents contributes to the broader goal of
minimizing energy waste and supporting sustainable
technological growth.
Performance Optimization:
Leakage currents can interfere with the integrity of signals in
sensitive circuits, affecting the overall performance and reliability
of systems. For high-performance applications such as
microprocessors and memory devices, reducing leakage current
ensures better signal fidelity and minimizes errors.
Challenges Leakage Current:
The increasing leakage current in VLSI circuits has become a
significant challenge, leading to increased power consumption
and reduced battery life.
 7
Power Consumption:
The growing demand for mobile and portable devices has made
power consumption a critical concern, as it directly affects battery
life and overall system performance.
Reliability:
The increasing leakage current can also lead to reduced reliability,
as it can cause transistor wear-out, oxide breakdown, and electro-
migration.
Opportunities
Improved Power Efficiency:
Reducing leakage current can lead to improved power efficiency,
enabling the development of smaller, faster, and more power-
efficient electronic devices.

Increased Reliability:
Minimizing leakage current can also improve reliability, reducing
the risk of transistor wear-out, oxide breakdown, and electro-
migration.

1.5 THESIS ORGANIZATION

This project work is laid out as follows:

chapter 1: comprises of an introduction, scope of project, objective
of project and motivation of project. chapter 2, a literature part is
presented and getting important data about the status. chapter 3,
software installation is presented. chapter 4, existing techniques
is addressed and proposed technique are given in chapter 5.
Chapter 6, simulation results is presented. chapter 7, advantages
& applications is presented. chapter 8, conclusion& future scope
is given.

1.6 SUMMARY

Introduction:
Leakage current refers to the undesired flow of electric current
through unintended paths in electronic components, even when
they are meant to be in an "off" state.
 8
In modern electronic devices, especially in miniaturized integrated
circuits (ICs) and semiconductor systems, leakage current has
become a significant concern due to smaller component sizes,
increasing performance demands, and energy efficiency
requirements.

Objective:
The main objective of leakage current reduction is to minimize or
eliminate these unwanted currents, thereby improving the overall
performance, power efficiency, and longevity of electronic devices.
This includes reducing power consumption, limiting heat
generation, and preventing signal distortion, which could
otherwise affect the functionality of the system.
Scope:
It involves applying advanced materials, optimized circuit design,
and innovative semiconductor technologies like high-k dielectrics,
FinFET transistors, power gating, and other power-saving
techniques to mitigate leakage effects.
Motivation:
The motivation behind reducing leakage current is driven by the
growing demand for energy-efficient electronics, especially in
mobile and portable devices, where battery life and heat
management are crucial.
Additionally, minimizing leakage current helps in improving
system reliability, reducing energy waste, and enhancing the
environmental sustainability of electronic technologies.
As components continue to shrink and devices become more
powerful, controlling leakage current is essential for maintaining
the desired performance levels in next generation electronics.
 9
CHAPTER 2

LITERATURE SURVEY

2.1 SRAM Cells & Leakage Reduction:

Static Random-Access Memory (SRAM) cells are vital components

in modern VLSI circuits, widely used in processors, caches, and
memory-intensive applications. As device dimensions shrink to
nanoscale levels, leakage power dissipation has become a critical
concern for SRAM designs. Reducing leakage power is particularly
important for achieving energy efficiency, prolonging battery life in
portable devices, and managing heat dissipation. Over the years,
researchers have proposed several innovative techniques to
address these challenges, focusing on optimizing SRAM cells for
low-leakage performance without compromising stability and
speed.

2.2 7T SRAM Cell for FinFET Technology

T. Santosh Kumar and Suman Lata Tripathi introduced a

groundbreaking 7T SRAM cell design leveraging FinFET
technology at an 18nm node. This approach incorporated the Self-
Controllable Voltage Level (SVL) technique to minimize leakage
power effectively. The novel design achieved an unprecedented
reduction in leakage current and power, with leakage current
recorded at just 16.56 nA and leakage power at 11.59 nW. These
results, achieved through simulations in Cadence Virtuoso,
demonstrated the potential of FinFET technology in creating ultra-
low-power SRAM designs.

2.3 Source-Biased SRAM Design

R. Krishna and Punithavathi Duraiswamy proposed an innovative

source-biased inverter configuration for SRAM cells. By adding two
transistors to control leakage, the design effectively minimized
 10
static power dissipation while maintaining dynamic power levels.
The approach led to a 66.1% reduction in leakage power at 32nm
technology, and its performance was further validated at 22nm
and 16nm nodes. When integrated into a 10T SRAM architecture,
the design showcased remarkable improvements, including an
86.24% leakage power reduction and enhanced stability compared
to traditional 6T SRAM cells.
Conclusion
SRAM cells play a pivotal role in modern electronic systems, and
their optimization for leakage reduction is essential for achieving
energyefficient designs. Techniques like the 7T SRAM, source-
biased designs, and diode clamping have demonstrated significant
improvements in minimizing leakage power while ensuring
stability and performance. However, ongoing research is required
to address the challenges of scalability, area efficiency, and
reliability.

2.4 CMOS Domino Logic & Reduction

CMOS domino logic is widely used in high-performance digital

circuits due to its high speed and compact design. These circuits
are integral to processors, signal processing units, and memory
modules, where rapid switching and low delay are critical.
However, as technology nodes shrink, leakage power dissipation
has emerged as a significant challenge, undermining the efficiency
of CMOS domino logic. This has led researchers to focus on
advanced techniques to mitigate leakage power while maintaining
the performance advantages of domino logic circuits.

2.5 KLECTOR Approach for Leakage Control

Ananth Kumar Tamilarasan et al. introduced the KLECTOR

technique to reduce leakage currents in CMOS domino logic
circuits. This method utilizes a "keeper" transistor configuration
 11
that restricts leakage currents during standby operation. By
leveraging a selfcontrolled transistor at the output node, the
KLECTOR approach ensures minimal voltage drops and reduced
leakage power. It was particularly effective in SRAM applications,
where it significantly enhanced energy efficiency during idle states.

2.6 Advanced Clock Gating Techniques

C. Ashok Kumar and colleagues proposed an enhanced clock

gating strategy to improve the power efficiency of sequential
circuits and SRAM designs. This approach introduced a D-latch
model combined with an extended clock gating mechanism to
minimize unnecessary clock switching activity. The innovation
included buffer circuits between source and load, which further
reduced power dissipation by addressing glitches and high
clocking activity. This method proved effective in reducing dynamic
and leakage power in CMOS domino circuits.
Conclusion
CMOS domino logic circuits are indispensable for high-speed and
high-performance applications. Innovative techniques like Gated
Leakage Transistors, the KLECTOR approach, and advanced clock
gating have demonstrated significant potential in reducing leakage
power while maintaining circuit efficiency. However, further
research is necessary to address challenges related to complexity,
scalability, and performance trade-offs. The development of novel,
scalable, and energy-efficient solutions will be crucial for the
continued evolution of CMOS domino logic in the era of nanoscale
technology.

2.7 Innovative Circuit Techniques:

Leakage power reduction has become a cornerstone of modern

VLSI design as device scaling to nanoscale dimensions increases
the prevalence of leakage currents. Traditional approaches, while
effective in specific contexts, often face limitations in scalability,
 12
efficiency, or applicability to advanced technology nodes. To
address these challenges, researchers have proposed a range of
innovative circuit techniques that leverage new configurations,
mechanisms, and strategies to achieve substantial reductions in
leakage power while preserving performance.

2.8 Charge Pump-Based Domino Logic

Karthikeyan and his team proposed a charge pump-based domino

logic circuit to address the leakage challenges in high fan-in gates.
This technique controls the keeper transistor's input through a
charge pump circuit, effectively minimizing leakage during
standby mode. When applied to domino OR gates, the approach
demonstrated a lower power-delay product compared to traditional
methods like regular domino logic or high-speed domino
configurations. The scalability of this method makes it a viable
solution for complex digital systems with high fan-in
requirements.

2.9 Cascaded Leakage Control Transistors (CLCT)

Kajal and Vijay Kumar Sharma developed the Cascaded Leakage

Control Transistor (CLCT) technology, a method designed to
reduce leakage power in both active and standby modes. The
technique leverages a series of transistors that selectively control
the leakage path based on circuit activity. CLCT demonstrated a
remarkable
34.14% improvement in energy efficiency for static and domino
logic circuits, particularly at 16nm and 14nm nodes. This
approach underscores the importance of designing methods that
scale effectively with shrinking technology nodes.
Conclusion
Innovative circuit techniques, including power gating, charge
pumpbased logic, and dynamic stacking, have made significant
strides in addressing leakage power challenges in VLSI design.
 13
These methods not only reduce static power dissipation but also
enhance the scalability and efficiency of circuits across a range of
applications. Continued advancements in these areas will play a
crucial role in enabling the next generation of energy-efficient
electronic devices, ensuring their viability in an era of shrinking
technology nodes and growing computational demands.

2.10 FinFET Technology: A Breakthrough in Low-Power Design

FinFET technology has been a game-changer for mitigating

leakage power in advanced nodes. Unlike traditional planar CMOS
transistors, FinFETs utilize a three-dimensional structure with a
finshaped channel. This design increases the effective channel
width and improves electrostatic control over the gate, significantly
reducing leakage currents.
Sandeep Garg and Tarun K. Gupta leveraged FinFET technology
to develop Series-Connected Dynamic Node-Driven Transistor
Domino Logic (SCDNDTDL). This technique effectively reduced
power dissipation by 73.16% in short-gate (SG) mode and 68.47%
in lowpower (LP) mode, demonstrating the potential of FinFETs for
ultralow-power applications.

2.11 Dynamic Logic Circuits and Stacking Techniques

Fahim Abrar and colleagues introduced a novel approach for wide

fan-in gates using dynamic stacking techniques in pull-down
networks (PDN). By optimizing the stacking effect circuitry, they
achieved an 18% reduction in leakage power. This method is
particularly effective in high-density designs, where managing
leakage becomes increasingly complex.
Similarly, Md Maharaj Kabir et al. developed dynamic logic circuits
that incorporated delay components to mitigate leakage currents.
This approach proved highly effective at 45nm nodes, achieving
significant reductions in both leakage power and propagation
delay. These techniques highlight the importance of rethinking
 14
circuit architectures to address leakage challenges in advanced
nodes.
Challenges in Advanced CMOS Nodes
Despite the successes of FinFET and advanced CMOS techniques,
several challenges remain. One of the most pressing issues is
bandto-band tunneling leakage, which arises due to high doping
concentrations in scaled devices. This effect contributes to
additional power dissipation and complicates leakage
management. Additionally, advanced nodes are more susceptible
to Negative Bias Temperature Instability (NBTI) and Hot Carrier
Injection (HCI), which degrade transistor performance over time.
Conclusion
FinFET technology and advanced CMOS techniques have
significantly advanced the state of leakage reduction in VLSI
circuits. By addressing the challenges posed by scaling to
nanoscale dimensions, these innovations enable energy-efficient
designs that meet the demands of modern electronic applications.
While challenges such as band-to-band tunneling and increased
design complexity persist, ongoing research and development in
this field hold the promise of unlocking new frontiers in low-power
semiconductor technology.
2.12 Summary:

Summary of the Literature Survey

The literature survey provides an overview of various techniques
and advancements in leakage reduction for low-power VLSI
designs. Researchers have proposed innovative approaches,
including SRAM optimizations, dynamic logic enhancements, and
transistor-based methods, to mitigate leakage currents. Key
techniques highlighted include:
1. SRAM Optimizations: Innovations like 7T SRAM cells,
sourcebiased designs, and diode clamping have demonstrated
significant leakage power reductions, especially in nanoscale
FinFET and CMOS technologies.
 15
2. CMOS Domino Logic: Techniques such as Gated Leakage
Transistors (GLTs) and the KLECTOR approach have improved
leakage performance in dynamic logic circuits while addressing
challenges like power delay trade-offs.
3. Advanced Circuit Techniques: Power gating, charge-pump
based logic, and stacking effects have been applied to reduce
leakage in high fan-in and sequential circuits, enhancing power
efficiency and scalability.
4. FinFET and Nanoscale Nodes: Advanced nodes have driven
the development of techniques like Cascaded Leakage Control
Transistors (CLCT) and series-connected FinFET transistors,
achieving substantial energy efficiency improvements.
 16
CHAPTER 3

SOFTWARE INSTALLATION

3.1 Introduction & Installation

Digital schematic circuit (DSCH)

DSCH is software for logic design. Based on primitives, a
hierarchical circuit can be built and simulated. It also includes
delay and power consumption evaluation. With the help of this
software one can implement digital circuits at its basic gate
primitives or at its transistor level.
The following step by step procedure gives you how to use this
software to implement circuits at transistor level.
1.To open the software double click on the DSCH icon on your
desktop

It opens the default window as shown below

Fig:3.1 dsch default window

2.To design the circuit, select the necessary components which are
shown in symbol library on right hand side and drag and drop on
the work area, use buttons for input and LED for output and also
 17
insert VDD and GND which are also part of symbol library as
shown below.

Fig:3.2 cmos inverter without connections

3. Made the interconnections as per the circuit diagram using add
a line option.

Fig:3.3 cmos inverter with connections

4.Now to observe the functionality of the circuit, run simulation
using the icon.
 18

Fig:3.4 circuit with led glow

When LED glow, it indicates a high output, that’s what the
functionality of inverter with low input it produces a high output,we
can change the input to high also which produces a low output as
shown below.

Fig:3.5 functionality of the circuit

5.We can also obtain the response in wave forms also, after
completion of simulation click on the icon.

Fig:3.6 timing diagram

 19
After successful completion of circuit design, we will go for layout
design using the schematic as reference in microwind 3.1 software
tool.
Microwind 3.1
Microwind is a tool for designing and simulating circuits at layout
level. The tool features full editing facilities (copy, cut, paste,
duplicate, move), various views (MOS characteristics, 2D cross
section. 3D process viewer), and an analog simulator.
1.To open the software double click on the microwind 3.1 icon on
your desktop.

It opens the default window as shown below

Fig:3.7 microwind default window

On the right hand side it contains all the necessary layers used in
layout design under palette window.
2. Before start designing the layout, select the design rule file as
follows, file select foundry choose default.rul
 20

Fig:3.8 design rule file

3. To design an inverter we need two transistors NMOS AND PMOS,
a MOS transistor is formed when a poly silicon layer is crossed with
diffusion layer.

Fig:3.9 NMOS&PMOS transistors

4. The poly silicon layer indicates gate terminal, where the diffusion
layer ends acts as source and drain which are interchangeable.
Now the interconnections can be completed by using metal1 layer
as shown.
 21

Fig:3.10 interconnections of metal layer

5.Now to join different layers use contact cuts, as given in palette
window.

Fig:3.11 layers with contact cut

6.Now add input to ploy layer, by choosing add pulse, for output
add a visible node at drain-drain contact metal layer as shown
below.
 22

Fig:3.12 adding input to ploy layer

7.Now run the simulation by using the icon.

Fig:3.13 simulation result

Layout design rules
N-well
r101 minimum width 10lamda
r102 between wells 10lamda
r110 minimum well area 144lamda square
 23
Diffusion
r201 minimum N+ and P+ diffusion width 4lamda
r202 between two P+ and N+ diffusions 4lamda
r203 extra N-well after P+ diffusion 6lamda
r204 between N+ diffusion and n- well 6lamda
r210 minimum diffusion area 16lamda square
Polysilicon
r301 polysilicon width 2lamda
r302 polysilicon gate on diffusion 2lamda
r307 extra polysilicon surrounding diffusion 3lamda
r304 between two polysilicon boxes 3lamda
Contact
r401 contact width 2lamda
r403 extra diffusion surrounding contact 1lamda
r404 extra poly surrounding contact 1lamda
r405 extra metal surrounding contact 1lamda
Metal
r501 between two metals 4lamda
r510 minimum metal area 16lamda square

Fig:3.14 r510 minimum metal area

 24
CHAPTER 4

EXISTING TECHNIQUES

4.1 Power Gating

Power gating is a technique used to reduce leakage current in VLSI

circuits. It involves turning off the power supply to idle blocks of
the circuit. This is achieved by inserting a sleep transistor between
the power supply and the idle block. When the sleep transistor is
turned off, the power supply to the idle block is disconnected,
reducing the leakage current.
Advantages:
Reduces leakage current in idle blocks Easy to implement
Low area overhead
Drawbacks:
Increased Area
Overhead Wake-up
Latency
Voltage Noise and Stability

4.2 Dual Threshold Voltage (DTMOS)

Dual Threshold Voltage (DTMOS) is a technique used to reduce

leakage current in VLSI circuits. It involves using two different
threshold voltages for transistors in the circuit. Transistors with a
high threshold voltage are used for non-critical paths, while
transistors with a low threshold voltage are used for critical paths.
Advantages:
Reduces leakage current in non-critical paths.
Improves performance in critical paths.
Low area overhead.
Drawbacks:
Area Overhead
Increased Design Complexity
Suboptimal Performance for Some Circuits
 25
4.3 Leakage Reduction Using Sleep Transistors

Leakage reduction using sleep transistors is a technique used to

reduce leakage current in VLSI circuits. It involves using sleep
transistors to disconnect the power supply from idle blocks of the
circuit. When the sleep transistor is turned off, the power supply
to the idle block is disconnected, reducing the leakage current.
Advantages:
Reduces leakage current in idle blocks Easy to implement Low area
overhead
Drawbacks:
Increased Area Overhead Wake-up Latency Complex
Control Logic

4.4 Leakage Reduction Using Pinch-Off Technique

Leakage reduction using pinch-off technique is a technique used

to reduce leakage current in VLSI circuits. It involves using a
pinch-off voltage to reduce the leakage current in transistors.
When the pinchoff voltage is applied, the transistor is turned off,
reducing the leakage current.

Advantages:
Reduces leakage current in transistors Easy to implement Low
area overhead
Drawbacks:
Performance Degradation Process Variability
Sensitivity
Limited Effectiveness at Low Voltages

4.5 Stacking Technique

Stacking technique is a technique used to reduce leakage current

in VLSI circuits. It involves stacking multiple transistors to reduce
the leakage current. When multiple transistors are stacked, the
leakage current is reduced
due to the reduced effective width of the transistors.
 26
Advantages:
Reduces leakage current in transistors Improves performance
Drawbacks:
Reduced Noise Margin
Power Consumption During Switching
Reliability Issues

4.6 Multi-Threshold CMOS (MTCMOS)

Multi-Threshold CMOS (MTCMOS) is a technique used to reduce

leakage current in VLSI circuits. It involves using multiple
threshold voltages for transistors in the circuit. Transistors with a
high threshold voltage are used for non-critical paths, while
transistors with a low threshold voltage are used for critical paths.
Advantages:
Reduces leakage current in non-critical paths Maintains
performance in critical paths
Drawbacks:
Design and Control Complexity
Limited Effectiveness in Some Circuit Designs due to the reduced
effective width of the transistors.
 27
CHAPTER 5

PROPOSED TECHNIQUE

5.1 Modified Feedback Sleeper Stack Technique

The Modified Feedback Sleeper Stack (MFSS) technique is a

leakage reduction technique that combines the benefits of
feedback and sleeper stack transistors to reduce leakage current
in VLSI circuits. The MFSS technique is an improvement over the
traditional Feedback Sleeper Stack (FSS) technique, which
provides better leakage reduction and lower area overhead.
The Modified Feedback Sleeper Stack Technique (MFSS) is an
advanced power optimization technique used in CMOS
(Complementary Metal-Oxide-
Semiconductor) circuit design, primarily focused on reducing both
dynamic power and static power
(leakage power) dissipation in digital logic gates. It is particularly
useful in the context of modern, deepsubmicron CMOS
technologies, where leakage power can become a significant
concern due to the increasing density of transistors and smaller
transistor sizes.
The core idea of the MFSS technique is to modify the transistor
stack in CMOS logic circuits by introducing sleeper transistors and
utilizing feedback loops to selectively turn off unnecessary
transistors during idle or low-switching periods. By doing so, the
technique minimizes leakage current and reduces the overall
power consumption of the circuit while still maintaining functional
performance.
 28

Fig:5.1 Circuit Diagram Of Proposed MFSS Technique

5.2 Working Principle

Step 1: Feedback Loop

The MFSS technique starts with a feedback loop that consists of a
feedback transistor (MFB) and a sleeper stack transistor (MSS).
The feedback transistor provides a negative feedback loop to the
sleeper stack transistor.
Step 2: Sleeper Stack Transistor
The sleeper stack transistor is a key component of the MFSS
technique. It is a stacked transistor that consists of multiple
transistors connected in series. The sleeper stack transistor
reduces the leakage current in the circuit by providing a high
resistance path to ground.
Step 3: Modified Feedback Loop
The modified feedback loop is the key innovation of the MFSS
technique. It provides an additional feedback path to the sleeper
stack transistor, helping to improve the leakage reduction. The
modified feedback loop consists of a feedback transistor (MFB2)
and a capacitor (CFB).
 29
Step 4: Control Logic
The control logic is used to control the feedback and sleeper stack
transistors. It provides a control signal (CTRL) that turns on or off
the feedback and sleeper stack transistors.
Step 5: Leakage Reduction
When the control signal (CTRL) is low, the feedback and sleeper
stack transistors are turned off. This reduces the leakage current
in the circuit by providing a high resistance path to ground.
Step 6: Feedback Loop Activation
When the control signal (CTRL) is high, the feedback and sleeper
stack transistors are turned on. The feedback loop is activated,
and the modified feedback loop provides an additional feedback
path to the sleeper stack transistor.
Step 7: Leakage Reduction Optimization
The control logic optimizes the leakage reduction by controlling the
feedback and sleeper stack transistors. It adjusts the control
signal (CTRL) to minimize the leakage current in the circuit.
Comparison with other techniques
Power Gating:
MFSS provides better leakage reduction than power gating,
especially in deep sub-micron technologies. However, power gating
is easier to implement and requires less area overhead.
Dual Threshold Voltage (DTMOS):
MFSS provides better leakage reduction than DTMOS, especially
in deep sub-micron technologies. However, DTMOS is easier to
implement and requires less area overhead.
Leakage Reduction Using Sleep Transistors:
MFSS provides better leakage reduction than sleep transistors,
especially in deep sub-micron technologies. However, sleep
transistors are easier to implement and require less area overhead.
 30
Dynamic Voltage and Frequency Scaling (DVFS):
MFSS provides better leakage reduction than DVFS, especially in
deep sub-micron technologies. However, DVFS is more flexible and
can provide better performance and power trade-offs.
Adiabatic Logic:
MFSS provides better leakage reduction than adiabatic logic,
especially in deep sub-micron technologies. However, adiabatic
logic provides better energy efficiency and can be more suitable for
ultra-low power designs.
Leakage Reduction Using Pinch-Off Technique: MFSS provides
better leakage reduction than pinch off technique, especially in
deep sub-micron technologies.
Stacking Technique:
MFSS provides better leakage reduction than stacking technique,
especially in deep sub-micron technologies. However, stacking
technique is easier to implement and requires less area overhead.
Multi-Threshold CMOS (MTCMOS):
MFSS provides better leakage reduction than MTCMOS, especially
in deep sub-micron technologies. However, MTCMOS is more
flexible and can provide better performance and power trade-offs.
MFSS vs. Power Gating
MFSS provides better leakage reduction (up to 90%) compared to
power gating (up to 70%).
MFSS has lower area overhead (5-10%) compared to power gating
(10-20%).
MFSS vs. Dynamic Voltage and Frequency
Scaling (DVFS)
MFSS provides better leakage reduction (up to 90%) compared to
DVFS (up to 50%).
MFSS has lower area overhead (5-10%) compared to DVFS (10-
20%).
MFSS vs. Adiabatic Logic
MFSS provides better leakage reduction (up to 90%) compared to
adiabatic logic (up to 50%).
 31
MFSS has lower area overhead (5-10%) compared to adiabatic logic
(15-25%).
MFSS vs. Stacking Technique
MFSS provides better leakage reduction (up to 90%) compared to
stacking technique (up to 70%). MFSS has lower area overhead (5-
10%) compared to stacking technique (10-15%).
MFSS vs. Leakage Reduction Using Body Biasing
MFSS provides better leakage reduction (up to 90%) compared to
body biasing (up to 60%).
MFSS has lower area overhead (5-10%) compared to body biasing
(10-15%).
MFSS vs. Multi-Threshold CMOS (MTCMOS)
MFSS provides better leakage reduction (up to 90%) compared to
MTCMOS (up to 70%).
MFSS has lower area overhead (5-10%) compared to MTCMOS (10-
15%).

5.3 NAND gate

The NAND gate is one of the most fundamental logic gates in digital
circuit design, and its implementation plays a crucial role in the
design of complex digital systems, such as processors, memory
elements, and arithmetic units. CMOS (Complementary Metal
Oxide-Semiconductor) NAND gates have been widely used due to
their power efficiency, speed, and reliability. However, with
increasing circuit densities and shrinking feature sizes in modern
CMOS technologies, leakage current and power consumption in
CMOS circuits have become significant challenges, particularly in
low-power applications.
NAND Gate Design Using the Feedback Sleeper Stack
In the modified design using the Feedback Sleeper Stack
Technique, the basic structure of the NAND gate remains similar
to traditional CMOS designs but with important modifications to
reduce power consumption
 32

Fig:5.2 NAND 3 Gate Using MFSS

Addition of Sleeper Transistors:

A sleeper transistor is inserted into the stack to prevent leakage
during idle or low-activity states. These transistors are placed in
such a way that they turn off when they are not required to
conduct. The sleep transistors are controlled by the feedback loop,
ensuring that they turn off when not needed.
Feedback Loop:
The feedback loop ensures that the transistors in the stack are
only active when necessary to generate the correct logic output.
When the input states do not require the output to change, the
feedback loop selectively turns off certain transistors.
This selective turning off of transistors minimizes unnecessary
switching and, thus, reduces both dynamic and leakage power.
Modification to the Pull-Up and Pull-Down Networks:
The pull-up network (PMOS transistors) and pulldown network
(NMOS transistors) in the NAND gate are modified to incorporate
the feedback and sleeper transistors.
The pull-up and pull-down networks are optimized so that the
necessary transistors are active only during the transitions
(switching) or when the output must change state.
 33
Control Signals:
The control signals for the sleeper transistors are derived from the
inputs. These signals generated by the feedback loop and ensure
that the sleeper transistors turn off when they are not required for
logic functionality. When both inputs are 0 or 1, the feedback loop
ensures that unnecessary transistors are kept in the off-state,
eliminating leakage currents.

5.4 NOR gate

The NOR gate is one of the fundamental logic gates in digital

circuit design, and it is used extensively in the construction of
more complex circuits, including memory devices, arithmetic
logic units (ALUs), and control logic in processors. The NOR gate
operates as a combination of an OR gate followed by a NOT gate,
meaning it outputs a high logic level (1) only when both of its
inputs are low (0). In all other input combinations, the output
will be low (0). However, with the scaling of CMOS technologies
to deep- submicron levels, the power consumption especially
due to leakage currents has become a major issue. As the sizes
of transistors decrease, the effects of leakage power.
NOR Gate Design with Feedback Sleeper Stack
The modified NOR gate, using the Modified Feedback Sleeper Stack
Technique, introduces the following changes to the traditional
design:
Addition of Sleeper Transistors:
A sleep transistor is introduced into the stack of either the NMOS
or PMOS network (or both). These sleeper transistors are designed
to be turned off during idle states. They only turn on when their
respective inputs demand a change in output.
For example, a sleeper transistor can be added in series with the
NMOS transistors in the pull-down network. When the input
combination does not require the output to change, this transistor
is turned off, preventing leakage current from flowing through the
NMOS stack.
 34
Feedback Mechanism:
The feedback mechanism ensures that the NMOS and PMOS
transistors are only activated when necessary. When the inputs
remain unchanged, the feedback loop ensures that all
unnecessary transistors are kept in the off state, preventing them
from leaking current.

Fig:5.3 NOR Gate Using MFSS

Control Signals:
The control signals for the sleeper transistors are generated by the
feedback loop. These signals are a function of the input states and
ensure that the sleep transistors are activated only when the
inputs require a change in the output state.
For example, when both inputs A and B are 0 (the output should
be 1), the sleeper transistors are activated in the pull-up network
to prevent leakage.

Idle States and Leakage Control:

When the inputs do not require a change in the output (i.e., when
the output remains steady for an extended period), the feedback
loop ensures that all unnecessary transistors are turned off. This
reduces leakage currents and thus minimizes static power
dissipation.
 35
5.5 XOR gate

The XOR (exclusive OR) gate is a fundamental digital logic gate

used extensively in arithmetic circuits, error detection and
correction, and cryptographic operations. The XOR gate produces
an output of high (1) if and only if the number of high inputs (1) is
odd. In simpler terms, for a 2-input XOR gate, the output is 1 when
one input is high (1) and the other is low (0). If both inputs are the
same (either both 0 or both 1), the output is 0. In conventional
CMOS design, XOR gates are implemented using a combination of
AND, OR, and NOT gates, which makes their design relatively
complex compared to simple gates like NAND or NOR.
XOR Gate Design with Modified Feedback
Sleeper Stack

The Modified XOR gate using the MFSS technique involves the
introduction of feedback loops and sleeper transistors into the
traditional XOR gate structure.

Fig:5.4 XOR Gate Using MFSS

XOR Gate Design with Modified Feedback Sleeper Stack

The Modified XOR gate using the MFSS technique involves the
introduction of feedback loops and sleeper transistors into the
 36
traditional XOR gate structure. The gate will still have its basic
operation, but with optimizations to improve power efficiency.
NMOS Network:
The NMOS transistors in the traditional XOR gate are designed in
a series-parallel configuration. However, in the modified design, a
sleeper transistor can be inserted in the NMOS stack. The feedback
loop ensures that the sleeper transistor is turned off when the
input combination does not require the output to change. This
prevents leakage current in the NMOS stack.
PMOS Network:
Similarly, the PMOS transistors can be optimized using the MFSS
technique. A feedback loop is used to monitor the input conditions,
ensuring that the PMOS transistors only conduct when necessary,
and a sleeper transistor is introduced to prevent leakage in the idle
state.
 37
CHAPTER 6

ADVANTAGES AND APPLICATIONS

6.1 Advantages

Effective Leakage Power Reduction: MFSS significantly reduces

leakage power consumption in sleep mode, making it suitable for
low-power applications.
Improved Energy Efficiency: By minimizing leakage power, MFSS
leads to substantial energy savings, especially in systems with
frequent idle periods.
Reduced Heat Generation: Lower power consumption results in
reduced heat generation, improving system reliability and lifespan.
Low Power Design: MFSS is particularly useful in designing low-
power digital circuits, such as those used in mobile devices, IoT
devices, and other battery-powered systems.
Increased Battery Life: By reducing power consumption, MFSS
can help increase battery life in portable devices.
Enhanced System Performance: MFSS can contribute to
improved overall system performance by reducing power
consumption and heat generation.
Flexibility and Scalability: The MFSS technique can be applied to
various circuit designs and technologies, making it a versatile
solution for low-power design.

6.2 Applications

Mobile Devices: Smartphones, tablets, and other portable

electronics.
Internet of Things (IoT): Low-power sensors, wearables, and other
IoT devices.
Low-Power Electronics: Wearable devices, fitness trackers, and
other battery-powered systems.
 38
Embedded Systems: Low-power microcontrollers and embedded
systems.
Battery-Powered Devices: Devices that require long battery life,
such as hearing aids and smartwatches.
Energy-Harvesting Systems: Systems that rely on energy
harvesting, such as solar-powered devices.
Medical Devices: Portable medical devices, such as insulin pumps
and portable defibrillators.
Aerospace and Defense: Low-power systems for aerospace and
defense applications.
Automotive Electronics: Low-power automotive electronics, such
as infotainment systems.
Consumer Electronics: Low-power consumer electronics, such as
smart home devices.
Industrial Automation: Low-power industrial automation
systems.
Wireless Sensor Networks: Low-power wireless sensor networks.
Energy-Efficient Computing: MFSS can be used in energy-
efficient computing systems.
Artificial Intelligence (AI) and Machine Learning (ML) Devices:
Low-power AI and ML devices can benefit from MFSS.
 39
CHAPTER 7

SOFTWARE RESULTS

7.1 NAND gate

Fig:7.1 schematic of NAND gate

Schematic Overview

A and B are the main logic inputs.

S1 and S2 appear to be sleep transistors or power-gating control
signals (common in low-power designs like Modified Feedback
Sleeper Stack technique).
PMOS Pull-up Network (Top Part) Connected to VDD.
Two PMOS transistors in parallel: Controlled by A and B
respectively. PMOS transistors conduct (pass logic high) when gate
= 0. So, if A = 0 or B = 0, at least one PMOS will conduct, pulling
the output high.
NMOS Pull-down Network (Bottom Part)
Three NMOS transistors in series: From top to bottom: controlled
by A, B, and S2. For output to go low, all NMOS must be ON → A
= 1, B = 1, and S2 = 1.
 40
Working
Output = 1 (High)
If either A or B is 0, then: At least one PMOS is ON → output pulled
to VDD. NMOS network is incomplete (at least one is OFF) → output
not pulled down.
Output = 0 (Low)
When A = 1, B = 1, and S2 = 1: Both PMOS OFF → no pull-up. All
NMOS ON → strong pull-down to GND → output = 0.
Role of S1 and S2(Sleep Transistors)
S1 is likely a header sleep transistor (PMOS), placed between VDD
and the circuit. S2 is a footer sleep transistor (NMOS), placed
between GND and NMOS network. These are used to reduce
leakage power in low-power designs. When S1 or S2 is OFF →
circuit is in sleep mode → no power drawn.

Fig:7.2 timing diagram of NAND gate

 41

Fig:7.3 truth table of NAND gate

Overview

The term "NAND" is a combination of "NOT" and "AND". This means

that a NAND gate performs the logical AND operation on its inputs
and then inverts (NOTs) the result
AND Operation: An AND gate produces a HIGH (1) output only if all
its inputs are HIGH (1). Otherwise, the output is LOW (0).
NOT Operation (Inversion): A NOT gate (or inverter) simply reverses
the input; if the input is HIGH, the output is LOW, and vice-versa.
So, a NAND gate is essentially an AND gate followed by an inverter.
The truth table shows all possible combinations of inputs (A and B)
and the corresponding output:
1. A = 0, B = 0: (0 AND 0) would be 0.
NOT (0) is 1. So, the output is 1.
2. A = 1, B = 0:(1 AND 0) would be 0.
NOT (0) is 1. So, the output is 1.
3. A = 0, B = 1:(0 AND 1) would be 0.
NOT (0) is 1. So, the output is 1.
4. A = 1, B = 1: (1 AND 1) would be 1.
NOT (1) is 0. So, the output is 0.
 42
7.2 NOR gate

Fig:7.4 schematic of NOR gate

Schematic Overview

A, B: Logic inputs.
S1, S2: Sleep control signals for PMOS (header) and NMOS (footer),
used in low-power design (Modified Feedback Sleeper Stack).
Pull-up Network (PMOS) Connected to VDD through a PMOS sleep
transistor controlled by S1. Two PMOS transistors in series,
controlled by A and B. PMOS conducts when gate = 0. So, only
when A = 0 AND B = 0, both PMOS conduct → output pulled high
(logic 1). Otherwise, output not connected to VDD.
Pull-down Network (NMOS)Connected to GND via a NMOS sleep
transistor controlled by S2. Two NMOS transistors in parallel,
controlled by A and B. NMOS conducts when gate = 1. So, if A = 1
OR B = 1, at least one NMOS conducts → output pulled low (logic
0).
If Output = 1
 43
When A = 0 and B = 0: PMOS path: Both PMOS ON → output pulled
to VDD. NMOS path: Both NMOS OFF → no pull-down.
If Output = 0
When A = 1 or B = 1: PMOS path broken → no pull-up. At least one
NMOS ON → output pulled to GND.
Power Gating (S1 & S2)
S1: PMOS sleep transistor at the top (header).
S2: NMOS sleep transistor at the bottom (footer).
These are used to disconnect power rails during standby/sleep
mode, saving leakage power.

Fig:7.5 timing diagram of NOR gate

 44

Fig:7.6 truth table of NOR gate

Overview

The term "NOR" is a combination of "NOT" and "OR". This means

that a NOR gate performs the logical OR operation on its inputs
and then inverts (NOTs) the result.
OR Operation: An OR gate produces a HIGH (1) output if at least
one of its inputs is HIGH (1). It only produces a LOW (0) output if
all its inputs are LOW (0).
NOT Operation (Inversion): A NOT gate (or inverter) simply reverses
the input; if the input is HIGH, the output is LOW, and vice-versa.
So, a NOR gate is essentially an OR gate followed by an inverter.
1. A = 0, B = 0:(0 OR 0) would be 0.
NOT (0) is 1. So, the output is 1.
2. A = 1, B = 0:(1 OR 0) would be 1.
NOT (1) is 0. So, the output is 0.
3. A = 0, B = 1:(0 OR 1) would be 1.
NOT (1) is 0. So, the output is 0.
4. A = 1, B = 1:(1 OR 1) would be 1.
NOT (1) is 0. So, the output is 0.
 45
7.3 XOR gate

Fig:7.7 schematic of XOR gate

Schematic Overview

Left Block (Pre-processing Stage)

This section likely generates A'B + AB' — the essential intermediate
signal for XOR.
Inputs A and B are fed into transistor pairs: PMOS transistors at
the top (with W=2.0u and L=0.12u) are connected to VDD.
NMOS transistors at the bottom (also W/L noted) are connected
to GND. These implement a logic structure that outputs A XOR B.
Right Block (Output Stage)
This is likely buffering or driving the final XOR output with stronger
logic levels: It has more stacked transistors, indicating
transmission and pull chains to refine or stabilize the logic levels
The last stage drives an LED-like symbol, representing the final
output of the XOR gate (out1). The logic from the first block feeds
into the second block, suggesting multi-level CMOS logic design.
 46
PMOS Network at top: Pulls output high for required XOR
conditions. NMOS Network at bottom: Pulls output low otherwise.
Transistors are sized differently (W=1u or 2u or 6u) for drive
strength and timing optimization.

Fig:7.8 timing diagram of XOR gate

Fig:7.9 truth table of XOR gate

Overview

The term "XOR" stands for "Exclusive OR." Unlike a regular OR gate
(where the output is HIGH if any input is HIGH), an XOR gate
 47
produces a HIGH (1) output only when its inputs are different from
each other. If the inputs are the same, the output is LOW (0).
The truth table shows all possible combinations of inputs (A and B)
and the corresponding output:
1. A = 0, B = 0: The inputs are the same.
So, the output is 0.
2. A = 1, B = 0: The inputs are different.
So, the output is 1.
3. A = 0, B = 1: The inputs are different.
So, the output is 1.
4. A = 1, B = 1: The inputs are the same.
So, the output is 0.

7.4 Simulation Results

Fig:7.10 simulation of NAND gate

 48

Fig:7.11 simulation of NOR gate

Fig:7.12 simulation of XOR gate

 49
Values of power and delay with MFSS technique

Fig:7.13 values of power & delay

Values of power and delay without MFSS technique

Fig:7.14 values of power & delay

 50
CHAPTER 8

CONCLUSION AND FUTURE SCOPE

8.1 Conclusion

In conclusion, the Modified Feedback Sleeper Stack (MFSS)

technique is a highly effective approach for reducing leakage
power and improving energy efficiency in CMOS circuits. By
leveraging MFSS, designers can create low-power digital
systems that are well-suited for a wide range of applications,
from mobile devices and IoT devices to other battery-powered
systems. With its ability to significantly reduce power
consumption and enhance system reliability, MFSS is poised to
play a crucial role in the development of next-generation energy-
efficient digital systems.
8.2 future scope

The Modified Feedback Sleeper Stack (MFSS) technique has a

promising future scope, with potential applications in emerging
technologies like quantum computing, neuromorphic
computing, and IoT devices. Further research and optimization
of MFSS can lead to increased adoption in the industry, driving
innovation and advancements in low-power design. As the
demand for energy-efficient systems continues to grow, MFSS is
poised to play a crucial role in shaping the future of digital
system design, enabling the development of more sustainable
and efficient technologies.
 51
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[CrossRef] [Google Scholar] [Publisher Link]
 52
APPENDIX
// DSCH 2.7f
// 27-04-2025 4.06.11 PM
// D:\tanner ex\micro\2input ls nand.sch

module 2input ls nand( in2,in1,out2);

input in2,in1;
output out2;
pmos #(24) pmos(w2,vdd,in1); // 2.0u 0.12u
pmos #(17) pmos(vdd,w2,in2); // 2.0u 0.12u
pmos #(17) pmos(out2,w2,w4); // 2.0u 0.12u
nmos #(17) nmos(out2,w4,w2); // 1.0u 0.12u
nmos #(17) nmos(w4,w6,in1); // 1.0u 0.12u
nmos #(10) nmos(vss,w6,in2); // 1.0u 0.12u
endmodule

// Simulation parameters in Verilog Format

always
#1000 in2=~in2;
#2000 in1=~in1;

// Simulation parameters
// in2 CLK 10 10
// in1 CLK 20 20
 53
// DSCH 2.7f
// 27-04-2025 4.03.23 PM
// D:\tanner ex\micro\NOR.sch

module NOR( A,B,S2,S1,out1);

input A,B,S2,S1;
output out1;
pmos #(24) pmos(out1,w1,B); // 2.0u 0.12u
nmos #(24) nmos(out1,w4,A); // 1.0u 0.12u
pmos #(10) pmos(w1,w6,A); // 2.0u 0.12u
nmos #(24) nmos(out1,w4,B); // 1.0u 0.12u
pmos #(17) pmos(w6,vdd,S1); // 2.0u 0.12u
nmos #(17) nmos(w6,vdd,w8); // 1.0u 0.12u
nmos #(24) nmos(w4,vss,S2); // 1.0u 0.12u
pmos #(24) pmos(w4,vss,w8); // 2.0u 0.12u
endmodule

// Simulation parameters in Verilog Format

always
#1000 A=~A;
#2000 B=~B;
#4000 S2=~S2;
#8000 S1=~S1;

// Simulation parameters
// A CLK 10 10
// B CLK 20 20
// S2 CLK 40 40
// S1 CLK 80 80
 54
// DSCH 2.7f
// 27-04-2025 3.59.42 PM
// D:\tanner ex\micro\XOR.sch

module XOR( A,B,out1);

input A,B;
output out1;
pmos #(10) pmos(w3,out1,w2); // 2.0u 0.12u
pmos #(10) pmos(w5,vdd,w4); // 2.0u 0.12u
pmos #(24) pmos(w2,vdd,A); // 2.0u 0.12u
nmos #(24) nmos(w2,vss,A); // 1.0u 0.12u
pmos #(24) pmos(w4,vdd,B); // 2.0u 0.12u
nmos #(24) nmos(w4,vss,B); // 1.0u 0.12u
pmos #(31) pmos(out1,w5,A); // 2.0u 0.12u
nmos #(31) nmos(out1,w8,A); // 1.0u 0.12u
nmos #(10) nmos(w8,vss,B); // 1.0u 0.12u
pmos #(45) pmos(vdd,w3,B); // 2.0u 0.12u
nmos #(10) nmos(w9,out1,w4); // 1.0u 0.12u
nmos #(45) nmos(vss,w9,w2); // 1.0u 0.12u
endmodule

// Simulation parameters in Verilog Format

always
#1000 A=~A;
#2000 B=~B;

// Simulation parameters
// A CLK 10 10
// B CLK 20 20