(Established under Section 3 of the UGC Act, 1956)

(A CHRISTIAN MINORITY INSTITUTION)

Jeppiaar Nagar, Rajiv Gandhi Road, Chennai – 600 119, Tamilnadu. India.

MICROPROCESSOR AND MICROCONTROLLER

LABMANUAL

Name: ……………………………….. Roll No.: ………

Semester: VI Branch: E.C.E Code: SEC4067

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY
Jeppiaar Nagar, Rajiv Gandhi Road, Chennai – 600 119
 INDEX
Name of the Laboratory : SEC-4067- MICROPROCESSOR AND MICROCONTROLLER LAB

Name of the Staff Lab In-Charge :

S Date of Page Date of

Name of the Experiment Marks Staff Signature
No Expt No Submission

STUDY OF 8085
MICROPROCESSOR

PROGRAMS USING ARITHMETIC

1 OPERATIONS

a 8-BIT ADDITION & SUBTRACTION

b 8-BIT MULTIPLICATION & DIVISION

c 16 BIT ADDITION & SUBTRACTION

d 16 BIT MULTIPLICATION

PROGRAMS FOR CODE

2. CONVERSION

a BCD to HEXA CONVERSION

b HEXA TO BCD CONVERSION

c ASCII TO HEXA CONVERSION

d HEXA TO ASCII CONVERSION

LARGEST,SMALLEST AND
3. SORTING OF AN ARRAY

a LARGEST OF AN ARRAY

b SMALLEST OF AN ARRAY

c SORT IN ASCENDING ORDER

d SORT IN DESCENDING ORDER

 STUDY OF 8051
MICROCONTROLLER

4. DATA TRANSFER PROGRAMS

a FILL INTERNAL MEMORY

b FILL EXTERNAL MEMORY

c MOVE DATA FROM INTERNAL TO

EXTERNAL MEMORY
d MOVE DATA FROM EXTERNAL TO
INTERNAL MEMORY
e MOVE DATA FROM WITHIN
EXTERNAL
5. PROGRAMS USING LOGICAL AND
BOOLEAN INSTRUCTIONS
6. READING AND WRITING ON A
PARALLEL PORT
OPERATION ON PORT BITS
a. (SQUARE WAVE FORM
GENERATION)
b.
TRAFFIC SIGNAL CONTROLLER
7. READING AND WRITING ON A
PARALLEL PORT
a.
7-SEGMENT LED INTERFACE
b.
DIGITAL IC TESTING
8.a STEPPER MOTOR CONTROLLER
(CLOCKWISE DIRECTION)
b. STEPPER MOTOR CONTROLLER
(ANTICLOCKWISE DIRECTION)
9.
TIMER
10.
SERIAL COMMUNICATION
 STUDY OF 8085 MICROPROCESSOR

AIM: To study the architecture and pin diagram of 8085 microprocessor.

Control Unit
Generates signals within uP to carry out the instruction, which has been decoded. In reality
causes certain connections between blocks of the uP to be opened or closed, so that data goes
where it is required, and so that ALU operations occur.

Arithmetic Logic Unit

The ALU performs the actual numerical and logic operation such as ‘add’, ‘subtract’, ‘AND’,
‘OR’, etc. Uses data from memory and from Accumulator to perform arithmetic. Always stores
result of operation in Accumulator.

Registers
The 8085/8080A-programming model includes six registers, one accumulator, and one flag
register, as shown in Figure. In addition, it has two 16-bit registers: the stack pointer and the
program counter. They are described briefly as follows. The 8085/8080A has six general-
purpose registers to store 8-bit data; these are identified as B,C,D,E,H, and L as shown in the
figure. They can be combined as register pairs - BC, DE, and HL - to perform some 16-bit
operations. The programmer can use these registers to store or copy data into the registers by
using data copy instructions.
Accumulator

The accumulator is an 8-bit register that is a part of arithmetic/logic unit (ALU). This register is
used to store 8-bit data and to perform arithmetic and logical operations. The result of an
operation is stored in the accumulator. The accumulator is also identified as register A.

Flags

The ALU includes five flip-flops, which are set or reset after an operation according to data
conditions of the result in the accumulator and other registers. They are called Zero(Z), Carry
(CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags; they are listed in the Table and their
bit positions in the flag register are shown in the Figure below. The most commonly used flags
are Zero, Carry, and Sign. The microprocessor uses these flags to test data conditions. For
example, after an addition of two numbers, if the sum in the accumulator id larger than eight
bits, the flip-flop uses to indicate a carry -- called the Carry flag (CY) – is set to one. When an
arithmetic operation results in zero, the flip-flop called the Zero(Z) flag is set to one. The first
Figure shows an 8-bit register, called the flag register, adjacent to the accumulator. However, it
is not used as a register; five bit positions out of eight are used to store the outputs of the five
flip-flops. The flags are stored in the 8-bit register so that the programmer can examine these
flags (data conditions) by accessing the register through an instruction. These flags have critical
importance in the decision-making process of the micro- processor. The conditions (set or
reset) of the flags are tested through the software instructions. For example, the instruction JC
(Jump on Carry) is implemented to change the sequence of a program when CY flag is set. The
thorough understanding
of flag is essential in writing assembly language programs.

Program Counter (PC)

This 16-bit register deals with sequencing the execution of instructions. This register is a
memory pointer. Memory locations have 16-bit addresses, and that is why this is a 16-bit
register. The microprocessor uses this register to sequence the execution of the instructions.
The function of the program counter is to point to the memory address from which the next byte
is to be fetched. When a byte (machine code) is being fetched, the program counter is
incremented by one to point to the next memory location

Stack Pointer (SP)

The stack pointer is also a 16-bit register used as a memory pointer. It points to a memory
location in R/W memory, called the stack. The beginning of the stack is defined by loading 16-
bit address in the stack pointer.
Instruction Register/Decoder

Temporary store for the current instruction of a program. Latest instruction sent here from
memory prior to execution. Decoder then takes instruction and ‘decodes’ or interprets the
instruction. Decoded instruction then passed to next stage.

Memory Address Register

Holds address, received from PC, of next program instruction. Feeds the address bus with
addresses of location of the program under execution.
Control Generator
Generates signals within uP to carry out the instruction which has been decoded. In reality
causes certain connections between blocks of the uP to be opened or closed, so that data goes
where it is required, and so that ALU operations occur.

Register Selector

This block controls the use of the register stack in the example. Just a logic circuit which
switches between different registers in the set will receive instructions from Control Unit.

General Purpose Registers

uP requires extra registers for versatility. Can be used to store additional data during a program.
More complex processors may have a variety of differently named registers.

8085 Pin description.

Pin Description

The following describes the function of each pin:

A6 - A1s (Output 3 State)
Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0
address,3 stated during Hold and Halt modes.

AD0 - 7 (Input/Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on
the bus during the first clock cycle of a machine state. It then becomes the data bus during the
second and third clock cycles. 3 stated during Hold and Halt modes.

ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the
address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to
guarantee setup and hold times for the address information. ALE can also be used to strobe the
status information. ALE is never 3stated.

SO, S1 (Output)
Data Bus Status. Encoded status of the bus cycle:
S1 S0
O O HALT
0 1 WRITE
1 0 READ
1 1 FETCH
S1 can be used as an advanced R/W status.

RD (Output 3state)
READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is
available for the data transfer.

WR (Output 3state)
WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0
location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.

READY (Input)
If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready
to send or receive data. If Ready is low, the CPU will wait for Ready to go high before
completing the read or write cycle.
HOLD (Input)
HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The
CPU, upon receiving the Hold request. will relinquish the use of buses as soon as the
completion of the current machine cycle. Internal processing can continue. The processor can
regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address,
Data, RD, WR, and IO/M lines are 3stated.

HLDA (Output)
HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will
relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed.
The CPU takes the buses one half clock cycle after HLDA goes
low.

INTR (Input)
INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the
next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be
inhibited from Incrementing and an INTA will be issued. During this cycle a RESTART or CALL
instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and
disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

INTA (Output)
INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the
Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or
some other interrupt port.
RST 5.5
RST 6.5 - (Inputs)
RST 7.5
RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they
cause an internal RESTART to be automatically inserted.
RST 7.5 ~~ Highest Priority
RST 6.5
RST 5.5 o Lowest Priority
The priority of these interrupts is ordered as shown above. These interrupts have a higher
priority than the INTR.

TRAP (Input)
Trap interrupt is a nonmaskable restart interrupt. It is recognized at the same time as INTR. It is
unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.
RESET IN (Input)
Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flipflops.
None of the other flags or registers (except the instruction register) are affected The CPU is
held in the reset condition as long as Reset is applied.

RESET OUT (Output)

Indicates CPlJ is being reset. Can be used as a system RESET. The signal is synchronized to
the processor clock.

X1, X2 (Input)
Crystal or R/C network connections to set the internal clock generator X1 can also be an
external clock input instead of a crystal. The input frequency is divided by 2 to give the internal
operating frequency.

CLK (Output)
Clock Output for use as a system clock when a crystal or R/ C network is used as an input to
the CPU. The period of CLK is twice the X1, X2 input period.

IO/M (Output)
IO/M indicates whether the Read/Write is to memory or l/O Tristated during Hold and Halt
modes.

SID (Input)
Serial input data line The data on this line is loaded into accumulator bit 7 whenever a RIM
instruction is executed.

SOD (output)
Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

Vcc
+5 volt supply.
Vss
Ground Reference.

Result: The architecture and pin diagram of 8085 was studied.

Program Format (8 bit addition)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9100]
9005 47 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9101]
9009 80 ADD B ;A ← A+B
D2 0E ; If no carry,
900A JNC 900E(L1)
90 go to L1
900D 0C INR C ;C ← C+1
900E 32 00 92 L1 : STA 9200 ; [9200] ← A
9011 79 MOV A, C ;A←C
9012 32 01 92 STA 9201 ; [9201] ← A
9015 CF RST 1 ; Reset
Expt. No: 1.a Page No:

Expt. Name: 8-BIT ADDITION Date:

Aim:

To write an ALP to perform 8-bit addition.

Algorithm:

1. Clear one register for carry (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register (Reg B)
4. Load the accumulator with the second data
5. Add Reg B content to accumulator
6. Check for carry, if there is no carry, go to step 8
7. Increment reg C to indicate carry
8. Store the results – carry in Reg C and sum in accumulator to memory locations
9. Stop
Sample Data:

Input Output

9100 – 04 9200 – 0C

9101 – 08 9201 – 00

9100 – FF 9200 – FE

9101 – FF 9201 – 01
Program:

MVI C, 00
LDA 9100
MOV B, A
LDA 9101
ADD B
JNC L1:
INR C
L1 : STA 9200
MOV A, C
STA 9201
RST 1

Result:

The ALP to perform 8-bit addition was executed and its output verified.
Program Format ( 8 bit subtraction)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9200]
9005 78 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9201]
9009 90 SUB B ;A ← A–B
DA 10 ; If no carry,
900A JNC 9010(L1)
90 go to L1
900D 2F CMA
;A ←A
900E 3C INR A ;A ← A+1
900F 0C INR C ;C ← C+1
9010 32 00 92 L1 : STA 9200 ; [9200] ← A
9013 79 MOV A, C ;A←C
9014 32 01 92 STA 9201 ; [9201] ← A
9017 CF RST 1 ; Reset
Expt. No: 1.a Page No:

Expt. Name: 8-BIT SUBTRACTION Date:

Aim:

To write an ALP to perform 8-bit subtraction.

Algorithm:

1. Clear one register for borrow (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register (Reg B)
4. Load the accumulator with the second data
5. Subtract Reg B content from accumulator content
6. Check for carry, if there is no carry, go to step 10
7. Complement accumulator content
8. Increment accumulator content
9. Increment reg C to indicate borrow
10. Store the results – borrow in Reg C and difference in accumulator to memory
locations
11. Stop
Sample Data:

Input Output

9200 – FF 9200 – 55

9201 – AA 9201 – 01

9200 – BB 9200 – 44

9201 – FF 9201 – 00
Program:

MVI C, 00
LDA 9200
MOV B, A
LDA 9201
SUB B
JNC L1
CMA
INR A
INR C
L1 : STA 9200
MOV A, C
STA 9201
RST 1

Result:

The ALP to perform 8-bit subtraction was executed and its output verified.
Program Format: (8 bit multiplication)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9100]
9005 47 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9101]
9009 57 MOV D, A ;D ← A
900A 3E 00 MVI A, 00 ; A ← 00
900C 82 L2 : ADD D ;A←A+D
; If no carry,
900D D2 11 90 JNC L1
go to L1
9010 0C INR C ;C ← C+1
9011 05 L1 : DCR B ;B ← B–1
; If not zero,
9012 C2 0C 90 JNZ L2
go to L2
9015 32 02 91 STA 9102 ; [9102] ← A
9018 79 MOV A, C ;A←C
9019 32 03 91 STA 9103 ; [9103] ← A
901C CF RST 1 ; Reset
Expt. No: 1.b Page No:

Expt. Name: 8-BIT MULTIPLICATION Date:

Aim:

To write an ALP to perform 8-bit multiplication.

Algorithm:

1. Clear one register for carry (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register for counter (Reg B)
4. Load the accumulator with the second data
5. Move the accumulator content to one register (Reg D)
6. Clear the accumulator
7. Add Reg D content to accumulator
8. Check for carry, if there is no carry, go to step 10
9. Increment Reg C to indicate carry
10. Decrement the counter register (Reg B)
11. Check for zero, if not zero, go to step 7
12. Store the results – carry in Reg C and product in accumulator to memory locations
13. Stop
Sample Data:

Input Output

9100 – 05 9102 – 14

9101 – 04 9103 – 00

9100 – FF 9102 – FE

9101 – FF 9103 – 01
Program:

MVI C, 00
LDA 9100
MOV B, A
LDA 9101
MOV D, A
MVI A, 00
L2 : ADD D
JNC L1:
INR C
L1 : DCR B
JNZ L2:
STA 9102
MOV A, C
STA 9103
RST 1

Result:

The ALP to perform 8-bit multiplication was executed and its output verified.
Program Format: ( 8 bit division)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C , 00 ; C ← 00
9002 3A 00 91 LDA 9100 ; A ← [9100]
9005 47 MOV B, A ;B←A
9006 3A 01 91 LDA 9101 ; A ← [9101]

; Compare A
9009 B8 L1 : CMP B
and B
; If carry, go
900A DA 12 90 JC 9012(L2) to L2

900D 90 SUB B ;A ←A–B

900E 0C INR C ;C ← C+1
900F C3 09 90 JMP L1 ; Jump to L1
9012 32 03 91 L2 : STA 9103 ; [9103] ← A
9015 79 MOV A, C ;A←C
9016 32 02 91 STA 9102 ; [9102] ← A
9019 CF RST 1 ; Reset
Expt. No: 1.b Page No:

Expt. Name: 8-BIT DIVISION Date:

Aim:

To write an ALP to perform 8-bit division.

Algorithm:

1. Clear one register to store the quotient (Reg C)

2. Load the accumulator with the first data
3. Move the accumulator content to one register (Reg B)
4. Load the accumulator with the second data
5. Compare the contents of Reg B and accumulator
6. Check for carry, if there is carry, go to step 10
7. Subtract the content of Reg B from accumulator
8. Increment Reg C
9. Repeat from step 5
10. Store the results – quotient in Reg C and reminder in accumulator to memory
locations
11. Stop
Sample Data:

Input Output

9100 – 02 9102 – 03 (Q)

9101 – 06 9103 – 00(R)

9100 – 07 9102 – 05 (Q)

9101 – 25 9103 – 02(R)

Program:

MVI C, 00
LDA 9100
MOV B, A
LDA 9101
L1 : CMP B
JC L2:
SUB B
INR C
JMP L1:
L2 : STA 9103
MOV A, C
STA 9102
RST 1

Result:

The ALP to perform 8-bit division was executed and its output verified.
Program Format: ( 16 bit addition)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 0E 00 MVI C, 00 ; C ← 00

; L ← [9100]
9002 2A 00 91 LHLD 9100
H ← [9101]

;E ← L
9005 EB XCHG
D←H

; L ← [9102]
9006 2A 02 91 LHLD 9102
H ← [9103]
;L ← L+E
9009 19 DAD D
H ←H+D
; If no carry,
900A D2 0E 90 JNC 900E(L1)
go to L1
900D 0C INR C ;C ← C+1
; [9104] ← L
900E 22 04 91 L1: SHLD 9104
[9105] ← H
9011 79 MOV A, C ;A ← C
9012 32 06 91 STA 9106 ; [9106] ← A
9015 CF RST 1 ; Reset
Expt. No: 1.c Page No:

Expt. Name: 16-BIT ADDITION Date:

Aim:

To write an ALP to add two 16-bit numbers.

Algorithm:

1. Clear one register for carry (Reg C)

2. Load the first data in HL register pair
3. Swap the contents of HL and DE pairs
4. Load the second data in HL register pair
5. Double add the contents of HL and DE pairs
6. Check for carry, if there is no carry go to step 8
7. Increment Reg C
8. Store the result which is in HL pair in a memory location
9. Move the carry in Reg C to accumulator
10. Store the accumulator content in memory
11. Stop
Sample Data:

Input Output

9100 – 06 9104 – 09

9101 – 05 9105 – 0B

9102 – 03 9106 – 00

9103 – 06

9100 – 06 9104 – 09

9101 – F0 9105 – E0

9102 – 03 9106 – 01

9103 – F0
Program:

MVI C, 00
LHLD 9100
XCHG
LHLD 9102
DAD D
JNC L1
INR C
L1 : SHLD 9104
MOV A, C
STA 9106
RST 1

Result:

The ALP for adding two 16-bit numbers was executed and its output verified.
Program Format: ( 16 bit subtraction)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; L ← [9100]
9000 2A 00 91 LHLD 9100
H ← [9101]

;E ← L
9003 EB XCHG
D←H

; L ← [9102]
9004 2A 02 91 LHLD 9102
H ← [9103]

9007 7D MOV A, L ;A ← L
9008 93 SUB E ;A ← A–E
9009 6F MOV L, A ;L ← A
900A 7C MOV A, H ;A ← H
;A ← A–D
900B 9A SBB D
– CARRY
900C 67 MOV H, A ;H ← A
; [9200] ← L
900D 22 00 92 SHLD 9200
[9201] ← H
9010 CF RST 1 ; Reset
Expt. No: 1.c Page No:

Expt. Name: 16-BIT SUBTRACTION Date:

Aim:

To write an ALP to subtract two 16-bit numbers.

Algorithm:

1. Load the first data in HL register pair

2. Swap the contents of HL and DE pairs
3. Load the second data in HL register pair
4. Subtract the content in E from content in L
5. Move the accumulator content to L
6. Subtract with borrow the content in D from content in H
7. Move the accumulator content to H
8. Store the result which is in HL pair in a memory location
9. Stop
Sample Data:

Input Output

9100 – 06 9200 – 03

9101 – 05 9201 – 01

9102 – 09

9103 – 06

9100 – 06 9200 – 02

9101 – 08 9201 – FE

9102 – 08

9103 – 06
Program:

LHLD 9100
XCHG
LHLD 9102
MOV A, L
SUB E
MOV L, A
MOV A, H
SBB D
MOV H, A
SHLD 9200
RST 1

Result:

The ALP for subtracting two 16-bit numbers was executed and its output verified.
Program Format: (16 bit multiplication)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; H ← 00
9000 21 00 00 LXI H, 0000
L ← 00
; B ← 00
9003 01 00 00 LXI
B, 0000 C ← 00

9006 31 FF FF LXI SP, FFFF ; SP ← FFFF

9009 ; D ← FF
11 FF FF LXI D, FFFF
E ← FF
; HL ← HL +
900C 39 L2 : DAD SP
SP
; If no carry,
900D D2 11 90 JNC L1
jump to L1
; BC ← BC +
9010 03 INX B
1
; DE ← DE -
9011 1B L1 : DCX D
1
9012 7A MOV A, D ;A ←D
9013 B2 ORA E ; A ← A OR E
; If no zero,
9014 C2 0C 90 JNZ 900c(L2)
jump to L2
; [9200] ← L
9017 22 00 92 SHLD 9200
[9201] ← H
901A 69 MOV L, C ;L ←C
901B 60 MOV H, B ;H ←B
; [9202] ← L
901C 22 02 92 SHLD 9202
[9203] ← H
901F CF RST 1 ; Reset
Expt. No: 1.d Page No:

Expt. Name: 16-BIT MULTIPLICATION Date:

Aim:

To write an ALP to perform 16-bit multiplication.

Algorithm:

1. Clear one register pair (BC) for carry

2. Load the first data in stack pointer
3. Load the second data in DE pair
4. Clear one register pair (HL)
5. Double add the contents of HL and SP
6. Check for carry, if there is no carry go to step 8
7. Increment BC pair
8. Decrement DE pair
9. Move Reg E content to accumulator
10. OR the contents of accumulator and Reg E
11. Check for zero, if not zero, go to step 5
12. Store the product in HL pair in a memory location
13. Move the carry in BC pair to HL pair
14. Store the carry in HL pair in a memory location
15. Stop
Sample Data:

Input Output

FFFF 9200 – 01

FFFF 9201 – 00

9202 – FE

9203 – FF
Program:

LXI H, 0000
LXI B, 0000
LXI SP, FFFF
LXI D, FFFF
L2 : DAD SP
JNC L1
INX B
L1 : DCX D
MOV A, D
ORA E
JNZ L2
SHLD 9200
MOV L, C
MOV H, B
SHLD 9202
RST 1

Result:

The ALP to perform 16-bit multiplication was executed and its output verified.
Program Format: ( BCD to hexa)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 3A 00 91 LDA 9100 ; A ← [9100]
9003 06 0A MVI B, 0A ; B ← 0A
9005 57 MOV D, A ;D ←A
9006 3E 00 MVI A, 00 ; A ← 00
9008 82 L1 : ADD D ;A ←A+D
9009 05 DCR B ;B ←B–1
; If no zero,
900A C2 08 90 JNZ L1
jump to L1
900D 4F MOV C, A ;C ←A
900E 3A 01 91 LDA 9101 ; A ← [9101]
9011 81 ADD C ;A ←A+C
9012 32 02 91 STA 9102 ; [9102] ← A
9015 CF RST 1 ; Reset
Expt. No: 2.a Page No:

Expt. Name: BCD TO HEX CONVERSION Date:

Aim:

To write an ALP to convert a given BCD number to HEX number.

Algorithm:

1. Load the accumulator with the MSB of the given BCD number from a memory
address
2. Initialize one register (Reg B) with immediate data 0A
3. Move the accumulator content to a register (Reg D)
4. Clear the accumulator
5. Add Reg D content to accumulator
6. Decrement Reg D
7. Check for zero, if not zero, go to step 5
8. Move the accumulator content to Reg C
9. Load the accumulator with the LSB of the given BCD number from a memory address
10. Add Reg C content to accumulator
11. Store the accumulator content in a memory location
12. Stop
Sample Data:

Input Output

9100 – 09 (MSB) 9102 – 62

9101 – 08 (LSB)
Program:

LDA 9100
MVI B, 0A
MOV D, A
MVI A, 00
L1 : ADD D
DCR B
JNZ L1
MOV C, A
LDA 9101
ADD C
STA 9102
RST 1

Result:

The ALP for converting a given BCD number to HEX number was executed and its
output verified.
Program Format: (hexa to bcd)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; B ← 00
9000 01 00 00 LXI B, 0000
C ← 00
9003 3A 00 91 LDA 9100 ; A ← [9100]
9006 D6 64 L2 : SUI 64 ; A ← A – 64
DA 0F ; If carry,
9008 JC L1
90 jump to L1
900B 04 INR B ;B ←B+1
900C C3 06 90 JMP L2 ; Jump to L2
900F C6 64 L1 : ADI 64 ; A ← A + 64
9011 D6 0A L4 : SUI 0A ; A ← A – 0A
DA 1A ; If carry,
9013 JC L3
90 jump to L3
9016 0C INR C ;C ←C+1
9017 C3 11 90 JMP L4 ; Jump to L4
901A C6 0A L3 : ADI 0A ; A ← A + 0A
901C 32 00 92 STA 9200 ; [9200] ← A
901F 79 MOV A, C ;A ←C
9020 32 01 92 STA 9201 ; [9201] ← A
9023 78 MOV A, B ;A ←B
9024 32 02 92 STA 9202 ; [9202] ← A
9027 CF RST 1 ; Reset
Expt. No: 2.b Page No:

Expt. Name: HEX TO BCD CONVERSION Date:

Aim:

To write an ALP to convert a given HEX number to BCD number.

Algorithm:

1. Clear one register pair (BC) for storing hundreds and tens
2. Load the accumulator with the HEX number from a memory address
3. Subtract 64H (100D) from accumulator
4. Check for carry, if there is carry go to step 7
5. Increment Reg B
6. Go to step 3
7. Add 64H (100D) to accumulator
8. Subtract 0AH (10D) from accumulator
9. Check for carry, if there is carry go to step 12
10. Increment Reg C
11. Go to step 8
12. Add 0AH (10D) to accumulator
13. Store the ones in accumulator in a memory location
14. Move the tens in Reg C to accumulator
15. Store the tens in accumulator in a memory location
16. Move the hundreds in Reg B to accumulator
17. Store the hundreds in accumulator in a memory location
18. Stop
Sample Data:

Input Output

9100 – FE 9200 – 04 (1’s)

9201 – 05 (10’s)

9202- 02 (100’s)
Program:

LXI B, 0000
LDA 9100
L2 : SUI 64
JC L1
INR B
JMP L2
L1 : ADI 64
L4 : SUI 0A
JC L3
INR C
JMP L4
L3 : ADI 0A
STA 9200
MOV A, C
STA 9201
MOV A, B
STA 9202
RST 1

Result:

The ALP for converting a given HEX number to BCD number was executed and its
output verified.
Program Format (HEXA TO ASCII)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 3A 00 91 LDA 9100 ; A ← [9100]
9003 C6 30 ADI
30 ; A ←A+B
CPI
9005 FE 39 39 ;A-39
9007 ;if zero go to
CA 0F 90 JZ LOOP:
loop

;If carry go to
900A D2 0F 90 JC LOOP:
loop

900D C6 07 ADI 07 ; A ←A+07

900F 32 01 91 LOOP: STA 9101 ; [9100] ← A

9012 CF RST 1 ;Reset

Program Format (ASCII TO HEXA )

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 3A 00 91 LDA 9100 ; A ← [9100]
9003 D6 30 SUI
30 ; A ←A-B
CPI
9005 FE 09 09 ;A-09
9007 ;if zero go to
CA 0F 90 JZ LOOP
loop

;If carry go to
900A D2 0F 90 JC LOOP
loop

900D D6 07 SUI 07 ; A ←A-07

900F 32 01 91 LOOP: STA 9101 ; [9100] ← A

9012 CF RST 1 ;Reset

Expt. No: 3 c&d Page No:

Expt. Name: HEXA TO ASCII AND ASCII TO HEXA Date:

AIM:To convert hexa to ASCII and ASCII to hexa.

ALGORITHM:

HEXA TO ASCII
1. Load accumulator with the hexa data
2. if the data is less than or equal to 09 add 30.
3. if the data is greater than 09 add 37.
4. store the result in memory
5. stop

ASCII TO HEXA

1. Load accumulator with the hexa data

2. if the data is less than or equal to 09 subtract 30.
3. if the data is greater than 09 subtract 37.
4. store the result in memory
5. stop

HEXA TO ASCII
LDA 9100
ADI A,30
CPI 39
JZ LOOP
JC LOOP
ADI A,07,
LOOP:STA 9101
RST 1

SAMPLE DATA
I/P 9100-00 9100-09 9100-0E
O/P 9101-30 9101-39 9101-45

ASCII EQUIVALENT FOR HEXA

0-9- 30-39
A-41,B-42,C-43,D-44,E-45,F-46
ASCII TO HEXA
LDA 9100
SUI A,30
CPI 39
JZ LOOP
JC LOOP
SUI A,07,
LOOP:STA 9101
RST 1

SAMPLE DATA

I/P 9100-32 9100-39 9100-46

O/P 9101-02 9101-09 91010F

Result: The program for converting hexa to ASCII and ASCII to hexa was executed.
Program Format: ( largest of an array)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; H ← 91
9000 21 00 91 LXI H, 9100
L ← 00
9003 06 07 MVI
B, 07 ; B ← 07

9005 7E MOV A, M ;A←M

9006 ; HL ← HL +
23 L2 : INX H
1
; Compare A
9007 BE CMP M
and M

; If no carry,
9008 D2 0C 90 JNC L1
jump to L1

900B 7E MOV A, M ;A←M

900C 05 L1 : DCR B ;B ←B-1
; If no zero,
900D C2 0C 90 JNZ L2
jump to L2
9010 32 00 92 STA 9200 ; [9200] ← A
9013 CF RST 1 ; Reset
Expt. No: 3a Page
No:

Expt. Name: SEARCH LARGEST IN AN ARRAY Date:

Aim:

To write an ALP to search the largest value in an array.

Algorithm:

1. Initialize one register pair (HL) with the starting address of the array
2. Initialize one register (Reg B) with one count less than the length of the
array
3. Move the memory content to accumulator
4. Increment HL pair
5. Compare the contents of accumulator and memory
6. Check for carry, if no carry, go to step 8
7. Move the memory content to accumulator
8. Decrement Reg B
9. Check for zero, if not zero, go to step 4
10. Store the accumulator content in a memory location
11. Stop
Sample Data:

Input Output

9100 – 08

9101 – 0A

9102 – 02

9103 – 0C 9200 – 19

9104 – 08

9105 – 06

9106 – 00

9107 – 19
Program:

LXI H, 9100
MVI B, 07
MOV A, M
L2 : INX H
CMP M
JNC L1
MOV A, M
L1 : DCR B
JNZ L2
STA 9200
RST 1

Result:

The ALP to search the largest value in an array was executed and its output
verified.
Program Format: (smallest of an array)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
; H ← 91
9000 21 00 91 LXI H, 9100
L ← 00
9003 06 07 MVI
B, 07 ; B ← 07

9005 7E MOV A, M ;A←M

9006 ; HL ← HL +
23 L2 : INX H
1
; Compare A
9007 BE CMP M
and M

; If carry,
9008 DA 0C 90 JC 900C(L1)
jump to L1

900B 7E MOV A, M ;A←M

900C 05 L1 : DCR B ;B ←B–1
; If no zero,
900D C2 0C 90 JNZ 9006(L2)
jump to L2
9010 32 00 92 STA 9200 ; [9200] ← A
9013 CF RST 1 ; Reset
Expt. No: 3b Page No:

Expt. Name: SEARCH SMALLEST IN AN ARRAY Date:

Aim:

To write an ALP to search the smallest value in an array.

Algorithm:

1. Initialize one register pair (HL) with the starting address of the array
2. Initialize one register (Reg B) with one count less than the length of the
array
3. Move the memory content to accumulator
4. Increment HL pair
5. Compare the contents of accumulator and memory
6. Check for carry, if there is carry, go to step 8
7. Move the memory content to accumulator
8. Decrement Reg B
9. Check for zero, if not zero, go to step 4
10. Store the accumulator content in a memory location
11. Stop
Sample Data:

Input Output

9100 – 08

9101 – 0A

9102 – 02

9103 – 0C 9200 – 00

9104 – 08

9105 – 06

9106 – 00

9107 – 19
Program:

LXI H, 9100
MVI B, 07
MOV A, M
L2 : INX H
CMP M
JC L1
MOV A, M
L1 : DCR B
JNZ L2
STA 9200
RST 1

Result:

The ALP to search the smallest value in an array was executed and its output
verified.
Program Format: ( ascending order)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 06 07 MVI
B, 07 ; B ← 07
; H ← 91
9002 21 00 91 L3 : LXI H, 9100
L ← 00
9005 0E 08 MVI
C, 08 ; C ← 08

9007 0D DCR C ;C←C–1

9008
7E L2 : MOV A, M ;A←M
; HL ← HL +
9009 23 INX H
1
; Compare A
900A BE CMP M
and M
; If carry,
900B DA 13 90 JC 9013(L1) jump to L1

900E 56 MOV D, M ;D ←M
900F 77 MOV M, A ;M ←A
; HL ← HL –
9010 2B DCX H
1
9011 72 MOV M, D ;M ←D
; HL ← HL +
9012 23 INX H
1
9013 0D L1 : DCR C ;C←C–1
; If no zero,
9014 C2 08 90 JNZ 9008(L2)
jump to L2
9017 05 DCR B ;B←B–1
; If no zero,
9018 C2 02 90 JNZ L3
jump to L3
901B CF RST 1 ; Reset
Expt. No: 3c Page No:

Expt. Name: SORTING – ASCENDING ORDER Date:

Aim:

To write an ALP to sort an array in ascending order.

Algorithm:

1. Initialize one register (Reg B) with one count less than the length of the
array
2. Initialize one register pair (HL) with the starting address of the array
3. Initialize one register (Reg C) with the length of the array
4. Decrement the inner counter - Reg C
5. Move the memory content to accumulator
6. Increment HL pair
7. Compare the contents of accumulator and memory
8. Check for carry, if there is carry, go to step 13
9. Move the memory content to Reg D
10. Move the accumulator content to memory
11. Decrement HL pair
12. Move the content of Reg D to memory
13. Increment HL pair
14. Decrement the inner counter – Reg C
15. Check for zero, if not zero, go to step 5
16. Decrement the outer counter - Reg B
17. Check for zero, if not zero, go to step 2
18. Stop
Sample Data:

Input Output

9100 – 08 9100 – 00

9101 – 0A 9101 – 02

9102 – 02 9102 – 06

9103 – 0C 9103 – 08

9104 – 08 9104 – 08

9105 – 06 9105 – 0A

9106 – 00 9106 – 0C

9107 – 19 9107 – 19
Program:

MVI B, 07
L3 : LXI H, 9100
MVI C, 08
DCR C
L2 : MOV A, M
INX H
CMP M
JC L1
MOV D, M
MOV M, A
DCX H
MOV M, D
L1 : INX H
DCR C
JNZ L2
DCR B
JNZ L3
RST 1

Result:

The ALP to sort an array in ascending order was executed and its output
verified.
Program Format: (descending order)

Memory Machine Mnemonics

Label Comments
Address Code Op-code Operand
9000 06 07 MVI
B, 07 ; B ← 07
; H ← 91
9002 21 00 91 L3 : LXI H, 9100
L ← 00
9005 0E 08 MVI
C, 08 ; C ← 08

9007 0D DCR C ;C←C–1

9008
7E L2 : MOV A, M ;A←M
; HL ← HL +
9009 23 INX H
1
; Compare A
900A BE CMP M
and M
; If no carry,
900B DA 13 90 JNC L1
jump to L1
900E 56 MOV D, M ;D ←M
900F 77 MOV M, A ;M ←A
; HL ← HL –
9010 2B DCX H
1
9011 72 MOV M, D ;M ←D
; HL ← HL +
9012 23 INX H
1
9013 0D L1 : DCR C ;C←C–1
; If no zero,
9014 C2 08 90 JNZ L2
jump to L2
9017 05 DCR B ;B←B–1
; If no zero,
9018 C2 02 90 JNZ L3
jump to L3
901B CF RST 1 ; Reset
Expt. No: 3d Page No:

Expt. Name: SORTING – DESCENDING ORDER Date:

Aim:

To write an ALP to sort an array in descending order.

Algorithm:

1. Initialize one register (Reg B) with one count less than the length of the
array
2. Initialize one register pair (HL) with the starting address of the array
3. Initialize one register (Reg C) with the length of the array
4. Decrement the inner counter - Reg C
5. Move the memory content to accumulator
6. Increment HL pair
7. Compare the contents of accumulator and memory
8. Check for carry, if there is no carry, go to step 13
9. Move the memory content to Reg D
10. Move the accumulator content to memory
11. Decrement HL pair
12. Move the content of Reg D to memory
13. Increment HL pair
14. Decrement the inner counter – Reg C
15. Check for zero, if not zero, go to step 5
16. Decrement the outer counter - Reg B
17. Check for zero, if not zero, go to step 2
18. Stop
Sample Data:

Input Output

9100 – 08 9100 – 19

9101 – 0A 9101 – 0C

9102 – 02 9102 – 0A

9103 – 0C 9103 – 08

9104 – 08 9104 – 08

9105 – 06 9105 – 06

9106 – 00 9106 – 02

9107 – 19 9107 – 00
Program:

MVI B, 07
L3 : LXI H, 9100
MVI C, 08
DCR C
L2 : MOV A, M
INX H
CMP M
JNC L1
MOV D, M
MOV M, A
DCX H
MOV M, D
L1 : INX H
DCR C
JNZ L2
DCR B
JNZ L3
RST 1

Result:

The ALP to sort an array in descending order was executed and its output
verified.
 STUDY OF 8051 MICROCONTROLLER

AIM:

To study the 8051 microcontroller.

SPECIFICATIONS OF 8051 MICRICONTROLLER:

Internal ROM or EPROM of 0 to 4k byte memory.
Internal RAM of 128 bytes.
32 I/O pins arranged as four 8 bit ports P0-P3.
Two 16 bit timer/counter T0 and T1.
Two external and three internal interrupt source.
Operating frequency 1MHZ to 16MHZ.
Full duplex serial data receiver/transmitter SBUF.
8 bit CPU with register A and B.

SPECIFICATION OF 89C51 MICROCONTROLLER:

Compatible with 19CS-51 products.
8k byte of in-system re-programmable flash memory.
Endurance-1000 write/erase cycle.
Fully 3 level program memory lock.
Fully static memory operation- 0Hz to 24Hz.
256x8 bit internal RAM.
32 programmable I/O lines.
Three 16 bit timer/counter.
8 interrupt source.
Programmable serial channel.
Low power idle and power down modes.

SPECIAL FUNCTION REGISTERS:

The 8051 operations that do not use the internal 128-byte RAM addresses
from 00h to 7fh are done by a group of specific internal registers, each called as
special function registers. SFR may be addressed much like internal RAM using
address from 80h to ffh.
IE REGISTER: (Interrupt enable)

The interrupt sources can be individually enable or disable by setting or

clearing a bit in SFR IE. And also interrupt register contains a global disable bit EA
which disable all interrupt at once.

SYMBOL POSITION NAME AND SIGNIFICANCE

Enable all control bit. Cleared by s/w to disable all interrupts,
EA IE.7 Set to
1 to permit individual interrupt.
- IE.6 (Reserved)
ET2 IE.5 (Reserved)
ES IE.4 Enable serial port interrupt
ET1 IE.3 Enable timer 1 overflow bit
EX1 IE.2 Enable external interrupt
ET0 IE.1 Enable timer 0 overflow bit
EX0 IE.0 Enable external interrupt 0

IP REGISTER: (Interrupt priority)

Each interrupt source can be individually programmed to one of two

priority by setting or clearing a bit in SFR.

SYMBOL POSITION NAME AND SIGNIFICANCE

- IP.7 Not implemented
- IP.6 Not implemented
PT2 IP.5 Reserved for future use
PS IP.4 Priority of serial port s/c by program
PT1 IP.3 Priority of timer 1 overflow bit
PX1 IP.2 Priority of external interrupt 1
PT0 IP.1 Priority of timer 0 overflow interrupt
PX0 IP.0 Priority of external interrupt 0

PCON REGISTER: (Power Mode Control)

It controls the data rate

SYMBOL POSITION NAME AND SIGNIFICANCE

SMOD PCON.7 Serial baud rate modify. Set 1 to double baud rate.
- PCON 6-4 Not defined (or ) not implemented
GF1 PCON.3 General purpose user flag bit 1
GF0 PCON.2 General purpose user flag bit 0
PD PCON.1 Power down bit
IDL PCON.0 Idle mode bit
THE TIMER CONTROL (TCON):

TCON has control bits and flags for the timers in the upper nibble and control
bits and flag for the external interrupt in the lower nibble.

BIT SYMBOL FUNCTION

7 TF1 Timer1 overflow flag
6 TR1 Timer1 run control bit
5 TF0 Timer0 overflow flag set when timer rolls from 1s to 0 cleared when
processor vectors to execute interrupt service routine located at
program
address 000Bh
Timer0 run control bit set to 1 program to enable timer to count
4 TR0 cleared
to 0 by program by half timer
3 IE1 External interrupt 1 edge flag
2 IT1 External interrupt 1 signal type control bit
1 IE0 External interrupt 0 edge 7 flag
0 IT0 External interrupt 0 signal type control bit

THE TIMER MODE CONTROL (TMOD):

TMOD is dedicated to two timers and can be consider to the two duplicate 4 bit
registers each of which control actions of one of timers.

BIT SYMBOL FUNCTION

7/3 Gate Gating control
6/2 C/T Timer/counter selector
5/1 M1 Timer/counter operating mode select bit 1
set/cleared by program to select mode
4 /0 M0 Timer/counter operating mode select bit 0
set/cleared by program to select mode

THE SERIAL PORT CONTROL (SCON):

SCON controls data communication.

BIT SYMBOL FUNCTION

7 SM0 Serial port mode bit 0 set/cleared by program to select mode
6 SM1 Serial port mode bit 1 set/cleared by program to select mode
5 SM2 Multiprocessor communication bit
4 REN Receive enable bit
3 TB8 Transmitted bit 8
2 RB8 Received bit 8
1 TI Transmit interrupt flag
0 RI Receive interrupt flag
SBUF:
SBUF is an 8 bit register dedicated for serial communication
in 8051. It can be accessed like any other register.

TRANSMISSION:

When a byte of data is to be transmitted via the TX0 pin. The SBUF is
loaded with datatype.

RECEPTION:

When 8051 receives data serially via RXO pin of it, the 8051 de
frames it. The start and stop bit are separated out from a byte of data.

PORTS IN 8051 MICROCONTROLLER:

PORT 0:

Port 0 is an 8 bit port. It is bidirectional. As an output port it can risk

high TTL inputs when 1’s.

PORT 1:

Port 1 is an 8 bit bidirectional I/O port with internal pull ups. The
ports pins are externally being pulled low. Its source current(TTL) is high
because of the internal pull ups.

PORT 2:
It is an 8 bit bidirectional I/O ports with internal for TTL
inputs. It accesses to external data memory that use 16 bit
address.

PORT 3:

It is an 8 bit bidirectional port with internal pull ups. Each

pin of the port will have special features. The special features are
given in the below table.
PIN ALTERNATIVE FUNCTIONS
P3.0 RXD(switch input port)
P3.1 TXD(serial output port)
P3.2 INTO(external interrupt 0)
P3.3 INT1(external interrupt 1)
P3.4 T0(Timer 0 external input)
P3.5 T1(Timer 1 external input)
P3.6 WR(external write data memory)
P3.7 RD(external read data memory)
XTAL1:

Input to the inverting oscillator amplifier and input to the internal clock
operating circuit.

XTAL2:
Output from the inverting oscillator amplifier.

PIN DIAGRAM OF 8051:

RESULT:

Thus the study of 8051 microcontroller is completed

Expt. No: 4 a&b Page No:

Expt. Name: FILL INTERNAL AND EXTERNAL MEMORY Date:

AIM: To perform filling of internal and external memory with 10 data.

ALGORITHM

TO FILL INTERNAL MEMORY

1. Initialize ro with the starting address.

2. Initialize r1 with the count.
3. move the data to be filled to a.
4. move the data from a to the content of ro.
5. inc ro.
6. decrement r1 and repeat step 4 till r1 reaches 0.
7. stop.

TO FILL EXTERNAL MEMORY

1. Initialize dptr with the starting address.

2. Initialize r1 with the count.
3. move the data to be filled to a.
4. move the data from a to the content of dptr.
5. inc dptr.
6. decrement r1 and repeat step 4 till r1 reaches 0.
7. stop.
PROGRAM

To fill internal memory

mov r0,#50
mov r1,#0a
mov a,#99
loop: mov @ro,a
inc ro
djnz r1,loop
lcall oobb

sample data

I/P
A-99

O/P
50-59 filled with 99

To fill external memory

mov dptr,#9100
mov r1,#0a
mov a,#77
loop: movx @dptr,a
inc dptr
djnz r1,loop:
lcall oobb

sample data

I/P
A-77

O/P
9100-9109 filled with 77

Result: The program to fill internal and external memory was executed.
Expt. No: 4 c.d.e Page No:

Expt. Name: INTERNAL TO EXTERNAL ,EXTERNAL TO

INTERNAL AND WITHIN EXTERNAL Date:

AIM: To perform filling of internal and external memory with 10 data.

ALGORITHM
INTERNAL TO EXTERNAL MEMORY

1. Initialize ro with the source address

2. Initialize dptr with the destination address.
3. Initialize r1 with the count.
4. move the content of ro to a.
5. move the data from a to the content of dptr.
6. inc ro.
7. inc dptr
8. decrement r1 and repeat from step 4 till r1 reaches 0.
9. stop.

EXTERNAL TO INTERNAL
1. Initialize dptr with the source address
2. Initialize ro with the destination address.
3. Initialize r1 with the count.
4. move the content of dptr to a.
5. move the data from a to the content of ro.
6. inc ro.
7. inc dptr
8. decrement r1 and repeat from step 4 till r1 reaches 0.
9. stop.

WITHIN EXTERNAL

1. Initialize dptr with the source address(9100)

2. Initialize r1 with the count.
3. move the content of dptr to a.
4. change the dph to dest address(92)
5. move the a value to content of dptr(destination).
6. inc dptr
7. change the dph to source address(91).
8. decrement r1 and repeat from step 3 till r1 reaches 0.
9. stop.

PROGRAM
Internal to external

mov r0,#50
mov dptr,#9100
mov r1,#0a
loop: mov a,@ro
movx @dptr,a
inc ro
inc dptr
djnz r1,loop
lcall oobb

sample data

I/P
50-59 (give the data i/p)

O/P
9100-9109 (see the output)

External to internal

mov r0,#50
mov dptr,#9100
mov r1,#0a
loop: movx a,@dptr
mov @ro,a
inc ro
inc dptr
djnz r1,loop
lcall oobb

sample data

I/P
9100-9109 (give the data i/p)

O/P
50-59(see the output)
External to external

mov dptr,#9100
mov r1,#0a
loop: movx a,@dptr
mov 83,#92
movx @dptr,a
inc dptr
mov 83,#91
djnz r1,loop
lcall oobb

sample data

I/P
9100-9109 (give the data i/p)

O/P
9200-9209(see the output)

Result: The program to transfer internal to external, external to internal and external to external
are executed
Expt. No: 5 Page No:

Expt. Name:LOGICAL AND BIT MANIPULATION INSTRUCTION Date:

AIM:

To write a program using logical and bit manipulation instruction.

ALGORITHM:

BIT MANIPULATION(check whether given number is odd or even)

1. initialize the starting address in ro.

2. check for even or odd by using bit manipulation instruction.
3. If there is carry after rotating then it is odd no orelse even no.
4. stop.

LOGICAL INSTRUCTION

1. initialize the starting address in ro and destination address in r1.

2. separate and store the upper nibble of the data in destination.
3. repeat till count becomes zero
4. stop.

PROGRAMS

a)BIT MANIPULATION
MOV R0,#50
MOV A,@RO
RRC A
JC L1:
MOV 51,#OE
L1: LCALL 00BB
MOV 51,#0D
LCALL 00BB

SAMPLE DATA
I/P 50-32 50-39
O/P 51-EVEN 51-ODD
b) BIT MANIPULATION
mov ro,#20
jb 27,l1
mov 51,#oe
lcall 00bb
l1: mov 51,#0d
lcall 00bb

SAMPLE DATA
I/P 20-32 20-39
O/P 51-EVEN 51-ODD

LOGICAL INSTRUCTION
MOV R0,#50
MOV R1,#60
MOV R2,#05
LOOP: MOV A,@RO
ANL A,#of0
RRA
RRA
RRA
RRA
MOV @R1,A
INC RO
INC R1
DJNZ R2,LOOP:
LCALL 00BB

SAMPLE DATA
I/P 50-10 51-25 52-38 53-49 54-56
O/P 60-01 61-02 62-03 63-04 64-05

Result: The program using logical and bit manipulation instruction was executed.
Expt. No: 6a Page No:

Expt. Name: OPERATION ON PORT BITS Date:

AIM:

To write a program to operate the port bits

ALGORITHM:
1.set the bit 0 of port 1
2.call delay routine
3.clr bit 0 of port 1
4.call delay routine
5.repeat from step 1

Delay
1.initialize one reg
2.decrement that reg till it becomes zero. 3.return to main program.

PROGRAM
L1: SETB 90
LCALL DELAY(9100)
CLR 90
LCALL DELAY(9100)
SJMP L1:

9100DELAY:
MOV RO,#44
L1: DJNZ RO,L1
RET

Output
Square wave

Result
The program to operate the port bits was executed.
Expt. No: 6b Page No:

Expt. Name: TRAFFIC LIGHT CONTROLLER Date:

AIM:
To control the traffic as per the sequence

ALGORITHM:

1. Initialize port A of 8255 as output port.

2. find the hex data to glow the corresponding lights in the traffic sequence.
3. repeat .

Find Hex data using the given sequence by seeing the diagram

SEQUENCE VEHICLE PEDESTRIAN FREE

LEFT
N S E W N S E W ON
I R R G G R R R R ON
II Y Y Y Y R R R R ON
III G G R R R R R R ON
IV Y Y Y Y R R R R ON
V R R R R G G G G OFF

Hex data to be given to the traffic light controller

SEQ PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 HEX DATA
UENCE
I 0 1 0 0 1 1 0 1 4D
II 0 0 1 1 1 0 0 1 39

III 1 0 0 0 1 0 1 1 8B
IV 0 0 1 1 1 0 0 1 39

V 1 1 0 0 0 0 0 0 C0

SEQ PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 HEX
UENCE DATA
I 0 0 0 0 1 1 1 1 0F
II 0 0 0 0 1 1 1 1 0F

III 0 0 0 0 1 1 1 1 0F
IV 0 0 0 0 1 1 1 1 0F

V 1 1 1 1 0 0 0 0 F0
TRAFFIC INTERFACE CARD

G G G
CO A1 AO
A5 Y
A6 R

G A3 Y R R Y G A3
G A2 A4 A7 A7 A4 G A2
G C1 G C1

A6 R
A5 Y
CO A1 AO
G G G
N

W E

PROGRAM:

MOV DPTR,#4003
MOV A,#80
MOVX @DPTR,A
L2: MOV 82,#00
MOV A,#4D
MOVX @DPTR,A
MOV 82,#01
MOV A,#0F
MOVX @DPTR,A
LCALL 9100(DELAY)
LCALL 9200(AMBER)
MOV 82.#00
MOV A,#8B
MOVX @DPTR,A
LCALL 9100(DELAY)
 LCALL 9200(AMBER)
MOV 82,#00
MOV A,#C0
MOVX @DPTR,A
MOV 82,#01
MOV A,#FO
MOVX @DPTR,A
LCALL 9100(DELAY)
LCALL 9100(DELAY)
LJMP 9006(L1:)

AMBER(9200)
MOV 82,#00
MOV A,#39
MOVX @DPTR,A
MOV 82,#01
MOV A,#0F
MOVX @DPTR,A
LCALL 9100(DELAY)
RET

DELAY(9100)
MOV R0,#3C
L4: MOV R1,#FF
L3: MOV R2,#FF
L2: DJNZ R2,9106(L2:)
DJNZ R1,9104(L3:)
DJNZ R0,9102(L4:)
RET

Result: The traffic light controller was executed.

Expt. No: 7 a&b Page
No:

Expt. Name: STEPPER MOTOR CONTROLLER Date:

AIM:

To rotate the stepper motor clockwise and anticlockwise direction.

ALGORITHM:

1. Initialize port A of 8255 as output port.

2. Load the step sequence in an array.
3. out the step sequence through port A to the stepper motor
4. Call the delay in between the step sequence.
5. send the 4 step sequence.(reverse the step sequence for anticlock wise)
6. delay decreases speed increases(inversely proportional)
7. repeat unconditionally so that the motor rotate continuously.

Program

STEPPER MOTRO CONTROLLER (ANTICLOCKWISE)

MOV DPTR,#4003
MOV A,#80
L1: MOVX @DPTR,A
MOV DPTR,#4000
MOV A,#C6
MOVX @DPTR,A
LCALL DELAY
MOV A,#84
MOVX @DPTR,A
LCALL DELAY
MOV A,#A5
MOVX @DPTR,A
LCALL DELAY
MOV A,#E7
MOVX @DPTR,A
LCALL DELAY
LJMP L1:
STEP SEQUENCE ANITCLOCKWISE
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA1 HEXA
VALUE
SUPPLY A B X X SUPPLY A B -
1 1 0 0 0 1 1 1 C6
1 0 0 0 0 1 0 0 84
1 0 1 0 0 1 1 0 A5
1 1 1 0 0 1 1 0 E7

FOR CLOCK WISE E7,A5,84,C6

Result: Stepper motor was rotated clockwise and anticlockwise direction.

Expt. No: 8a Page No:

Expt. Name: 7-SEGMENT LED Date:

AIM:
To blink 1 using 7-segment LED.
ALGORITHM:

1. Initialize port A of 8255 as output port.

2. send the data to flash ‘1’ through port A.
3. repeat .
PROGRAM

MOV DPTR,#4003
MOV A,#80
MOVX @DPTR,A
L1:MOV DPTR,#4000
MOV A,#06
MOVX @DPTR,A
LCALL DELAY
MOV A,#00
MOVX @DPTR,A
LCALL DELAY
LJMP L1:

DELAY
MOV R0,#FF
L3:MOV R1,#FF
L2:DJNZ R1,L2:
DJNZ R0,L3:
RET

Figure shows Common cathode and common anode 7 segment LED

Result: The 7 segment LED flashed ‘1’.

Expt. No: 8 b Page
No:

Expt. Name: DIGITAL IC TESTING Date:

AIM:
To test the given IC is working or not.
ALGORITHM:

1. Initialize port A of 8255 as output port.

2. send 1 and 0 for checking not gate.
3. the LED is connected to the output of the IC so the LED blinks.
4. repeat

MOV DPTR,#4003
MOV A,#80
MOVX @DPTR,A
L1:MOV DPTR,#4000
MOV A,#01
MOVX @DPTR,A
LCALL DELAY(9100)
MOV A,#00
MOVX @DPTR,A
LCALL DELAY(9100)
LJMP L1:

9100: DELAY
MOV R0,#FF
L3:MOV R1,#FF
L2:DJNZ R1,L2:
DJNZ R0,L3:
RET

Result: The 7404 IC was tested

KIT ENTERING PROCEDURE

1. TO ENTER THE PROGRAM 4.TO CHECK THE PROGRAM

-A9000 -D9000(FOR EXAMPLE)

MVI C,00 SPACE BAR

NEXT INSTRUCTION .

RST 1

2. TO ENTER DATA

-M9100(FOR EXAMPLE)

DATA 1

SPACE BAR

DATA 2

SPACE BAR

3. TO EXECUTE THE PROGRAM

- G9000(FOR EXAMPLE)

4. TO SEE THE RESULT

-MRESULT LOCATION(FOR EG(9102))

RESULT 1

SPACE BAR

RESULT 2