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6 Bit Wallace Tree Multiplier - Complete - Final

The document discusses the design and implementation of a 6-bit Wallace Tree Multiplier, highlighting its advantages over an Array Multiplier in terms of delay and area optimization. It includes detailed components such as schematics, layouts, and simulations for various gates like AND, OR, XOR, Half Adder, and Full Adder. The complete circuit specifications are provided, including area, delay measurements, and the methodology for reducing stages in the multiplier design.

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Zulfaquar Alam
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14 views50 pages

6 Bit Wallace Tree Multiplier - Complete - Final

The document discusses the design and implementation of a 6-bit Wallace Tree Multiplier, highlighting its advantages over an Array Multiplier in terms of delay and area optimization. It includes detailed components such as schematics, layouts, and simulations for various gates like AND, OR, XOR, Half Adder, and Full Adder. The complete circuit specifications are provided, including area, delay measurements, and the methodology for reducing stages in the multiplier design.

Uploaded by

Zulfaquar Alam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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IVLSI 6 Bit Wallace Tree Multiplier

Contents:
• Background Theory (Wallace tree Multiplier delay compared to Array Multiplier, reduction of stages)
• Basic components: Schematic/layout(should be able to recognise comp/drv/lvs/graphs of each component)
• Complete circuit -schematic/layout/drc/lvs/waveform, specs:area,delay, total number of components
• Questions to be answered: how did you optimize area?
• Basic procedure: symbol/tb/layout link
Background Theory:
http://www.csbio.unc.edu/mcmillan/Comp411F15/Lecture12.pdf

http://www.micro.deis.unibo.it/~baccaran/Rabaey/chapter11.pdf
Parallel addition of partial products does not take bits from previous coloumn unlike array multiplier.
Direct Implementation of schematic shown in slide
Procedure for reduction of stages:

• Whenever there are three bits in a coloumn use FA as 3:2 compressor


• Use HA as 2:2 compressor only when it will produce a product bit
• The picture on next page shows reduction using this method, it is different from textbook method only from stage 2 to
final ripple carry stage
Complete circuit

• Vdd=1.8V
• Area= 60.49um *259.51um=15723.71 um^2 =0.015725 mm^2
• How did you measure delay ? Testbench used?
• Delay for the sequence (101101 x 100111= 0110 1101 1011) = 1.39 ns

Measuring Area:
Wallace Tree Multiplier:

Wallce Tree Multiplier Schematic

Full-adders with a binary ‘0’ as one of the inputs were replaced with half-adders.

Wallce Tree Multiplier Symbol


Wallace Tree Multiplier Test Bench

Simulations:
All the inputs were defined as with a voltage waveform defined by “vpulse”. Active high voltage was used with binary ‘1’
being represented by voltage level of ‘1v’, and binary ‘0’ being represented by a voltage level of ‘0v’.
Binary ‘1’ was defined by “vpulse” by giving ‘v1’ and v2’ as 0v and 1v. Binary ‘0’ was similarly defined but both ‘v1’
and ‘v2’ were given a voltage level of ‘0v’.
Combination 1:
Combination 2:
Wallace Tree Layout

Wallace Tree Multiplier Layout (Zoomed in)


DRC for Complete Wallace Tree Multiplier

LVS Check for complete Wallace Tree Multiplier


AV extraction Wallace Tree:

They are parasitic capacitances, which are side effects formed by different layers you used for your layout

More info on this


Basic Components:

• And Gate
• OR Gate
• XOR Gate
• Half Adder
• Full Adder
AND Gate:

1. Transistor level schematic:

Inputs: A,B.
Output: vout
2. Layout
3.LVS

4.DRC
5. Symbol

6. Testbench Schematic
7. Output simulations

i/p A 1 1

0 0

i/p B 1 1
0
0

o/p

0 0 0
OR Gate:

1. Transistor level schematic


Inputs: A,B
Output:vout
2. Layout vdd

o/p

i/p A

i/p B

gnd
3. DRC

4.LVS
5.Symbol

6. Testbench Schematic
7. Output Simulations

i/p 1 1
A
0 0

i/p B
1 1
0 0

o/p
1 1
1
0

As observed from the graph the output simulation match that of the truth table shown below.
XOR Gate:

Previously implemented schematic/layout of XOR with NAND gates(16 Fets):


! Schematic
Previously XOR gate was implemented with NAND gates, the current XOR gate has been implemented with
transmission gate logic to optimize for area . Six FETs are used here.

• Layout

Input A
Vdd rail

Output
Input B

ground rail
! DRC

! LVS
! Symbol

•
Test bench Schematic

! Output Simulations

1 1 1 1 1
0 0 0 0

1 1 1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0 0

1
1 1 1 1
0 0 0 0 0
Half Adder:

! Schematic

! Layout
vdd rail i/p A,B

Carry

ground rail Sum


! DRC
! LVS

! Symbol

! Test bench schematic


"
Full Adder:

! Schematic

! Layout
Vdd rail
i/p A,B
Carry out Cin

sum

ground rail
! DRC

! LVS
! Symbol

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