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Library Ieee Use Ieee - STD - Logic - 1164.all

A library stores information about a design project. A VHDL package contains commonly used declarations that can be shared between models. To use items from the std_logic_1164 package, the library and use keywords must specify ieee library and ieee.std_logic_1164 package at the start of a VHDL file. Xilinx Foundation Express includes packages like std_logic_1164 for standard datatypes and std_logic_arith for arithmetic functions. User-defined packages can declare components and their architectures. The library and use clauses allow other files to access declarations from packages.

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223 views4 pages

Library Ieee Use Ieee - STD - Logic - 1164.all

A library stores information about a design project. A VHDL package contains commonly used declarations that can be shared between models. To use items from the std_logic_1164 package, the library and use keywords must specify ieee library and ieee.std_logic_1164 package at the start of a VHDL file. Xilinx Foundation Express includes packages like std_logic_1164 for standard datatypes and std_logic_arith for arithmetic functions. User-defined packages can declare components and their architectures. The library and use clauses allow other files to access declarations from packages.

Uploaded by

Bijay Kumar
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOC, PDF, TXT or read online on Scribd
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c.

Library and Packages: library and use keywords

A library can be considered as a place where the compiler stores information about a design project. A VHDL package is a file or module that contains declarations of commonly used objects, data type, component declarations, signal, procedures and functions that can be shared among different VHDL models.

We mentioned earlier that std_logic is defined in the package ieee.std_logic_1164 in the ieee library. In order to use the std_logic one needs to specify the library and package. This is done at the beginning of the VHDL file using the library and the use keywords as follows:

library ieee; use ieee.std_logic_1164.all;

The .all extension indicates to use all of the ieee.std_logic_1164 package.

The Xilinx Foundation Express comes with several packages.

ieee Library:

std_logic_1164 package: defines the standard datatypes std_logic_arith package: provides arithmetic, conversion and comparison functions for the signed, unsigned, integer, std_ulogic, std_logic and std_logic_vector types std_logic_unsigned std_logic_misc package: defines supplemental types, subtypes, constants and functions for the std_logic_1164 package.

To use any of these one must include the library and use clause: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;

In addition, the synopsis library has the attributes package:

library SYNOPSYS; use SYNOPSYS.attributes.all;

One can add other libraries and packages. The syntax to declare a package is as follows:

-- Package declaration package name_of_package is package declarations end package name_of_package; -- Package body declarations package body name_of_package is package body declarations end package body name_of_package;

For instance, the basic functions of the AND2, OR2, NAND2, NOR2, XOR2, etc. components need to be defined before one can use them. This can be done in a package, e.g. basic_func for each of these components, as follows:

-- Package declaration library ieee; use ieee.std_logic_1164.all; package basic_func is -- AND2 declaration component AND2 generic (DELAY: time :=5ns); port (in1, in2: in std_logic; out1: out std_logic); end component;

end package basic_func;

-- Package body declarations library ieee; use ieee.std_logic_1164.all; package body basic_func is -- 2 input AND gate entity AND2 is generic (DELAY: time); port (in1, in2: in std_logic; out1: out std_logic); end AND2; architecture model_conc of AND2 is begin out1 <= in1 and in2 after DELAY;

end model_conc;

end package body basic_func;

Notice that we included a delay of 5 ns. However, it should be noticed that delay specifications are ignored by the Foundation synthesis tool. We made use of the predefined type std_logic that is declared in the package std_logic_1164. We have included the library and use clause for this package. This package needs to be compiled and placed in a library. Lets call this library my_func. To use the components of this package one has to declare it using the library and use clause:

library ieee, my_func; use ieee.std_logic_1164.all, my_func.basic_func.all;

One can concatenate a series of names separated by periods to select a package. The library and use statements are connected to the subsequent entity statement. The library and use statements have to be repeated for each entity declaration.

One has to include the library and use clause for each entity as shown for the example of the fourbit adder above.

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