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Chap. 8 Datapath Units: Prof. An-Yeu Wu Undergraduate VLSI Course

The document discusses various adder designs including one-bit full adders, carry-ripple adders, transmission-gate adders, carry-lookahead adders, Manchester adders, carry-select adders, conditional-sum adders, and very wide adders. It provides details on the boolean functions, implementations, advantages, and disadvantages of each design. The document was presented by Prof. An-Yeu Wu at National Taiwan University and includes homework on implementing an 8-bit conditional-sum adder.

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58 views32 pages

Chap. 8 Datapath Units: Prof. An-Yeu Wu Undergraduate VLSI Course

The document discusses various adder designs including one-bit full adders, carry-ripple adders, transmission-gate adders, carry-lookahead adders, Manchester adders, carry-select adders, conditional-sum adders, and very wide adders. It provides details on the boolean functions, implementations, advantages, and disadvantages of each design. The document was presented by Prof. An-Yeu Wu at National Taiwan University and includes homework on implementing an 8-bit conditional-sum adder.

Uploaded by

Nitin Raj
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
You are on page 1/ 32

National Taiwan University

Chap. 8 Datapath Units


Prof. An-Yeu Wu Undergraduate VLSI Course
Updated: May 24, 2002

National Taiwan University

Several Implementations of Adders


One-Bit Full Adder (Cell) Carry-Ripple Adder Transmission-Gate Adder Carry lookahead Adder Bit-Serial Adder Carry-Select Adder Conditional- Sum Adder Manchester Adder Very wide Adder

A. Y. Wu

pp. 2

National Taiwan University

One-Bit Full Adder (Cell)


A and B are the adder inputs, C is the carry input, SUM is the sum output, and CARRY is the carry output.

A. Y. Wu

pp. 3

National Taiwan University

Boolean Function
SUM ABC ABC ABC ABC C AB AB C AB AB

A B C CARRY AB AC BC AB C A B ABC A B C CARRY

SUM ABC A B C AB C A B

pp. 4

A. Y. Wu

National Taiwan University

Implementation

A. Y. Wu

pp. 5

National Taiwan University

Implementation (Cont.)

A. Y. Wu

pp. 6

National Taiwan University

Carry-Ripple Adder
Simple & Slow
One stage delay time Tc n stages delay time nTc

A. Y. Wu

pp. 7

National Taiwan University

Bit-Parallel Adder

A. Y. Wu

pp. 8

National Taiwan University

Subtractor

A. Y. Wu

pp. 9

National Taiwan University

Bit-Serial Adder

A. Y. Wu

pp. 10

National Taiwan University

Carry-Save Adder

Use register to store CARRY

A. Y. Wu

pp. 11

National Taiwan University

CPA

A. Y. Wu

pp. 12

National Taiwan University

Transmission-Gate Adder
Use T-G to Implement XOR Gate

A. Y. Wu

pp. 13

National Taiwan University

Transmission-Gate Adder (Cont.)

Total 24 Transistors SUM and CARRY have the same delay time
A. Y. Wu pp. 14

National Taiwan University

Reduced Tx numbers Dont care speed


A. Y. Wu pp. 15

National Taiwan University

Carry-Lookahead Adders
The linear growth of adder carry-delay with the size of the input word for n-bit adder maybe improved by calculation the carries to each stage in parallel.

A. Y. Wu

pp. 16

National Taiwan University

Carry-Lookahead Adders (Cont.)


Carry of the ith stage --Ci=Gi + PiCi-1 Gi=AiBi generate signal Pi=Ai + Bi propagate signal

Expanding Ci= Gi + PiCi-1 + PiPi-1Gi-2 + .. + PiP1P0


For four stages, the appropriate term : C0= G0 + P0CI C1= G1 + P1G0 + P1P0CI C2= G2 + P2G1 + P2P1G0 + P2P1P0CI C3= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0CI Fig1. Generic carry-lookahead adder

A. Y. Wu

pp. 17

National Taiwan University

A. Y. Wu

pp. 18

National Taiwan University

Carry-Lookahead Adders (Cont.)


The size and fan-in of the gates needed to implement this carry-lookahead scheme can clearly get out of hand the number of stages of lookahead is usually limited to about 4. The circuit and layout are quite irregular.

A. Y. Wu

pp. 19

National Taiwan University

Dynamic Carry Gates

The worst-case delay path in this circuit has six ntransistor in series.
A. Y. Wu pp. 20

National Taiwan University

High-speed Carry Lookahead Logic

Use pseudo-nMos to achieve high-speed static operation.


A. Y. Wu pp. 21

National Taiwan University

Manchester Adder Circuits

A. Y. Wu

pp. 22

National Taiwan University

Manchester Adder Circuits (Cont.)


Dynamic stage
When CLK is low, the output node is pre-charged by the p pull-up transistor. When CLK goes high, the pull-down transistor turns on. If carry generate G=AB is true the output node discharges. If carry propagate P=A+B is true a previous carry may be coupled to the output node, conditionally discharging it.

Static stage
This requires P to be generated as AB The Manchester adder stage improves on the carrylookahead implementation.
A. Y. Wu pp. 23

National Taiwan University

Manchester Adder Circuits (Cont.)

The control signals T1,T2,and T3 shown in Fig6(b) are generated by:


T1 = -(P0P1P2)P3 T2 = -P3 T3 = P0P1P2P3
Fig6. Manchester adder with carry bypass: (a) simple (b) conflict free
A. Y. Wu pp. 24

National Taiwan University

Manchester Adder Circuits (Cont.)


The worst case propagation time of a Manchester adder can be improved by bypassing the four stages if all carry-propagate signals are true. Fig. 6(b) uses a conflict -free bypass circuit, which improves the speed by using a 3-input multiplexer that prevents conflicts at the wired OR node in the adder. In Fig. 6(b), the inverter presented on the Cin signal has been moved to the center of the carry chain to improve speed.

A. Y. Wu

pp. 25

National Taiwan University

Carry-Select Adder

Fig7. Carry-select adder:(a) basic architecture (b) 32-bit carry-select adder example

A. Y. Wu

pp. 26

National Taiwan University

Conditional-Sum Adder

A. Y. Wu

pp. 27

National Taiwan University

Conditional-Sum Adder (Cont.)

A. Y. Wu

pp. 28

National Taiwan University

Very Wide Adders

A. Y. Wu

pp. 29

National Taiwan University

Very Wide Adders (Cont.)

A. Y. Wu

pp. 30

National Taiwan University

Very Wide Adders with Bypass

A. Y. Wu

pp. 31

National Taiwan University

Homework #5
- Conditional Sum Adder8-bit - Draw the schematic diagram of your design. - Verify your idea first using C or Matlab programs. - Write down the Verilog code to verify your design.Check your results with the C/Matlab results. - Due date: June 14, 2002

A. Y. Wu

pp. 32

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