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ADSD Lab Record

The document outlines the design and simulation of various types of adders including half adder, full adder, serial binary adder, carry look ahead adder, and multiprecision adder using Cadence nesim and RTL Compiler. It provides theoretical explanations and source code for half and full adders, as well as a detailed description and implementation of the carry look ahead adder. The focus is on the functionality and complexity of these combinational circuits in performing binary addition.

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6 views3 pages

ADSD Lab Record

The document outlines the design and simulation of various types of adders including half adder, full adder, serial binary adder, carry look ahead adder, and multiprecision adder using Cadence nesim and RTL Compiler. It provides theoretical explanations and source code for half and full adders, as well as a detailed description and implementation of the carry look ahead adder. The focus is on the functionality and complexity of these combinational circuits in performing binary addition.

Uploaded by

parokiamarycaroline
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Ex.

no:1 DESIGN OF ADDERS

07/02/22

AIM:

To design and simulate the following adders:

a) Half adder
b) Full adder
c) Serial binary adder
d) Carry look ahead adder
e) Multiprecision adder

SOFTWARE TOOLS:

Cadence nesim, RTL Compiler

a) HALF ADDER:

THEORY:

A combinational circuit that performs the addition of two bits is called a HALF
ADDER. This addition consists of four possible combinations for two inputs designated
as augend and addend bits and its two outputs designated as sum and carry.

SOURCE CODE:

module ha(sum,carry,a,b,);

input a,b;

output sum,carry;

assign carry=a&b;

assign sum=a^b;

endmodule

b) FULL ADDER:

THEORY:

A combinational circuit that performs the addition of three bits (two significant
bit and a previous carry) is called a FULL ADDER. The eight rows under the input
variables designate all possible combinations of the three variables and has two
outputs designated as sum and carry.
SOURCE CODE:

module fa(sum,carry,a,b,c,);

input a,b,c;

output sum,carry;

wire s1,c1,c2;

xor g1(s1,a,b);

and g2(c1,a,b);

xor g3(sum,s1,c);

and g4(c2,s1,c);

xor(carry,c2,c1);

endmodule

c) CARRY LOOK AHEAD ADDER:

THEORY:

The addition of two binary numbers in parallel implies that all the bits of the
augend and addend for computation at the same time. As in any combinational circuit,
the signal must propagate through the gates before the correct output sum is available
in the output terminals. The total propagation time is equal to the propagation delay of
a typical gate, times the number of gates in the circuit. There are techniques for
reducing the carry propagation time in parallel adder. The most widely used technique
employs the principle of CARRY LOOK AHEAD LOGIC.

The longest propagation delay time in an adder is the time it takes the carry to
propagate through the full adders.

If we define new variables Gi is called a carry generate and it produces a carry of 1


when both inputs Ai and Bi are 1, regardless of the input carry Ci.

Pi is called a carry propagate, because it determines whether a carry into stage i will
propagate into stage i+1. Since the Boolean function for each output carry is expressed
in sum of product form, each function can be implemented with one level of AND gates
followed by an OR gate.

Note that this circuit can add in less time because final carry out does not have
to wait for previous stage carries to propagate; in fact, final carry out is propagated at
the same time as previous stage carries. This gain in speed of operation is achieved at
the expense of additional complexity (hardware).

SOURCE CODE:

module cla(cout,sum,a,b,c);

input [3:0]a,b,c;

output [3:0]sum,cout;
wire p0,p1,p2,p3,g0,g1,g2,g3;

wire c1,c2,c3,c4;

assign p0=a[0]^b[0];

assign p1=a[1]^b[1];

assign p2=a[2]^b[2];

assign p3=a[3]^b[3];

assign g0=a[0]&b[0];

assign g1=a[1]&b[1];

assign g2=a[2]&b[2];

assign g3=a[3]&b[3];

assign c1=g0|(p0&c);

assign c2=g1|(p1&g0)|(p1&p0&c);

assign c3=g3|(p2&g1)|(p2&p1&g0)|(p2&p1&p0&c);

assign c4=g3|(p3&g2)|(p3&p2&p1&g1)|(p3&p2&p1&g0)|(p3&p2&p1&p0&c);

assign sum[0]=p0^c;

assign sum[1]=p1^c1;

assign sum[2]=p2^c2;

assign sum[3]=p3^c3;

cout=c4;

endmodule

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