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CMOS Presentation

This document describes a model for predicting static delay variations in CMOS digital logic circuits due to electrical disturbances in the power supply. The model accounts for propagation delay through inverters and more complex logic gates. It was validated through simulation against a ring oscillator, 4-bit full adder, dynamic logic circuit, and transmission gates. Results showed maximum relative errors of 2.6% between predicted and simulated delays. The model provides a way to understand soft errors caused by timing changes within logic due to electrical disturbances.

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84 views20 pages

CMOS Presentation

This document describes a model for predicting static delay variations in CMOS digital logic circuits due to electrical disturbances in the power supply. The model accounts for propagation delay through inverters and more complex logic gates. It was validated through simulation against a ring oscillator, 4-bit full adder, dynamic logic circuit, and transmission gates. Results showed maximum relative errors of 2.6% between predicted and simulated delays. The model provides a way to understand soft errors caused by timing changes within logic due to electrical disturbances.

Uploaded by

delinquent_abhishek
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Department of Electronics Engineering

Shri Ramdeobaba College of Engineering and Management, Nagpur.

CMOS Assignment-II
Section : A
Roll No. :
(40,48)

Modeling Static Delay Variations in Push-Pull


CMOS digital logic circuits due to electrical
disturbances in power supply

Introduction ..

Electrical Fast
Transients

What is the use of this


model

Delay Model For Generic


Logic
Circuits
The
propogation
delay through
the cmos inverter is given by

where VT=Vth/Vdd,
Vdd is the power supply
voltage,
Vth is the threshold voltage,
is the velocity saturation
index for a MOSFET

tT is the rise or fall time of


the input signal,
ID0 is the drain current, and
CL is the load capacitance
driven by the gate

The propagation delay through


the inverter chain is given by:

Fig:- Chain of inverter

tpLH,tot,tpHL,tot

Vdd/(Vdd-Vth)^ * [S1.f(Vth,
)g(Vdd,Vth, ,D) + S2]
=

VALIDATION ON A
TEST IC
1. Predicting the Frequency(Period) of a
Ring Oscillator

Fig:- Ring Oscillator

The period of the output oscillation


can be calculated as,
T= tpLH,tot + tpHL,tot

2. Immunity Test Setup

Fig:- EFT Immunity test setup for the ring


oscillator

Fig:- Test results during a negative


600 V EFT

DELAY PREDICTION FOR GENERIC


LOGIC GATES
To verify that the delay model will work well with
more complex logic circuits, four different logic
circuits were tested through simulation.
A. NANDNOR Gate Logic Block Using 0.5 Micron
Technology
B. Four-Bit Full Adder Using 0.18 Micron Technology
C. Dynamic Logic Circuit Using 0.18 Micron Technology
D. Transmission Gates Using 0.18 Micron Technology

A. NANDNOR GATE LOGIC BLOCK USING 0.5 MICRON


TECHNOLOGY

NAND and NOR gates uses conventional CMOS


pushpull structures.
Gates with different drive strengths are used.

fig. Logic block with NAND and NOR gates

FIG. SIMULATED AND ESTIMATED DELAYS


THROUGH A LOGIC BLOCK CONTAINING NAND AND
NOR GATES. TOP: TPLH ; BOTTOM: TPHL .

B. FOUR-BIT FULL ADDER USING 0.18 MICRON


TECHNOLOGY

For a 1-bit full adder, if the two input digits A != B,


then Co = Ci , and in this case, the full adder is said
to be in the propagate mode.
For the 4-bit full adder, the two 4-bit digits A and B
were set to 1111 and 0000, respectively, so that
all 1-bit full adders were in propagate mode.
In this case, the carry out Cout = Cin .
The propagation delay from Cin to Cout was tested.
The predicted and simulated delays are shown in
Fig. The maximum relative errors were 0.5% and
0.3% for tpLH and tpHL, respectively.

FIG. SIMULATED AND ESTIMATED DELAYS


THROUGH THE 4-BIT FULL ADDER. TOP: TPLH ;
BOTTOM: TPHL .

C. DYNAMIC LOGIC CIRCUIT


USING 0.18 MICRON
TECHNOLOGY
For this dynamic logic circuit, Vout = Vin only when clk becomes logic high
and Vout remains at a logic low when clk is logic low. Therefore, the
propagation delay for the dynamic logic circuit was from clk to Vout .

FIG. SIMULATED AND ESTIMATED DELAYS THROUGH


THE DYNAMIC LOGIC CIRCUITS

D. TRANSMISSION GATES USING 0.18 MICRON


TECHNOLOGY
Ten transmission gates were connected in series and configured in
transmission mode .
The normal power supply voltage was 3.3 V.
The predicted and simulated delays are as shown in Fig.
The maximum relative errors were 2.6% and 2.5% for tpLH and tpHL,
respectively.

FIG. SIMULATED AND ESTIMATED DELAYS


THROUGH THE TRANSMISSION GATE CIRCUIT. TOP:
TPLH; BOTTOM: TPHL.

CONCLUSION
There are some limitations to the delay model.
Accuracy might get lower.
Power supply voltage is constant during the
logic transition of the output.

The proposed model can be


helpful
for
predicting
and
understanding the soft errors
caused by these timing changes
within the logic.

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