Delay estimation

Performance metrics of a chip:

 Speed
 Power
 Reliability
 Cost

The main issues to be considered are:

1. Delay estimation in CMOS gate
2. Power dissipation in CMOS logic
3. Interconnect delay and signal integrity
4. Design margining
5. Reliability
6. Effects of scaling

Delay estimation:
Critical paths: generally, the slowest paths in a logic design, can be recognized by timing simulations
using timing analyser.
The critical paths can be affected at four main levels:
• The architectural/microarchitectural level
• The logic level
• The circuit level
• The layout level
The critical paths can be affected at four main levels:
• The architectural/microarchitectural level
• The logic level
• The circuit level
• The layout level

Microarchitectural level: designer should know the algos of function implementation and the technology being
targeted, Viz., how many gate delays fit in a lock cycles, how fast processing occurs, how fast memories are
accessed, how long signal takes to propagate along a wire, etc.
Tradeoffs include: the no. of pipeline stages, no. of execution units and the size of memories.

Logic level: tradeoffs include types of functional blocks (eg. Ripple carry vs CLA adders), no. of stages in the gate
cycle, fan-in and fan-out of the gates.

Circuit level: delay can be tuned at this level by proper selection of transistor sizes or using other styles of CMOS
logic.

Layout level: The floorplan is of great importance because it determines the wire length that can dominate the delay.
Also, tuning of particular cells may reduce parasitic capacitance.
Some definitions

Commonly used delay models

 RC Delay model
 Elmore delay model
 Linear delay model
 RC delay model of MOS transistors (of k unit width)

The propagation delay of a logic gate can be estimated from RC delay model

RC delay model to find out

propagation Delay of an
inverter
For an ideal inverter, no parasitic diffusion capacitances
are present, hence the delay for such inverter would be
only 3RC.
Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise and fall
resistances equal to that of a unit inverter (R). Annotate the gate with its gate and diffusion
capacitances. Assume all diffusion nodes are connected. Then sketch the equivalent circuits for the
falling output transition and for the worst-case rising output transition.
 Elmore Delay model:

Elmore’s delay model estimates the delay of an RC ladder as shown in fig.

It is calculated as the sum over each node in the ladder of the resistance Rn-i between that node and the

source (Vin), multiplied by the capacitance on the node.

N N i
t pd  Rn  i Ci  Ci  R j
i 1 i 1 j 1

Here Rn-i represents the total resistance from the source to the node i.
Example: Find the Elmore’s delay at the nodes Vout3 and Vout4 in the RC tree.

Delay at Vout3 is:

tpd

Estimation of Elmore’s delay at Vout3 in the RC tree

 Estimation of Elmore’s delay at Vout4

Delay at Vout4 is:

tpd
 Linear delay model : Delay in a logic gate:
In general, the propagation delay of a gate is written as:
d=p+f
p= parasitic delay inherent to the gate when no load is
attached (set by internal parasitic capacitance)
f= effort delay or stage effort

Fan effort depends on the complexity and fan-out of the

gate
f=gh

g: Logical effort (gate complexity; measures the relative

ability of a gate to deliver current, g=1 for inverter)

h: Electrical effort (also called fan-out in case of

identical load), if load is not identical then h is computed
as Cout/Cin

Logical effort is also defined as “the slope of the gate’s delay vs. fanout curve divided by the
slope of an inverter’s delay vs. fanout curve”.
Introduction to logical effort
Chip designers face a bewildering array of choices–
What is the best circuit topology for a function?
How many stages of logic give least delay?
How wide should the transistors be?
Logical effort is a method to make these decisions
–Uses a simple model of delay
–Allows back-of-the-envelope calculations
–Helps make rapid comparisons between alternatives
–Emphasizes remarkable symmetries?

The logical effort of a logic gate is defined as how worse it is at delivering output current
than would be an inverter with identical input capacitance.
The logical effort of a logic gate is defined as the ratio of its input capacitance to that of an
inverter that delivers equal output current.
Calculating logical effort

Capacitance of reference inverter Cinv= 1+2=3

The input capacitance of single input at NAND gate (Load) Cout = Wpull-up+Wpull-dn = 2+2 = 4
Logical effort of NAND gate = Cout/ Cinv = 4/3 per input
Total logical effort of 2 input NAND gate = 2*4/3 = 8/3 (symmetric gate)

Similarly, for NOR gate,

Cout = 4+1 = 5
Logical effort of NOR gate = Cout/ Cinv = 5/3 per input
Total logical effort of 2 input NOR gate = 2*5/3 = 10/3 (symmetric gate)
Calculating logical effort

Logic gates sized for unit resistance

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
 Calculating logical effort

Asymmetric AOI gate

Logical effort is calculated in the same way

Inputs a and b each has logical effort = 6/3=2

whereas c has 5/3
Total logical effort = 17/3

Input c is reflecting less capacitive load than the other two

inputs, hence it is easier to drive c as compared to a and b.

Asymmetries are also used in NAND and NOR gates by

taking different transistor sizes to reduce the logical effort
on some inputs and hence the load.

The logical effort of a logic function depends mainly on the circuit topology and slightly on the electrical
properties of the fabrication process used to build it.
Logical effort of individual stages of logic can be combined to find the logical effort of networks.

The Electrical effort h describes how the electrical environment of the logic gate affects performance and
how the size of the transistors in the gate determines its load driving capability.
Calculations of logical effort of some of the gates and digital circuits

γ = width of pull-up transistor

(pmos) of an inverter whereas
pull-down transistor(nmos) has
unity width.
Calculating Parasitic delay (p)
 Is the delay of a gate when it drives zero load and it can be estimated with RC delay models.
 The major contribution to the parasitic capacitance is from the diffused region capacitance connected
to the output signal. In other words, p is set by internal parasitic capacitance.
 These diffused capacitances depends on their layout geometry and on process parameters.

For a crude approximation, let’s take a transistor of width w has diffusion capacitance equal to wCd.
The parasitic capacitance of an inverter is thus calculated as
For pull-up transistor (of width γ) , the diffusion capacitance = γCd

Pull-down transistor of width w has diffusion capacitance = Cd

τ=3RC
The input (gate) capacitance of inverter = (1+ γ) Cg

The parasitic delay of inverter pinv= parasitic capacitance/ input capacitance = Cd /Cg= 1.0 (approx)

 w  d

The parasitic pcapacitance
 1  
of logic
p gates can be estimated from the inverter parameters as follows:
inv
 
where w : width of transistors connected to the logic gate’s output
Parasitic delay (p) of various logic gates and digital circuits

This inverter approximation can be applied to an n-input NAND/NOR gate whose pull-down
transistor has width w and pull-up transistor has width γ, connected to the output signal.
Hence, p = npinv

Increasing transistor sizes reduces resistance but increases capacitance correspondingly, so parasitic
delay is, on first order, independent of gate size

This method gives crude estimation, more refined results can be found using Elmore’s delay model.
Example of applying linear delay model to logic gates
Example of applying linear delay model to logic gates

Use the linear delay model to estimate the frequency of an N-stage ring oscillator (RO)
constructed in a 65-nm process with τ= 3 ps.

For an inverter,
Logical Effort: g = 1
Electrical Effort: h = 1
Parasitic Delay: p = 1
Thus the delay of each stage : d = gh+p = 2
An N-stage RO has a period of 2N stage delays, therefore the period T = 2*2N
Frequency of N-stage : fosc = 1/(4N)

A 31 stage ring oscillator in 65 nm process has a frequency of

1/(4*31*3 ps) = 2.7 GHz.
Example of applying linear delay model to logic gates
A particular technology node has a FO4 delay of 9 ps. How many minimum size (2:1)
inverters need to be included in a ring oscillator so that the frequency is close to 7.3 GHz?

FO4 delay = 15RC = 9ps

Stage delay = 6RC = 3.6ps

f = 1/(2*N*d )
N = 1/(2*f*d)

τ=3RC

FO4 delay d = (gh+p)RC

= (1*4+1)RC
= 5*3RC

Stage delay = 2*3RC = 6RC

Delay in Multistage Logic Networks
Logical effort generalizes to multistage networks

• Path Logical Effort, (product of logical efforts of each stage along the path)

• Path Electrical Effort

• Path Effort

Can we write F = GH in general?

No, in paths that branch F

Delay in Multistage Logic Networks

• Path Logical Effort,

• Path Electrical Effort

• Path Effort

Can we write F = GH in general?

No, in paths that branch F

Consider a path from primary input to one of the outputs

G=1
H = 90 / 5 = 18
GH = 18
But F =f1f2 = g1h1g2h2
h1 = (15 +15)/5 = 6
h2 = 90/15 = 6
F = g1h1g2h2 = 36 = 2*GH

In other words, F=2GH in this path on account of two-way branch.

Delay in Multistage Logic Networks
We must introduce a new kind of effort to account for branching between stages of a path.

The branching effort (i.e., the total capacitance seen by a stage to the capacitance on the path)

From fig., it is (15+15)/15 = 2

Path Branching Effort

Now, we can define the path effort F as the product of logical, electrical and branching efforts of the
path. F = GBH

Thus, the delay of a Multistage network can be computed as

Path Delay; D = = DF + P

Path effort delay; DF =

Path parasitic delay; P =

Delay in Multistage Logic Networks
Designing Fast Circuits

Path Delay; D = = DF + P

Delay is smallest when each stage bears same effort

ˆf g h F N1
i i

Thus, the minimum delay of an N-stage path is

1
D NF  P N

This is a key result of logical effort

 Find fastest possible delay
 Doesn’t require calculating gate sizes
Delay in Multistage Logic Networks 1
D NF  P N

Designing Fast Circuits

Example 1: Consider the path from to involving three two-input NAND gates shown in Figure. The input
capacitance of the first gate is C and the load capacitance is also C. What is the least delay of this path
and how should the transistors be sized to achieve least delay?

To compute the path effort, we must compute the logical, branching, and electrical efforts along the path.
The path logical effort is the product of the logical efforts of the three NAND gates, G = g0g1g2
= (4/3)3 = 2.37.
The branching effort is B = 1, because all of the fanouts along the path are one, i.e., there is no
branching.
The electrical effort is H = C/C = 1. Hence, the path effort is F = GBH = 2.36
1

Now, we find the least delay achievable along the path to b D  NF  P = 3(2.37)1/3 + 3 (2pinv)
N

delay units
Delay in Multistage Logic Networks 1
D  NF N  P
Designing Fast Circuits
Example 1: Consider the path from A to B involving three
two-input NAND gates shown in Figure. The input capacitance
of the first gate is C and the load capacitance is also C. What
is the least delay of this path and how should the transistors
be sized to achieve least delay?

To compute the path effort, we must compute the logical, branching, and electrical efforts along the path.
The path logical effort is the product of the logical efforts of the three NAND gates, G = g0g1g2
= (4/3)3 = 2.37.
The branching effort is B = 1, because all of the fanouts along the path are one, i.e., there is no branching.
The electrical effort is H = C/C = 1. Hence, the path effort is F = GBH = 2.36
1
Now, we find the least delay achievable along the path to be D  NF N  P = 3(2.37)1/3 + 3 (2pinv)
delay units.

This minimum delay can be realized if the transistor sizes in each logic gate are chosen properly

First compute the stage effort f = (2.37)1/3 = 4/3.

Starting with the output load C, apply the capacitance transformation to compute input capacitance
z = C* (4/3)/(4/3) = C. Similarly, y = C* (4/3)/(4/3) = C. Hence we find that all three NAND gates should have
the same input capacitance, C. In other words, the transistor sizes in the three gates will be the same.
Delay in Multistage Logic Networks
1
D  NF  PN

Designing Fast Circuits

Example 2: Using the same network as in the

previous example, find the least delay
achievable along the path from to when the
8C
output capacitance is 8C.

From previous example G = g0g1g2 = (4/3)3, electrical effort H = 8C/C = 8,

we compute F = GBH = (4/3)3 * 8 = 18.96,
so the least path delay is D = 3(18.96)1/3 + 3 (2pinv) = 14.0 delay units.
Observe that although the electrical effort in this example is eight times the electrical effort in the
earlier example, the delay is increased by only 40%.
Now let us compute the transistor sizes that achieve minimum delay. The stage effort f = (18.96)1/3 = 8/3
Starting with the output load 8C, apply the capacitance transformation to compute input capacitance z =
8C* (4/3)/(8/3) = 4C. Similarly, y = z* (4/3)/(8/3) = 2C.
To verify the calculation, calculate the capacitance of the first gate y * (4/3)/(8/3) = y/2 = C, matching
the design specification.
Each successive logic gate has twice the input capacitance of its predecessor.
This is achieved by making the transistors in a gate twice as wide as the corresponding transistors in its
predecessor. The wider transistors in successive stages are better able to drive current into the larger
loads.
Delay in Multistage Logic Networks D  NF  P
1
N

Designing Fast Circuits

Example 3: Optimize the circuit in Figure to

obtain the least delay along the path from A to
B when the electrical effort is 4.5.

The path logical effortG = g0g1g2 = (4/3)3, The branching effort at

the output of the first stage is (y+y)/y = 2, and at the output of 2nd stage it is (z+z+z)/z = 3.
The path branching effort B = 2*3 = 6. The electrical effort H = 4.5 from the circuit.
we compute F = GBH = 64 and so the least path delay is D = 3(64)1/3 + 3 (2pinv) = 18.0 delay units.

To achieve this minimum delay, we must equalize the effort in each stage.
Since the path effort is 64, the stage effort should be (64)1/3 = 4.
Starting from the output, z = 5.4C*(4/3)/4 = 1.5
The second stage drives three copies of the third stage, so y= 3z*(4/3)/4 = z = 1.5C
We can check the math by finding the size of the first stage 2y*(4/3)/4 = (2/3)y = C, as given in the
design
Delay in Multistage Logic Networks 1
D  NF  P
N

Designing Fast Circuits

Example 4: Size the circuit as shown in figure below for minimum delay.
Suppose the load is 20 microns of gate capacitance and that the inverter has 10
microns of gate capacitance as shown.

The path logical effort is G = 1*(5/3)*(4/3)*1 = 20/9.

The electrical effort along the path is H = 10/10 = 2,
The path branching effort is B = 1
Thus F = GBH = (20/9)(2)(1) = 40/9 and f = (40/9)1/4 = 1.45 and D = 3(64)1/3 + 3(2pinv) = 18.0 delay units.
Starting from the output, z = 20*(1)/1.45 = 14, y = 14*(4/3)/1.45 = 13 and x = 13*(5/3)/1.45 = 15
These input gate widths are divided among the transistors in each gate.
Notice that the inverters are assigned larger electrical efforts than the more complex gates because they
are better at driving loads.
Note that the parasitic delay does not enter into the procedure for calculating transistor sizes
to obtain minimum delay. Because the parasitic delay is fixed, independent of the size of the logic gate,
adjustments to the size of logic gates cannot alter parasitic delay. In fact, we can ignore parasitic delay
entirely unless we want to obtain an accurate estimate of the time required for a signal to propagate
through a logic network, or if we are comparing two logic networks that contain different types of logic
gates or different numbers of stages and therefore exhibit different parasitic delays.
Delay in Multistage Logic Networks 1
D NF  P N

Designing Fast Circuits

Example 5: Consider three alternative circuits for driving a load 25 times the
input capacitance of the circuit. The first design uses one inverter, the
second uses three inverters in series, and the third uses five in series. All
three designs compute the same logic function. Which is best, and what is
the minimum delay?
In all three cases, the path logical effort is one, the branching effort is one, and the electrical effort is 25.
the path delay D = N(25)1/N +Npinv where N = 1, 3, or 5.
For N =1, D = 26 delay units
For N = 3, D = 11.8 and for N = 5,
D = 14.5 delay units

The best choice is N =3. In this design, each stage will bear an effort of (25)1/3 = 2.9,
so each inverter will be 2.9 times larger than its predecessor.
Delay in Multistage Logic Networks 1
D NF  P N

Designing Fast Circuits

Example 5: A string of inverters is used to drive a signal that goes off-chip

through a pad. The capacitance of the pad and its load is 35 pF, which is
equivalent to about 20,000 microns of gate capacitance. Assuming the
load on the input should be a unit-sized inverter in a 0.6 micron process
with 7.2 microns of input capacitance, how should the inverter string be
designed?
In all three cases, the path logical effort is one, the branching effort is one, and the electrical effort is 25.
the path delay D = N(25)1/N +Npinv where N = 1, 3, or 5.
For N =1, D = 26 delay units
For N = 3, D = 11.8 and for N = 5, D = 14.5 delay units

From the previous example, the logical and branching efforts are both 1, but the electrical effort is
20000/7.2 = 2777.
IF N= 6, the stage effort will be f = (2777)1/6 = 3.75
Thus the input capacitance of each inverter in the string will be 3.75 times that of its predecessor.
The path delay will be D = 6*3.75 + 6 *pinv = 28.5 delay units.
This corresponds to an absolute delay of 28.5τ = 1.43 ns, assuming τ = 50 ps.