DSP C5000

Chapter 2
Architecture Overview

Copyright © 2003 Texas Instruments. All rights reserved.

 Objectives

 Describe and compare the basic CPU

architecture of the C54x and the C55x
 Discuss pipeline phases
 List the key features of the C54x and C55x
memory map and peripherals
 Give a detailed presentation of CPU
registers

ESIEE, Slide 2 2
Copyright © 2003 Texas Instruments. All rights reserved.
 What Makes a DSP a Special Processor?

C5000
ESIEE, Slide 3 Copyright © 2003 Texas Instruments. All rights reserved.
 Common Architectural Features of DSPs

Data crunching:

MAC- multiply/ accumulate Unit

Executes one or more MAC in one clock cycle
Internal registers for storing operands and results
Multiple internal data memories
Auxilary adressing registers (8 or more) with
a dedicated ALU
Multiple buses and dual access to data memory
Separate access to program and data memories
(Harvard architecture)
DMA (Direct Memory Access)

ESIEE, Slide 4 Copyright © 2003 Texas Instruments. All rights reserved.

 Common Architectural Features of DSPs

Real-time and Multi-tasking:

Hardware and software interrupt handling
Zero overhead loops
Pipelined instructions
Parallel units
Specialised peripherals

Complex Algorithms:
Specialised instructions (Viterbi, LMS…)
Bit reverse adressing (FFT)
Circular buffers (FIR filters)

ESIEE, Slide 5 Copyright © 2003 Texas Instruments. All rights reserved.

 General DSP System Block Diagram

ESIEE, Slide 6 Copyright © 2003 Texas Instruments. All rights reserved.

 What Constitutes a Good DSP?

ESIEE, Slide 7 Copyright © 2003 Texas Instruments. All rights reserved.

 DSP Requires Multiply and Accumulate

ESIEE, Slide 8 Copyright © 2003 Texas Instruments. All rights reserved.

 Multiply and Accumulate Unit

ESIEE, Slide 9 Copyright © 2003 Texas Instruments. All rights reserved.

 Multiple Buses

ESIEE, Slide 10 Copyright © 2003 Texas Instruments. All rights reserved.

 Internal Memory for Fast Access

ESIEE, Slide 11 Copyright © 2003 Texas Instruments. All rights reserved.

 Instruction Pipeline for Fast Execution
Instruction is broken into smaller tasks
that can be executed in parallel

ESIEE, Slide 12 Copyright © 2003 Texas Instruments. All rights reserved.

 Sequential Processing of Instructions

ESIEE, Slide 13 Copyright © 2003 Texas Instruments. All rights reserved.

 Less Cycles per Instruction
Less Power Consumption

ESIEE, Slide 14 Copyright © 2003 Texas Instruments. All rights reserved.

 Texas Instruments
C5000 Solutions

ESIEE, Slide 15 Copyright © 2003 Texas Instruments. All rights reserved.

 Basic Harvard Architecture
1st DSP Generation

ESIEE, Slide 16 Copyright © 2003 Texas Instruments. All rights reserved.

 TMS320C54X DSP Generation Block
Diagram

Conventional Harvard DSP architecture

Program
Bus Data Bus

ESIEE, Slide 17 Copyright © 2003 Texas Instruments. All rights reserved.

 TMS320C54X Key Features
CPU
Advanced multibus architecture with:
 one program bus, three data buses, and four address buses
 40-bit arithmetic logic unit (ALU), including
a 40-bit barrel shifter and two 40-bit accumulators
 17-bit × 17-bit parallel multiplier coupled to a
40-bit dedicated adder non-pipelined single-cycle
multiply/accumulate (MAC) operation
 Compare, select, store unit (CSSU) for the Viterbi
operator implementation
Two address generators, including eight auxiliary registers
(ARn) and two auxiliary register arithmetic units (ARu)

ESIEE, Slide 18 Copyright © 2003 Texas Instruments. All rights reserved.

 C54X Memory Blocks

Memory
 192K words × 16-bit addressable memory
space in 3 blocks:
1) 64K-words program**
2) 64K-words data,
3) 64K-words I/O

**extended program memory depending on the C54X version.

ESIEE, Slide 19 Copyright © 2003 Texas Instruments. All rights reserved.

 TMS320C55X DSP Block Diagram

3 Data Read
Buses

1 Program
Bus

2 Data Write
Bus
ESIEE, Slide 20 Copyright © 2003 Texas Instruments. All rights reserved.
 TMS320C55x Key Features
 32 x 16-bit Instruction buffer queue (IBQ)
 Two 17-bit x17-bit MAC units
 One 40-bit ALU
 One 40-bit Barrel Shifter
 One 16-bit ALU
 Four 40-bit accumulators
 Twelve independent buses:
– Three data read buses
– Two data write buses
– Five data address buses
– One program read bus
– One program address bus

ESIEE, Slide 21 Copyright © 2003 Texas Instruments. All rights reserved.

 More C55x Features
 User-configurable IDLE Domains
 Variable length instructions and
efficient block repeat operations
 Dual MAC operations in a single
cycle
 Performs high precision arithmetic
and logical operations
 Shift a 40-bit result up to 31 bits to
the left,or 32 bits to the right
 Performs arithmetic in a simpler ALU
of 16 bits.
 Hold results of computations and
reduce the required memory traffic
(4 Accumulators)
ESIEE, Slide 22 Copyright © 2003 Texas Instruments. All rights reserved.
 Comparison Between C54x and C55x
C54x C55x
MACs 1 2
Accumulators 2 4
Read buses 2 3
Write buses 1 2
Program fetch 1 1
Address buses 4 6
Program word size 16 bits 8/16/24/32/40/48 bits
Data word size 16 bits 16 bits
Auxiliary Register ALUs 2 (16-bit each) 3 (24-bit each)
ALU 1 (40-bit) 1 (40-bit)/1 (16-bit)
Auxiliary Registers 8 8
Data Registers 0 4
Memory separate data/prog Unified space

ESIEE, Slide 23 Copyright © 2003 Texas Instruments. All rights reserved.

 Performances Features Comparison Between
C54x and C55x
30 to 160 Million Instructions per Second (MIPS) and MACs
for the C54x compared to 140 to 800 MIPS for the C55x
(5 times better)

Core Power consumption improves by 6 from 0.32 mW/ MIPS

for the C54x to 0.05 for the C55x.

Variable instruction length (8 to 48 bits) for the C55x and 16 bits

for the C54x gives a better code density.

C55x has twice as many Macs (2 and 1), Accumulators (4 and

2), program fetch words (32 and 16 bits)

ESIEE, Slide 24 Copyright © 2003 Texas Instruments. All rights reserved.

 Same family but big differences!

Short overview of the C54x and C55x

ESIEE, Slide 25 Copyright © 2003 Texas Instruments. All rights reserved.

 Convolution with the C54x 1 of 2
Amplitude

Data Read Buses

MAC ALU
Time
x4 x3 x2 x1 x0
A
B
3
y 0 =  a nx n z = x2 + x4 + x3 + x1  Single-cycle MAC
n=0  Single-cycle ADD

MAC *AR2+, *AR3+, A ADD @x2, B ...

ESIEE, Slide 26 3
Copyright © 2003 Texas Instruments. All rights reserved.
 Convolution with the C54x 2 of 2
Amplitude

Data Read Buses

MAC ALU
Time
x4 x3 x2 x1 x0
A
B
3
y 0 =  a nx n z = x2 + x4 + x3 + x1  Single-cycle MAC
n=0  Single-cycle ADD

MAC *AR2+, *AR3+, A ADD @x2, B ...

ESIEE, Slide 27 3
Copyright © 2003 Texas Instruments. All rights reserved.
 With the C55x it can be done faster!
Amplitude Data Coeffs
a0
 2 taps/cycle
a1
Data Read Buses
a2
a3
Time
x4 x3 x2 x1 x0 MAC
t
MAC

Results
y0 = a0x0 + a1x1 + a2x2 + a3x3 AC0
A
AC1
y1 = a0x1 + a1x2 + a2x3 + a3x4

C55x: MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1

C54x: MAC *AR2+, *AR3+, A Copyright © 2003 Texas Instruments. All rights reserved. - 28
ESIEE, Slide 28 Copyright © 2003 Texas Instruments. All rights reserved.
 C54x Architecture
Data Read A/D Bus (C)
Program A/D Bus (P)
Data Read A/D Bus (D)
PC
XPC MAC ALU
Addr
DP @x2 AR0-7
Gen
Decode A
B

Data Write A/D Bus (E)

MAC *AR2+, *AR3+, A ADD @x2, B ...

ESIEE, Slide 29 4
Copyright © 2003 Texas Instruments. All rights reserved.
 C55x Architecture
Program A/D Bus

Data Read Buses (D, B, C)

Instr A
Buffer PC ARn d CDP MAC MAC
d
Queue r
Gen
AC0
AC1
Decode

Data Write Buses (E, F)

IU PU AU DU

MAC *AR2+, *CDP+, AC0 :: MAC *AR3+, *CDP+, AC1

ESIEE, Slide 30 Copyright © 2003 Texas Instruments. All rights reserved.
 C55x Program and Instruction Units
00_0000 PAB[24] PC

Internal PDB[32] RETA

Prog Addr Gen
IU
Instruction Status Registers
External Buffer Program Flow
64 x 8
PPU
48 Interrupts
FF_FFFF
PU
 4-byte packet fetched Decoder
every cycle
 Variable-length instruction set Now, the A-unit...
(8, 16, 24, 32, 40, 48-bit)
PU AU DU
ESIEE, Slide 31 Copyright © 2003 Texas Instruments. All rights reserved.
 C55x Addressing Unit (AU)
ARAU
00_0000 BAB[24]
First 64KW Pg 0 A X AR0-7
d
CAB[24] d
r X CDP
DAB[24] G
e X DP
n
23/16-bit

CB[16] ALU/Shft Stack

Last 64KW Pg 127 Pointers
FF_FFFF
T0
DB[16] Circular
T1 Buffers
T2 23/16-bit
 A-Unit handles all data addressing
T3
 Xreg: 23 bits, reg: 16 bits 16-bit
AU
 Where else could the data go?...
ESIEE, Slide 32 Copyright © 2003 Texas Instruments. All rights reserved.
 C55x Data Computation Unit (DU)
00_0000
MAC MAC
Internal AC0
40-bit
BB[16] AC1 ALU
AC2
CB[16] Shift
AC3
40-bit
External DB[16]
Viterbi Hardware
FF_FFFF Transition Regs

Bit Operations
 D-Unit executes most
mathematical operations DU
 Now, what happens to the result?...

ESIEE, Slide 33 Copyright © 2003 Texas Instruments. All rights reserved.

 C55x Writes (E and F buses)
00_0000
EAB[24] AU
Internal
FAB[24]

DU
EB[16]
External AC0
FB[16] AC1
AC2
FF_FFFF
AC3

 32-bit write in one cycle

ESIEE, Slide 34 Copyright © 2003 Texas Instruments. All rights reserved.

 C54x Block Diagram • 17x17 MAC Unit
• Saturation and
Rounding
Program/Data ROM Program/Data SRAM Hardware
16K Words JTAG Test/
128K Words
Emulation • Two 40-bit ACC’s
D(15-0) Control

Program/Data Buses
• 40-bit ALU
A(23-0) Muxed GP I/O • 40-bit Barrel
Shifter
MAC ALU DMA Timer
17 x 17 MPY 40-Bit ALU Ch 0 • Temporary Register
CMPS Operator 8/16-bit Host Port
40-Bit Adder
• Exponent Encoder

Peripheral Bus
(VITERBI) Ch 1 Interface (HPI)
RND, SAT EXP Encoder Ch 2 Multichannel Buffered
Shifter Accumulators
Serial Port (McBSP) • Program and Data
Ch 3
40-Bit Barrel 40-Bit ACC A Multichannel Buffered Address Generation
Ch 4 Serial Port (McBSP)
Units
(-16, 31) 40-Bit ACC B
Ch 5 Multichannel Buffered
Addressing Unit Serial Port (McBSP) • Compare, Select
8 Auxiliary Registers
PLL Clock and Store Unit
2 Addressing Units Generator
S/W Waitstate
• 4 Internal Bus Pairs
Power Management Generator
• External Interface

C5416 example
5
ESIEE, Slide 35 Copyright © 2003 Texas Instruments. All rights reserved.
 Focus on C54x Architecture

ESIEE, Slide 36 Copyright © 2003 Texas Instruments. All rights reserved.

 C54x Block Diagram • 17x17 MAC Unit
• Saturation and
Rounding
Program/Data ROM Program/Data SRAM Hardware
16K Words JTAG Test/
128K Words
Emulation • Two 40-bit ACC’s
D(15-0) Control

Program/Data Buses
• 40-bit ALU
A(23-0) Muxed GP I/O • 40-bit Barrel
Shifter
MAC ALU DMA Timer
17 x 17 MPY 40-Bit ALU Ch 0 • Temporary Register
CMPS Operator 8/16-bit Host Port
40-Bit Adder
• Exponent Encoder

Peripheral Bus
(VITERBI) Ch 1 Interface (HPI)
RND, SAT EXP Encoder Ch 2 Multichannel Buffered
Shifter Accumulators
Serial Port (McBSP) • Program and Data
Ch 3
40-Bit Barrel 40-Bit ACC A Multichannel Buffered Address Generation
Ch 4 Serial Port (McBSP)
Units
(-16, 31) 40-Bit ACC B
Ch 5 Multichannel Buffered
Addressing Unit Serial Port (McBSP) • Compare, Select
8 Auxiliary Registers
PLL Clock and Store Unit
2 Addressing Units Generator
S/W Waitstate
• 4 Internal Bus Pairs
Power Management Generator
• External Interface

C5416 example
ESIEE, Slide 37 Copyright © 2003 Texas Instruments. All rights reserved.
 C54x Pipeline
Program A/D Bus (P)

Internal Data Read A/D Bus (D) Ext’l A

External
Mem
Memory Data Read A/D Bus (C) I/F D Memory
Data Write A/D Bus (E)

 Internal: Up to 4 accesses / cycle  External: 1 access / cycle

 up to 8M words program
Pipeline Phases
P - generate program address P F D A R X
F - get opcode P F D A R X
D - decode instruction P F D A R X
A - generate read address P F D A R X
R - read operands P F D A R X
X - execute
P F D A R X

ESIEE, Slide 38 Full Pipeline 6

Copyright © 2003 Texas Instruments. All rights reserved.
 C54x Memory and Buses

Program A/D Bus (P)

Internal Data Read A/D Bus (D) Ext’l A

External
Mem
Memory Data Read A/D Bus (C) I/F D Memory
Data Write A/D Bus (E)

 Internal: Up to 4 accesses / cycle  External: 1 access / cycle

 up to 8M words program

ESIEE, Slide 39 Copyright © 2003 Texas Instruments. All rights reserved.

 C54 Pipeline Phases

Pipeline Phases
P - generate program address P F D A R X
F - get opcode P F D A R X
D - decode instruction P F D A R X
A - generate read address P F D A R X
R - read operands P F D A R X
X - execute
P F D A R X
Full Pipeline

ESIEE, Slide 40 Copyright © 2003 Texas Instruments. All rights reserved.

 C54x Pipeline Bus/Hardware Use
P Generate Program address PA PC
F Get opcode PD Program mem
D Decode instruction Decoder
A Generate Read address DA/CA ARs, ARAU
R Read operands DD/CD Data mem
Generate Write address EA ARs, ARAU
X Execute instruction MAC, ALU
Write result ED Data mem

 When storing results back to memory, the

“write” is broken into two phases:
- generating the write address
- writing the result
 Overlaid onto R & X phases
ESIEE, Slide 41 7
Copyright © 2003 Texas Instruments. All rights reserved.
 Pipeline Implications 1 of 3
What if all data and P
program are external? 54x
D
P1 F1 D1 A1 R1 X1
P2 F2 D2 A2 R2 X2
P3 F3 D3 A3 R3 X3
P4 -- -- -- F4 D4 A4 R4 X4
-- -- -- P5 F5 D5 A5 R5 X5
-- -- -- P6 F6 D6 A6 R6

 External read conflicts with external fetch

 Can reduce performance by at least 50%
How would you avoid this situation?
ESIEE, Slide 42 8
Copyright © 2003 Texas Instruments. All rights reserved.
 Pipeline Implications 2 of 3
When either
Program or Data 54x 54x
is located internally... P or D
D P
…fetch and read can
occur simultaneously

P1 F1 D1 A1 R1 X1
P2 F2 D2 A2 R2 X2
P3 F3 D3 A3 R3 X3
P4 F4 D4 A4 R4 X4
P5 F5 D5 A5 R5 X5
P6 F6 D6 A6 R6 X6

What if both program and data are located internally?

ESIEE, Slide 43 9
Copyright © 2003 Texas Instruments. All rights reserved.
 Pipeline Implications 3 of 3
Program Data
SARAM DARAM
ROM ROM

P Bus
A
D Bus Ext’l
Mem
C Bus I/F D

E Bus

There are no conflicts as long as you follow these rules:

 ROM/SARAM - 1 access per block per cycle
 DARAM - 2 accesses per block per cycle

Size and number of blocks vary based upon device - refer to memory map
ESIEE, Slide 44 10
Copyright © 2003 Texas Instruments. All rights reserved.
 C5409 Memory Maps
PROGRAM
PAGE 0 (64K) DATA
0000 0000

DARAM or MMR,
External OVLY Scratch, 64K x 16
8M x 16 memory bit DARAM Data
Program Space
Space
7FFF 7FFF 32K x 16
16K x 16 Internal
Internal External External DARAM
ROM memory memory
C000 Internal or C000
External
External memory
memory DROM
bit or Internal
FF80 VECTORS ROM
FFFF FFFF

OVLY Maps most of on-chip DARAM into Program space

DROM Maps most of on-chip Program ROM into Data space
ESIEE, Slide 45 11
Copyright © 2003 Texas Instruments. All rights reserved.
 C5409 Program Memory Options (Page 0)
All External Internal/External 'RAM' Option
MP/MC = 1 MP/MC = 0 OVLY = 1
0000 0000 0000
0080

DARAM

External External
memory memory 7FFF

External
memory
C000 C000
Internal External
16K x 16 memory or
ROM Internal ROM
FF80 Vectors FF80 Vectors FF80 Vectors
FFFF FFFF FFFF

ESIEE, Slide 46 12
Copyright © 2003 Texas Instruments. All rights reserved.
 C5409 8M x 16 Program Space
 The OVLY bit selects between two different program memory maps:

OVLY = 0 OVLY = 1
00 0000 00 0000 32K
Page 0 DARAM

64K words Upper 32K

Page 0
00 FFFF 00 FFFF External Mem SAME
. .
. .
. .
7F 0000 7F 0000 32K
Page 127 DARAM

64K words Upper 32K

Page 127
7F FFFF 7F FFFF External Mem

ESIEE, Slide 47 13
Copyright © 2003 Texas Instruments. All rights reserved.
 C5409 Data Memory

0000 0000 0000

DARAM MMR
Block a
32K x 16 0060 Scratch
DARAM 2000 0080
DARAM
Block b
8000 4000
DARAM
DARAM Block a
Block c
External
memory 6000
F000 External DARAM
memory or Block d
ROM
FFFF 7FFF 1FFF

ESIEE, Slide 48 14
Copyright © 2003 Texas Instruments. All rights reserved.
 C5409 Peripheral Overview
54x C5409
core

McBSP 3 Multi-Channel BSPs: Each offers up to 128-channel rcv/xmt

DMA 6-channels: facilitates data/program transfers w/o CPU intervention
HPI Host Port Interface: 8-bit interface to host processor
Boot Boot Loader: Multiple ways to load program to volatile memory
Timers One 20-bit timer: Can generate timer-based interrupts
GPIO General Purpose I/O: External lines dedicated to I/O
PLL Phase Locked Loop: software programmable
Power Down Idle Modes: Power saving modes and features

ESIEE, Slide 49 15
Copyright © 2003 Texas Instruments. All rights reserved.
 C54x Review - Answers
 Name the buses on the C54x
PA,PD CA,CD DA,DD EA,ED
 How large are the accumulators?
40 bits
 How many adders are on the part?
2, one in the MAC and the other in the ALU
 Where are the Memory Mapped Registers located?
From 0x00 to 0x5F in Data Memory
 Where is the Reset Vector located?
0xFF80 in Program Memory

ESIEE, Slide 51 17
Copyright © 2003 Texas Instruments. All rights reserved.
 Focus on C55x Architecture

ESIEE, Slide 52 Copyright © 2003 Texas Instruments. All rights reserved.

 Functional Diagram of C5510 1 of 2

ESIEE, Slide 53 Copyright © 2003 Texas Instruments. All rights reserved.

 Functional Diagram of C5510 2 of 2

ESIEE, Slide 54 Copyright © 2003 Texas Instruments. All rights reserved.

 Pipelines of the C55x
There are 2 independent pipelines:
Program fetch pipeline (3 clock cycles)
Program execution pipeline (7 clock cycles)

 Pipeline execution breaks an operation into smaller

pieces that can be executed independently.
 The fetch pipeline is done inside the Instruction
Buffer Unit and fills IBQ
 The execute pipeline fetches instructions from IBQ
and executes them

ESIEE, Slide 55 Copyright © 2003 Texas Instruments. All rights reserved.

 C55x Fetch Packet Pipeline

PF1 - gen prog address PF1 PF2 F IBQ

PF2 - memory wait PF1 PF2 F
4 bytes 64x8
F - fetch 4-byte packet PF1 PF2 F

 Fetch-packet pipeline fetches 4-byte packets from program

memory INTO the IBQ every cycle (unless IBQ is full)
 Fetch packet pipeline operates independently from execute pipeline

Program Bus
E Data Read Buses (B,C,D)
A M
I PU IU AU DU
F
D
Data Write Buses (E,F)

ESIEE, Slide 56 Copyright © 2003 Texas Instruments. All rights reserved.

 C55x Execute Pipeline
D AD AC1AC2 R X W
D - decode opcode D AD AC1AC2 R X W
AD - compute address
D AD AC1AC2 R X W
AC1 - gen read address
AC2 - memory wait IBQ D AD AC1AC2 R X W
R - read operands 64x8 1-6 D AD AC1AC2 R X W
bytes
X - execute D AD AC1AC2 R X W
W - write to memory D AD AC1AC2 R X W

 Execute pipeline fetches instructions

FROM the IBQ, then executes them
 IU performs fetch/decode from IBQ
E Data Read Buses (B,C,D)
A M  AU generates operand addresses
I IU AU DU
F  AU/DU execute instructions
D  X: result to register
Data Write Buses (E,F) W: result to memory

ESIEE, Slide 57 Copyright © 2003 Texas Instruments. All rights reserved.

 Execute Pipeline Phases 1 of 2
D
Read six bytes from the instruction buffer queue.
Decode an instruction pair or a single instruction.
Dispatch instructions to the appropriate CPU functional units.
Read STx_55 bits associated with data address generation:
ST1_55(CPL), ST2_55(ARnLC), ST2_55(ARMS), ST2_55(CDPLC)
AD
Read/modify registers involved in data address generation.
Perform operations that use the A-unit ALU.
Decrement ARx for the conditional branch instruction
Evaluate the condition of the XCC instruction
AC1
Memory read operations, send addresses on the appropriate CPU
address buses.

ESIEE, Slide 58 Copyright © 2003 Texas Instruments. All rights reserved.

 Execute Pipeline Phases 2 of 2
AC2
Allows one cycle for memories to respond to read requests.

R
Read data from memory, I/O space, and MMR-addressed registers.
Read A-unit registers
Evaluate the conditions of conditional instructions.

X
Read/modify registers that are not MMR-addressed.
Read/modify individual register bits.
Set conditions.
Evaluate the condition of the RPTCC instruction.

W
Write data to MMR-addressed registers or to I/O space (peripheral
registers).
Write data to memory.
ESIEE, Slide 59 Copyright © 2003 Texas Instruments. All rights reserved.
 C5510 Unified Memory Map
Program Data  Program and data share
00_0000 00_0000 the same map
MMRs
00_00C0 DARAM (32KW) 00_0060  2 ways to view the map:
Internal
01_0000 00_8000 23 0
SARAM (128KW) Prog
05_0000 02_8000 23 1 0
Data 0
External 1. Program - (Bytes)
- 16M x 8-bit, linear 24-bit
addresses
FF_FFFF 7F_FFFF
- Used by fetch/decode logic
A(24)

D(32)

2. Data (Words)
- 8M x 16-bit, segmented into
64K pages, 23-bit address
C55xx - Most code written by a user
core will access data
ESIEE, Slide 60 Copyright © 2003 Texas Instruments. All rights reserved.
 Memory Access
 16M bytes of memory are addressable as
program space or data space
 When the CPU uses program space to read
program code from memory, it uses 24-bit
addresses to reference bytes.
 When program accesses data space, it uses 23-bit
addresses to reference 16-bit words.
 In both cases, the address buses carry 24-bit
values, but during a data-space access, the least
significant bit on the address bus is forced to 0.

ESIEE, Slide 61 Copyright © 2003 Texas Instruments. All rights reserved.

 Data Memory

Data space is divided into 128 main data pages (0

through 127) of 64K addresses each.

An instruction that references a main data page

concatenates a 7-bit main data page value with a 16-bit
offset.

On data page 0, the first 96 addresses (00 0000h-

00 005Fh) are reserved for the memory-mapped
registers (MMRs).

ESIEE, Slide 62 Copyright © 2003 Texas Instruments. All rights reserved.

 I/O Memory
 I/O space is separate from data/program space and is
available only for accessing registers of the
peripherals on the DSP. The word addresses in I/O
space are 16 bits wide, enabling access to 64K
locations

 The CPU uses the data-read address bus DAB for

reads and data-write address bus EAB for writes.
When the CPU reads from or writes to I/O space, the
16-bit address is concatenated with leading 0s.

Example, suppose an instruction reads a word at the 16-bit address

0102h. DAB carries the 24-bit value 00 0102h.

ESIEE, Slide 63 Copyright © 2003 Texas Instruments. All rights reserved.

 C5510 Peripheral Overview
Host EHPI
C5510 MCBSP
GPIO
DMA 55xx Timers
External EMIF CPU
Memory Power
Boot Cache

EHPI 3 Multi-Channel Buffered SPs

- 16-bit host access to memory - High speed sync serial comm
DMA General Purpose I/O
- 6 Channels (rotating priority) - 8-bit i/o port
EMIF Timer/Counters
- Access to EPROM, SRAM, SBSRAM, - Two 20-bit timer/counters
SDRAM
Power-Down Modes
BOOT Loader
Instruction Cache (24K bytes)
- From external memory, Host, McBSP

ESIEE, Slide 64 Copyright © 2003 Texas Instruments. All rights reserved.

CPU Registers Description

C54x and C55x

Copyright © 2003 Texas Instruments. All rights reserved.

 CPU Registers C54x vs C55x
 The study of CPU registers gives a very
good understanding on the processor
architecture.
 The C54x DSP is code compatible with
the C55x, therefore registers have the
same functionally in both DSPs.
 Registers in the C55x are more complex
so we will see their role and give
equivalents for the C54x.
 The following table summarizes the
differences.

ESIEE, Slide 66 Copyright © 2003 Texas Instruments. All rights reserved.

 C55x CPU Registers and
C54x Equivalents 1 of 3

Abbreviation Name Size C54x

AC0–AC3 Accumulators 0 through 3 40 bits A,B
AR0–AR7 Auxiliary registers 0 to 7 16 bits same
BK03, BK47, BKC Circular buffer size registers 16 bits BK
BRC0, BRC1 Block-repeat counters 0 & 1 16 bits BRC
BRS1 BRC1 Save register 16 bits none
BSA01,
Circular buffer start address
BSA23,BSA45, 16 bits none
registers
BSA67, BSA
Coefficient data pointer (low
CDP 16 bits none
part of XCDP)
CDPH High part of XCDP 7 bits none

ESIEE, Slide 67 Copyright © 2003 Texas Instruments. All rights reserved.

 C55x CPU Registers and
C54x Equivalents 2 of 3
CFCT Control-flow context register 8 bits none
Computed single-repeat
CSR 16 bits none
register
DBIER0, Debug interrupt enable
16 bits none
DBIER1 registers 0 and 1
Data page register (low
DP 16 bits DP(9 )
part of XDP)
DPH High part of XDP 7 bits none
IER0, IER1 Interrupt enable registers 0& 1 16 bits IMR
IFR0, IFR1 Interrupt flag registers 0 and 1 16 bits IFR
IVPD, IVPH Interrupt vector pointers 16 bits IPTR(9 )
PC Program counter 24 bits PC(16)
PDP8 Peripheral data page register 9 bits none
Block-repeat end address
REA0, REA1 24 bits REA
registers 0 and 1

ESIEE, Slide 68 Copyright © 2003 Texas Instruments. All rights reserved.

 C55x CPU Registers and
C54 Equivalents 3 of 3
RETA Return address register 24 bits na.
RPTC Single-repeat counter 16 bits na.
Block-repeat start address registers 0
RSA0, RSA1 24 bits RSA
and 1
SP Data stack pointer 16 bits SP
SPH High part of XSP and XSSP 7 bits na.
SSP System stack pointer 16 bits na.
ST0,ST1,
ST0_55–ST3_55 Status registers 0 through 3 16 bits
PMST
T0–T3 Temporary registers 0 to 3 16 bits T
TRN0, TRN1 Transition registers 0 and 1 16 bits TRN
Extended auxiliary registers 0 through
XAR0–XAR7 23 bits na.
7
XCDP Extended coefficient data pointer 23 bits na.
XDP Extended data page register 23 bits na.
XSP Extended data stack pointer 23 bits na.
XSSP Extended system stack pointer 23 bits na.
C548, C549,
XPC(not C55) Extended program counter 7 bits C5402, C5410,
C5420

ESIEE, Slide 69 Copyright © 2003 Texas Instruments. All rights reserved.

 Accumulators (AC0–AC3)
 The C55 contains four 40-bit accumulators:
AC0, AC1, AC2, and AC3 (The primary function of these
registers is to assist in data computation in the D unit: ALU,
MACs and the shifter.
 The four accumulators are equivalent:
any instruction that uses an accumulator can be programmed
to use any one of the four.
 Each accumulator is partitioned into:
a low word (ACxL), a high word (ACxH), and eight guard
bits (ACxG).
 Each of portion can be accessed individually:
by using addressing modes that access the memory-mapped
registers.
 In the TMS320C54x-compatible mode (C54CM = 1),
accumulators AC0 and AC1 correspond to
TMS320C54x accumulators A and B, respectively.
ESIEE, Slide 70 Copyright © 2003 Texas Instruments. All rights reserved.
 Transition Registers (TRN0, TRN1)
 The two transition registers are used in the compare-
and-select-extremum instructions:
 When performing two 16-bit extremum selections update
TRN0 and TRN1 based on the comparison of two
accumulators’ high words and low words.
 TRN0 is updated based on the comparison of the
accumulators high words;
 TRN1 is updated based on the comparison of the low words.
 When performing a single 40-bit extremum selection the
selected transition register (TRN0 or TRN1) is updated
based on the comparison of two accumulators throughout
their 40 bits.
 TRN0 and TRN1 can hold transition decisions for the
path to new metrics in Viterbi algorithm
implementations.

ESIEE, Slide 71 Copyright © 2003 Texas Instruments. All rights reserved.

 Temporary Registers (T0–T3)
 Four 16-bit general-purpose temporary
registers: T0–T3 can be used for:
 Hold one of the memory multiplicands for
multiply, multiply-and-accumulate, and multiply-
and-subtract instructions
 Hold the shift count used in addition, subtraction,
and load instructions performed in the D unit
 Keep track of more pointer values by swapping
the contents of the auxiliary registers (AR0–AR7)
and the temporary registers (using a swap
instruction)
 Hold the transition metric of a Viterbi butterfly
for dual 16-bit operations performed in the D-unit
ALU
ESIEE, Slide 72 Copyright © 2003 Texas Instruments. All rights reserved.
 Registers Used to Address Data Space and
I/O Space
Auxiliary Registers (XAR0–XAR7 / AR0–AR7)
 The CPU includes eight extended auxiliary
registers XAR0–XAR7
 Each high part ( ARnH) is used to specify the 7-
bit main data page for accesses to data space.
 Each low part ( ARn) can be used as:
 A 16-bit offset to the 7-bit main data page (to form a 23-bit
address)
 A bit address (in instructions that access individual bits or bit
pairs)
 A general-purpose register or counter

ESIEE, Slide 73 Copyright © 2003 Texas Instruments. All rights reserved.

 ARn and XARn Access
 ARn Auxiliary register n and XARn Extended
auxiliary register n are accessible via
dedicated instructions .
ARn is mapped to memory
XARn is not mapped to memory.
 ARnH high part of extended auxiliary register
n is Not individually accessible.
To access ARnH, you must access XARn.
 XAR0–XAR7 or AR0–AR7 are used in the AR
indirect addressing mode and the dual AR
indirect addressing mode.
 Basic arithmetical, logical and shift operations
can be performed on AR0–AR7 in the A-unit
arithmetic logic unit (ALU).
ESIEE, Slide 74 Copyright © 2003 Texas Instruments. All rights reserved.
 Coefficient Data Pointer (XCDP / CDP)
 CDP is a coefficient data pointer, and CDPH
an associated extension register, concatenate
the two form the extended CDP that is called
XCDP
 CDPH is used to specify the 7-bit main data
page for accesses to data space.
 The low 16 bits part (CDP) can be used as:
 A 16-bit offset to the 7-bit main data page
(to form a 23-bit address)
 A bit address (in instructions that access
individual bits or bit pairs)
 A general-purpose register or counter
ESIEE, Slide 75 Copyright © 2003 Texas Instruments. All rights reserved.
 XCDP and CDP Accesses

 XCDP Extended coefficient data pointer is

accessible via dedicated instructions only.
XCDP is not a register mapped to memory.
 CDP Coefficient data pointer is accessible via
dedicated instructions and as a memory-
mapped register
 CDPH High part of extended coefficient data
pointer is accessible via dedicated instructions
and as a memory-mapped register

ESIEE, Slide 76 Copyright © 2003 Texas Instruments. All rights reserved.

 Circular Buffer Start Address Registers
(BSA01, BSA23, BSA45, BSA67, BSAC)
 The CPU includes five 16-bit circular buffer
start address registers
 Each buffer start address register is
associated with a particular pointer
 A buffer start address is added to the pointer
only when the pointer is configured for
circular addressing in status register ST2_55.

ESIEE, Slide 77 Copyright © 2003 Texas Instruments. All rights reserved.

 Circular Buffer Size Registers
(BK03, BK47, BKC)
 Three 16-bit circular buffer size registers
specify the number of words (up to 65535) in
a circular buffer.
 Each buffer size register is associated with
particular pointers
 In the TMS320C54x-compatible mode
(C54CM = 1), BK03 is used for all the
auxiliary registers, and BK47 is not used.

ESIEE, Slide 78 Copyright © 2003 Texas Instruments. All rights reserved.

 Data Page Register (XDP / DP)
 Data page register, DP, and associated
extension register DPH can be concatenated
to form an extended DP that is called XDP
 The high part (DPH) is used to specify the 7-
bit main data page for accesses to data space.
 The low part specifies a 16-bit offset (local
data page) that is concatenated with the main
data page to form a 23-bit address.
 In the DP direct addressing mode, XDP
specifies a 23-bit address, and in the k16
absolute addressing mode, DPH is
concatenated with a 16-bit immediate value to
form a 23-bit address.

ESIEE, Slide 79 Copyright © 2003 Texas Instruments. All rights reserved.

 DP/ XDP Accesses
 XDP Extended data page register Accessible
via dedicated instruction only. XDP is not a
register mapped to memory.
 DP Data page register accessible via dedicated
instructions and as a memory-mapped
register
 DPH High part of extended data page
Register is accessible via dedicated
instructions and as a memory-mapped
register

ESIEE, Slide 80 Copyright © 2003 Texas Instruments. All rights reserved.

 Peripheral Data Page Register (PDP)

 The 9-bit peripheral data page register

(PDP) selects a 128-word page within the
64K-word I/O space.

ESIEE, Slide 81 Copyright © 2003 Texas Instruments. All rights reserved.

 Stack Pointers (XSP / SP, XSSP / SSP)
 The data stack pointer (SP), a system stack
pointer (SSP), and an associated extension
register (SPH) are the CPU stack registers
 When accessing the data stack, the CPU
concatenates SPH with SP to form an
extended SP that is called XSP.
 XSP contains the address of the value last
pushed onto the data stack.
 SPH holds the 7-bit main data page of
memory, and SP points to the specific word on
that page.

ESIEE, Slide 82 Copyright © 2003 Texas Instruments. All rights reserved.

 Stack Register Accesses
 XSP Extended data stack pointer is accessible
via dedicated instructions only. XSP is not a
register mapped to memory.
 SP Data stack pointer is accessible via
dedicated instructions and as a memory-
mapped register
 XSSP Extended system stack pointer is
accessible via dedicated instructions only.
XSSP is not a register mapped to memory.
 SSP System stack pointer is accessible via
dedicated instructions and as a memory-
mapped register
 SPH High part of XSP and XSSP is accessible
via dedicated instructions and as a memory-
mapped register.
ESIEE, Slide 83 Copyright © 2003 Texas Instruments. All rights reserved.
 Program Flow Registers (PC, RETA, CFCT)

 PC Program counter is a 24-bit register holds

the address of the 1 to 6 bytes of code being
decoded in the I unit.
 When the CPU performs an interrupt or call,
the current PC value (the return address) is
stored on the stack, and then PC is loaded
with a new address.
 When the CPU returns from an interrupt
service routine or a called subroutine, the
return address is restored to PC.

ESIEE, Slide 84 Copyright © 2003 Texas Instruments. All rights reserved.

 RETA Return Address Register
CFCT Control-flow Context Register
If the selected stack configuration uses the
fast-return process
 RETA is a temporary holding place for the return
address and CFCT is a temporary holding place for
the 8-bit loop context while a subroutine is being
executed
 CFCT, along with RETA, enables the efficient
execution of multiple layers of subroutines
 You can read from or write to RETA and CFCT as
a pair with dedicated, 32-bit load and store
instructions.
 The Loop context is stored into CFCT, when an
interrupt or a subroutine call occur the loop
context is stored in CFCT and restored on return.
ESIEE, Slide 85 Copyright © 2003 Texas Instruments. All rights reserved.
 Registers For Managing Interrupts

 IVPD Point to the DSP interrupt vectors

(IV0–IV15 and IV24–IV31)
 IVPH Point to the host interrupt vectors
(IV16–IV23)
 IFR0, IFR1 Indicate which maskable
interrupts have been requested
 IER0, IER1 Enable or disable maskable
interrupts
 DBIER0, DBIER1 Configure select maskable
interrupts as time-critical interrupts

ESIEE, Slide 86 Copyright © 2003 Texas Instruments. All rights reserved.

 Interrupt Vector Pointers (IVPD, IVPH)
Two 16-bit interrupt vector pointers (IVPD and IVPH)
point to interrupt vectors in program space.

 The DSP interrupt vector pointer (IVPD) points to the

256-byte program page that contains the DSP
interrupt vectors (IV0–IV15 and IV24–IV31). These
vectors can be mapped to memory that is allocated to
the DSP only.
 The host interrupt vector pointer (IVPH) points to the
256-byte program page that contains the host interrupt
vectors (IV16–IV23). These vectors can be mapped to
memory shared by the DSP and the host processor, so
that the host processor can define the associated
interrupt service routines.
 If IVPD and IVPH have the same value, all of the
interrupt vectors will be in the same 256-byte program
page.
ESIEE, Slide 87 Copyright © 2003 Texas Instruments. All rights reserved.
 Interrupt Flag Registers (IFR0, IFR1)
The 16-bit interrupt flag registers, IFR1 and
IFR0, contain flag bits for all the maskable
interrupts:
 When a maskable interrupt request reaches the
CPU, the corresponding flag is set to 1 in one of
the IFRs.
 This indicates that the interrupt is pending, or
waiting for acknowledgement from the CPU.
 One can read IFRs to identify pending interrupts,
and write to the IFRs to clear pending interrupts.
 To clear an interrupt request write a 1 to the
corresponding IFR bit.
 All pending interrupts can be cleared by writing
the current contents of the IFR back into the IFR.
 Acknowledgement of a hardware interrupt
request also clears the corresponding IFR bit.
 A device reset clears all IFR bits.
ESIEE, Slide 88 Copyright © 2003 Texas Instruments. All rights reserved.
 RTOSINTF Bit in IFR1
 RTOSINTF bit 10 in IFR1 is an interrupt flag
bit for the real-time operating system
interrupt, RTOSINT
 When you read the RTOSINTF bit,
 If RTOSINTF=0, RTOSINT is not pending.
 If RTOSINTF=1, RTOSINT is pending.

 To clear this flag bit to 0 (and clear its

corresponding interrupt request), write
a 1 to the bit.

ESIEE, Slide 89 Copyright © 2003 Texas Instruments. All rights reserved.

 DLOGINTF and BERRINTF Bits in IFR1

 DLOGINTF is the bit 9 of IFR1 for the datalog interrupt,

 If DLOGINTF bit is:
 0 then DLOGINT is not pending.
 1 then DLOGINT is pending.
 BERRINTF is the 8th Bit in IFR1 is an Interrupt flag the
bus error interrupt, BERRINT
 If BERRINTF bit is:
 0 then BERRINT is not pending.
 1 then BERRINT is pending.
 To clear these flags to 0 (and clear the corresponding
interrupt request), write a 1 to the bit.

ESIEE, Slide 90 Copyright © 2003 Texas Instruments. All rights reserved.

 IF16–IF23 Bits in IFR1
/IF2–IF15 Bits in IFR0

 These are flag bits in IFR1 or IFR0

 If Interrupt flag IFx is:
 0 then the interrupt associated with
interrupt vector x is not pending.
 1 then the interrupt associated with
interrupt vector x is pending.
 To clear a flag bit to 0 (and clear its
corresponding interrupt request), write
a 1 to the bit.

ESIEE, Slide 91 Copyright © 2003 Texas Instruments. All rights reserved.

 Interrupt Enable Registers (IER0, IER1)
 To enable a maskable interrupt, set its
corresponding bit in IER0 or IER1 to 1.
 To disable a maskable interrupt, clear
its corresponding enable bit to 0.
 At reset, all the IER bits are cleared to
0, disabling all the maskable interrupts.
 IER1 and IER0 are not affected by a
software reset instruction or by a DSP
hardware reset.
 Initialize these registers before you
globally enable (INTM = 0) the
maskable interrupts.
ESIEE, Slide 92 Copyright © 2003 Texas Instruments. All rights reserved.
 RTOSINTE, DLOGINTE, BERRINTE and
IE16–IE23 Bits in IER1
& IE2–IE15 Bits in IER0
 RTOSINTE is the Enable bit for the
real-time operating system
interrupt,RTOSINT
 DLOGINTE is the Enable bit for the
data log interrupt, DLOGINT
 BERRINTE is the Enable bit for the bus
error interrupt, BERRINT
 IE16–IE23 bits are enable flags
interrupt associated with interrupt
vector x.
 IE2–IE15 bits are enable flags interrupt
associated with interrupt vector x.
ESIEE, Slide 93 Copyright © 2003 Texas Instruments. All rights reserved.
 Debug Interrupt Enable Registers
(DBIER0, DBIER1)
 DBIER1 and DBIER0 are used only when the
CPU is halted in the real-time emulation
mode of the debugger.
 A maskable interrupt enabled in a DBIER is
defined as a time-critical interrupt.
 When the CPU is halted in the real-time
mode, the only interrupts that are serviced
are time-critical interrupts that are also
enabled in an interrupt enable register (IER1
or IER0).
 Write the DBIERs to enable or disable time-
critical interrupts. To enable an interrupt, set
its corresponding bit.
ESIEE, Slide 94 Copyright © 2003 Texas Instruments. All rights reserved.
 Registers for Controlling Repeat Loops

 Single-Repeat Registers (RPTC, CSR)

 Block-Repeat Registers (BRC0–1,
BRS1, RSA0–1, REA0–1)
 These CPU registers are mapped in
memory

ESIEE, Slide 95 Copyright © 2003 Texas Instruments. All rights reserved.

 Status Registers (ST0_55–ST3_55)
 The four 16-bit registers (ST0_55, ST1_55, ST2_55
and ST3_55) contain control bits and flag bits
 Control bits affect the operation of the C55x DSP
 Flag bits reflect the current status of the DSP or
indicate the results of operations.
 ST0_55, ST1_55, and ST3_55 are each accessible at
two addresses
 At one address, all the TMS320C55x bits are available.
 At the other address (the protected address), some of the bits
cannot be modified.
 The protected address is provided to support TMS320C54x
code that was written to access ST0, ST1, and PMST (the
C54x counterpart of ST3_55).

ESIEE, Slide 96 Copyright © 2003 Texas Instruments. All rights reserved.

 Contents of Status Registers

ESIEE, Slide 97 Copyright © 2003 Texas Instruments. All rights reserved.

 ST0_55 Contents

 ACOV0, ACOV1, ACOV2, and ACOV3 bits

give for each of the four accumulators its own
overflow flag
 CARRY: this bit is the Carry/borrow
detection and depends on the M40 bit in
ST1_55:
 M40 = 0: Carry/borrow is detected with respect to
bit position 31.
 M40 = 1: Carry/borrow is detected with respect to
bit position 39.
 For compatibility with TMS320C54x code,
make sure M40 = 0.
ESIEE, Slide 98 Copyright © 2003 Texas Instruments. All rights reserved.
 DP Status Bits in ST0_55
 DP is a copy in ST0_55 of the 9 most
significant bits of the data page register (DP)
 This 9-bit field is provided for compatibility
with the TMS320C54x DSPs.
 TMS320C55x DSPs have a data page pointer
independent of ST0_55.
 Any change to bits 15–7 of the data page register
DP(15–7) is reflected in the DP status bits.
 Any change to the DP status bits is reflected in
DP(15–7).

ESIEE, Slide 99 Copyright © 2003 Texas Instruments. All rights reserved.

 TC1 and TC2 Bits of ST0_55
 TC1 and TC2 are Test/Control flag
 The main function of a test/control bits is to hold the
result of a test performed by specific instructions.
 All the instructions that affect a test/control flag allow
you to choose whether TC1 or TC2 is affected.
 TCx (where x = 1 or 2) or a Boolean expression of
TCx can be used as a trigger in any conditional
instruction.
 You can clear and set TC1 and TC2 with the following
instructions:
o BCLR TC1 ; Clear TC1
o BSET TC1 ; Set TC1
o BCLR TC2 ; Clear TC2
o BSET TC2 ; Set TC2

ESIEE, Slide 100 Copyright © 2003 Texas Instruments. All rights reserved.
 ASM Bit Field of ST1_55
 ASM is the Accumulator shift mode bit
 In the TMS320C54x-compatible mode ,
ASM supplies a shift value in the range –16
through 15 (5 bits in 2’s complement).
 If C54CM=1: C54x code running on the
C55x DSP, and ASM contains the shift
count for instructions that specify a shift of
an accumulator value.
 If C54CM = 0: ASM is ignored and the
shift count for an accumulator shift
operation comes from the temporary
register (T0, T1, T2, or T3) specified in the
C55x instruction or from a constant
embedded in the C55x instruction.

ESIEE, Slide 101 Copyright © 2003 Texas Instruments. All rights reserved.
 BRAF Bit of ST1_55
 BRAF: Block-repeat active flag is used in the
TMS320C54x-compatible mode (C54CM = 1).
 BRAF indicates/controls the status of a block-repeat
operation.
 If C54CM = 1 (C54x mode): BRAF is saved and
restored with ST1_55 during context switches caused
by calls, interrupts, and returns.
 BRAF is automatically cleared when a far branch
(FB) or far call (FCALL) instruction is executed.
 If C54CM = 0: BRAF is not used. The status of repeat
operations is maintained automatically by the CPU
(see CFCT )
 To stop or set an active block-repeat operation in the
C54x-compatible mode, you can use the following
instruction:
 BCLR BRAF ; Clear BRAF
 BSET BRAF ; Set BRAF

ESIEE, Slide 102 Copyright © 2003 Texas Instruments. All rights reserved.
 C16 Bit of ST1_55
 C16 is the Dual 16-bit arithmetic mode bit used in the
C54x-compatible mode (C54CM = 1), execution of
some instructions is affected by C16.
 The arithmetic performed in the D-unit ALU depends
on C16:
 If C16 =0 then for an instruction that is affected by C16, the D-unit
ALU performs one 32-bit operation (double-precision arithmetic) .
 If C16=1 then an instruction that is affected by C16, the D-unit
ALU performs two 16-bit operations in parallel (dual 16-bit
arithmetic).
 If C54CM = 0: The CPU ignores C16. The instruction
alone determines whether dual 16-bit arithmetic or
32-bit arithmetic is used.
 You can clear and set C16 with the following instructions:
 BCLR C16 ; Clear C16
 BSET C16 ; Set C16

ESIEE, Slide 103 Copyright © 2003 Texas Instruments. All rights reserved.
 C54CM Bit of ST1_55
 C54CM is the TMS320C54x-compatible mode bit
 The C54CM bit determines whether the CPU will
support code that was developed for a TMS320C54x
DSP:
 If C54CM=0 then the CPU supports code written for
a TMS320C55x (C55x) DSP.
 If C54CM=1 then you can use code that was
originally developed for a TMS320C54x (C54x) DSP.
 In C54 mode all the C55x CPU resources remain
available; the additional features on the C55x can be
used for code optimization.
 Change modes with the following instructions and
assembler directives:
 BCLR C54CM ; Clear C54CM (happens at run time)
 BSET C54CM ; Set C54CM (happens at run time)
ESIEE, Slide 104 Copyright © 2003 Texas Instruments. All rights reserved.
 CPL Bit of ST1_55
 CPL is the Compiler mode bit and determines
which of two direct addressing modes is active:
 CPL=0 then Direct accesses to data space are
made relative to the data page register (DP).
 CPL=1 then Direct accesses to data space are
made relative to the data stack pointer (SP). The
DSP is said to be in compiler mode.
 Change modes with the following instructions
and assembler directives:
 BCLR CPL ; Clear CPL (happens at run
time)
 BSET CPL ; Set CPL (happens at run time)

ESIEE, Slide 105 Copyright © 2003 Texas Instruments. All rights reserved.
 FRCT Bit of ST1_55
 FRCT is the Fractional mode bit that
sets the fractional mode on or off:
 FRCT=0 then results of multiply
operations are not shifted.
 FRCT=1 then results of multiply
operations are shifted left by 1 bit for
decimal point adjustment.
 This is required when you multiply two
signedQ15 values and you need a Q31
result.
 You can clear and set FRCT with :
 BCLR FRCT ; Clear FRCT
 BSET FRCT ; Set FRCT
ESIEE, Slide 106 Copyright © 2003 Texas Instruments. All rights reserved.
 HM Bit of ST1_55
 HM is the Hold mode bit used when the DSP
acknowledges an active HOLD signal. It
places its external interface in the high-
impedance state.
 Depending on HM, the DSP may also stop
internal program execution:
 HM=0 then the DSP continues executing
instructions from internal program memory.
 HM=1 then the DSP stops executing
instructions from internal program memory.
 To clear and set HM:
 BCLR HM ; Clear HM
 BSET HM ; Set HM
ESIEE, Slide 107 Copyright © 2003 Texas Instruments. All rights reserved.
 INTM Bit of ST1_55
 INTM is the Interrupt mode bit, it globally enables
or disables the maskable interrupts.
 If INTM =0 All unmasked interrupts are enabled.
 If INTM=1 All maskable interrupts are disabled.
 Software interrupt instruction and software reset
instruction, set INTM before branching to the
interrupt service routine.
 Before executing an interrupt service routine (ISR),
the CPU automatically sets the INTM bit to globally
disable the maskable interrupts. The ISR can re-
enable the maskable interrupts by clearing the INTM
bit.
 BCLR INTM ; Clear INTM
 BSET INTM ; Set INTM
 A return-from-interrupt instruction restores the
INTM bit from the data stack.
ESIEE, Slide 108 Copyright © 2003 Texas Instruments. All rights reserved.
 M40 Bit of ST1_55

 M40 is the computation mode bit for the D unit

 M40 bit selects one of two computation modes for the

D unit:
 If M40=0 then the sign bit is extracted from bit
position 31:
 During arithmetic, the carry is determined with respect to
bit position 31.
 Overflows are detected at bit position 31.
 During saturation, the saturation value is 00 7FFF FFFFh
(positive overflow) or FF 8000 0000h (negative overflow).
 Accumulator comparisons versus 0 are done using bits 31–0.
 Shift or rotate operations are performed on 32-bit values.

ESIEE, Slide 109 Copyright © 2003 Texas Instruments. All rights reserved.
 M40 Bit
 Note: In the TMS320C54x compatible
mode (C54CM = 1), CM=0
 An accumulator’s sign bit is extracted from bit
position 39.
 Accumulator comparisons versus 0 are done
using bits 39–0.
 Signed shifts are performed as if M40 = 1.
 M= 40-bit mode. In this mode the sign bit is
extracted from bit position 39, the same as
before on 40 bits.
 To clear and set M40 :
 BCLR M40 ; Clear M40
 BSET M40 ; Set M40

ESIEE, Slide 110 Copyright © 2003 Texas Instruments. All rights reserved.
 SATD Bit of ST1_55
 SATD is the Saturation mode bit, it determines
whether the CPU saturates overflow results in the D
unit:
 SATD =0 No saturation is performed.
 SATD=1 If an operation result gives an overflow, the
result is saturated. The saturation depends on the
value of the M40 bit:
 M40 = 0 The CPU saturates the result to 00 7FFF FFFFh
(positive overflow) or FF 8000 0000h (negative overflow).
 M40 = 1 The CPU saturates the result to 7F FFFF FFFFh
(positive overflow) or 80 0000 0000h (negative overflow).
 To clear and set SATD :
 BCLR SATD ; Clear SATD
 BSET SATD ; Set SATD

ESIEE, Slide 111 Copyright © 2003 Texas Instruments. All rights reserved.
 SXMD Bit of ST1_55
 SXMD is the Sign-extension mode bit. It sets
and resets the sign-extension mode, which
affects accumulator operations that are
performed in the D unit:
 If SXMD=0 then sign-extension mode is off:
 For 40-bit operations, 16-bit or smaller
operands are zero extended to 40 bits.
 For the conditional subtract instruction, any
16-bit divisor produces the expected result.
 When the D-unit arithmetic logic unit (ALU)
is locally configured in its dual 16-bit mode,
16-bit values used in the higher part of the D-
unit ALU are zero extended to 24 bits.
ESIEE, Slide 112 Copyright © 2003 Texas Instruments. All rights reserved.
 SXMD
 If SXMD=1 then 40-bit operations, 16-bit or smaller
operands are sign extended to 40 bits.
 When the D-unit ALU is locally configured in its dual
16-bit mode, 16-bit values used in the higher part of
the D-unit ALU are sign extended to 24 bits.
 16-bit accumulator halves are sign extended if they
are shifted right.
 During a signed shift of an accumulator, if it is a 32-
bit operation (M40 = 0), bit 31 is copied into the
accumulator’s guard bits (39–32).
 Set and reset SXMD by:
 BCLR SXMD ; Clear SXMD
 BSET SXMD ; Set SXMD

ESIEE, Slide 113 Copyright © 2003 Texas Instruments. All rights reserved.
 XF Bit of ST1_55

 The XF bit is a general-purpose output

bit that can be manipulated by software
and exported to XF pin of the DSP
 To clear and set XF:
 BCLR XF ; Clear XF
 BSET XF ; Set XF

ESIEE, Slide 114 Copyright © 2003 Texas Instruments. All rights reserved.
 AR0LC–AR7LC Bits of ST2_55
 AR0LC–AR7LC Bits are the
linear/circular configuration bits of the
eight auxiliary registers, AR0–AR7.
 If ARnLC= 0 ARn is used for linear
addressing
 If ARnLC=1 ARn is used for circular
addressing
 To clear and set the ARnLC bits
 BCLR AR0LC ; Clear AR0LC
 BSET AR0LC ; Set AR0LC

ESIEE, Slide 115 Copyright © 2003 Texas Instruments. All rights reserved.
 ARMS Bit of ST2_55
 ARMS AR mode switch bit determines the CPU mode
used for the AR indirect addressing mode:

 ARMS=0 « DSP mode operands », provides efficient

execution of DSP intensive applications. Among these
operands are those that use reverse carry propagation
when adding to or subtracting from a pointer.
Short-offset operands are not available.

 ARMS=1 « Control mode operands », enables

optimized code size for control system applications.
The short-offset operand *ARn(short(#k3)) is
available.
 BCLR ARMS ; Clear ARMS (happens at run time)
 .ARMS_off ; Tell assembler ARMS = 0
 BSET ARMS ; Set ARMS (happens at run time)
 .ARMS_on ; Tell assembler ARMS = 1

ESIEE, Slide 116 Copyright © 2003 Texas Instruments. All rights reserved.
 CDPLC Bit of ST2_55
 CDPLC is the CDP linear/circular
configuration bit. It determines whether
the coefficient data pointer (CDP) is
used for linear addressing or circular
addressing:
 CDPLC=0 Linear addressing
 CDPLC=1 Circular addressing

 To clear and set CDPLC :

 BCLR CDPLC ; Clear CDPLC
 BSET CDPLC ; Set CDPLC

ESIEE, Slide 117 Copyright © 2003 Texas Instruments. All rights reserved.
 DBGM Bit of ST2_55
 DBGM: Debug mode bit gives the ability to
block debug events during time-critical
portions of a program:
 If DBGM=0 Debug is enable
 If DBGM=1 Debug is disable, emulator
cannot access memory or registers.
 Software breakpoints still cause the CPU to
halt, but hardware breakpoints or halt
requests are ignored.
 Before interrupt service routine CPU sets the
DBGM bit to disable.
 Return-from-interrupt instruction restores
the DBGM bit from the data stack.
ESIEE, Slide 118 Copyright © 2003 Texas Instruments. All rights reserved.
 EALLOW Bit of ST2_55
/RDM Bit of ST2_55

 EALLOW is the Emulation access enable bit.

It enables or disables write access to non-CPU
emulation registers:
 If EALLOW =0 Emulation access is disabled
 If EALLOW=1 Emulation is enabled

 RDM, Rounding mode bit, defines the type of

rounding performed by the CPU:
 If RDM =0 the mode is Round to the infinite.
 CPU adds 8000h (215) to the operand then clears
bits 15 through 0 to generate a rounded result in a
24- or 16-bit representation.
ESIEE, Slide 119 Copyright © 2003 Texas Instruments. All rights reserved.
 Round Mode RDM
If RDM=1 then Round to the nearest.
The rounding depends on bits 15 through 0 of
the operand, and bits 15–0 are cleared
•For compatibility with TMS320C54x code,
RDM must be 0 and C54CM = 1.
•To clear or set
BCLR RDM ; Clear RDM
BSET RDM ; Set RDM

ESIEE, Slide 120 Copyright © 2003 Texas Instruments. All rights reserved.
 CACLR Bit of ST3_55
 CACLR, Cache clear bit, enables to check
when the process for clearing the program
cache is complete:
 CACLR=0 Complete. The cache hardware clears
the CACLR bit when the process is complete.
 CACLR=1 Not complete. All cache blocks are
invalid. The number of cycles needed to clear the
cache depends on the memory architecture.
 If cache is cleared, the content of the prefetch
queue in the instruction buffer unit is
automatically flushed.
 CACLR bit can be changed (pipeline protect):
 BCLR CACLR ; Clear CACLR
 BSET CACLR ; Set CACLR
ESIEE, Slide 121 Copyright © 2003 Texas Instruments. All rights reserved.
 CAEN Bit of ST3_55
 CAEN is the Cache enable bit that
enables or disables the program cache:
 CAEN =0 then cache is disabled.
 All program requests are handled either
by the internal memory or the external
memory, depending on the address
decoded.
 CAEN=1 Cache is enabled. Program
code is fetched from the cache, from the
internal memory, or from the external
memory, depending on the address
decoded.
ESIEE, Slide 122 Copyright © 2003 Texas Instruments. All rights reserved.
 CAFRZ Bit of ST3_55

 CAFRZ is « Cache freeze bit » that freezes

the program cache.
 IF CAFRZ =0, the cache is in its default
operating mode (updated)
 If CAFRZ=1, the cache is frozen (the cache
content is locked).
 To change CAFRZ bit use:
 BCLR CAFRZ ; Clear CAFRZ
 BSET CAFRZ ; Set CAFRZ

ESIEE, Slide 123 Copyright © 2003 Texas Instruments. All rights reserved.
 CBERR Bit of ST3_55
 CBERR is the « CPU bus error flag »
 The CBERR bit is set when an internal bus error is
detected. An error causes the CPU to set the bus error
interrupt flag (BERRINTF) in IFR1.
 The interrupt service routine for the bus error
interrupt (BERRINT) must clear the CBERR bit
before it returns control to the interrupted program
using: BCLR CBERR ; Clear CBERR
 If CBERR =0 The flag has been cleared by program
or by a reset.
 CBERR=1 An internal bus error has been detected.

ESIEE, Slide 124 Copyright © 2003 Texas Instruments. All rights reserved.
 CLKOFF Bit of ST3_55

 CLKOFF bit disables CLKOUT

 If CLKOFF = 1, the output of the
CLKOUT pin is disabled and remains at
a high level.
 Set and clear by:
 BCLR CLKOFF ; Clear CLKOFF
 BSET CLKOFF ; Set CLKOFF

ESIEE, Slide 125 Copyright © 2003 Texas Instruments. All rights reserved.
 HINT Bit of ST3_55

 HINT: Host interrupt bit is used to send

an interrupt request to a host processor
by the way of the host port interface.
 To produce an active-low interrupt
pulse clear and then set the HINT bit:
 BCLR HINT ; Clear HINT
 BSET HINT ; Set HINT

ESIEE, Slide 126 Copyright © 2003 Texas Instruments. All rights reserved.
 MPNMC Bit of ST3_55

• MPNMC defines the Microprocessor / Micro-

computer mode
• MPNMC reflects the logic level on the MP/MC
pin when the pin is sampled at reset
• The MPNMC bit enables or disables the on-chip
ROM.
 If MPNMC=0 Microcomputer mode. The on-chip
ROM is enabled; it is addressable in program space.
 If MPNMC=1 Microprocessor mode. The on-chip
ROM is disabled; it is not in the program-space map.

ESIEE, Slide 127 Copyright © 2003 Texas Instruments. All rights reserved.
 SATA Bit of ST3_55
 SATA is the Saturation mode bit for the A unit
 SATA bit determines whether the CPU
saturates overflow results of the A-unit
arithmetic logic unit (A-unit ALU):
 If SATA=0 No saturation is performed.
 If SATA=1 On. If result is in overflow,
result is saturated to 7FFFh or 8000h (for
positive or negative overflow respectively).
 Can be cleared and set by:
 BCLR SATA ; Clear SATA
 BSET SATA ; Set SATA

ESIEE, Slide 128 Copyright © 2003 Texas Instruments. All rights reserved.
 SMUL Bit of ST3_55
 SMUL is the Saturation-on-multiplication
mode bit:
 If SMUL =0 Off
 If SMUL =1 On.
 SMUL=1 forces the product of the two
negative numbers to be a positive number.
 For multiply-and-accumulate/subtract
instructions, the saturation is performed after
the multiplication and before the
addition/subtraction.
 Clear and set SMUL with :
 BCLR SMUL ; Clear SMUL
 BSET SMUL ; Set SMUL
ESIEE, Slide 129 Copyright © 2003 Texas Instruments. All rights reserved.
 SST Bit of ST3_55
 SST is the Saturate-on-store mode bit used
in the C54-compatible mode (C54CM=1)
 If C54CM=0 SST is ignored by the C55x.
 If C54CM = 1: SST turns the saturation-
on-store mode on or off.
 SST= 0 no saturation
 SST=1 CPU saturates a shifted or
unshifted accumulator value before
storing it. The saturation depends on the
value of the sign-extension mode bit
(SXMD)
ESIEE, Slide 130 Copyright © 2003 Texas Instruments. All rights reserved.