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ASIC Design and Implementation of Counters: Project Guide DR.T Surendar Reddy

This document discusses the design and implementation of a 16-bit binary counter with clock gating to reduce power consumption. It proposes a design that gates the clock signal at the nibble (4-bit) level to reduce switching power. The existing system uses a global clock for all flip-flops, while the proposed design gates the clock for groups of 4 bits to cut down dynamic power usage. Implementing clock gating is presented as an efficient technique for lowering power dissipation in integrated circuits like counters.

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Srinivas Goud
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81 views9 pages

ASIC Design and Implementation of Counters: Project Guide DR.T Surendar Reddy

This document discusses the design and implementation of a 16-bit binary counter with clock gating to reduce power consumption. It proposes a design that gates the clock signal at the nibble (4-bit) level to reduce switching power. The existing system uses a global clock for all flip-flops, while the proposed design gates the clock for groups of 4 bits to cut down dynamic power usage. Implementing clock gating is presented as an efficient technique for lowering power dissipation in integrated circuits like counters.

Uploaded by

Srinivas Goud
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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ASIC Design And Implementation of

Counters

PROJECT GUIDE
Dr.T Surendar Reddy

By :
K.Sahithi (15J41A04F0)
K.Varsha Sai (15J41A04F1)
T.Devi Manasa (15J41A04H4)
ABSTRACT
 Gating of the clock signal in VLSI chips is
nowadays a mainstream design methodology
for reducing switching power consumption.
 As a consequence many techniques have been
proposed to reduce power dissipation. This
gives the circuit level design of a 16-bit binary
counter implemented with clock gating at
nibble (4-bit) level.
 This analysis stresses the use of clock gating as
an efficient power reduction technique.
INTRODUCTION
 Counters are widely used as essential building
blocks for variety of circuit operations. Flip-flops
can be connected together to perform counting
operations. Such a group of flip-flops is a
counter.
 As a consequence many techniques have been
proposed to reduce clock system power
dissipation .
 Several techniques to reduce the dynamic
power have been developed, of which clock
gating is predominant
EXISITING SYSTEM
 In the traditional synchronous design style, the
system clock is connected to the clock pin on
every flip-flop in the design.
Results in :
 Power consumed by combinatorial logic whose

values are changing on each clock edge.


 Power consumed by flip-flops .

 Power consumed by the clock tree buffers in

the design.
PROPOSED SYSTEM
 Gating the clock path substantially reduces the
power consumed by a Flip Flop.

IMPLEMENTATION:
 16-bit counter without clock gating.

Zeroth Review
BLOCK DIAGRAM
Q<15:12>

Q<3:0> Q<7:4> Q<11:8>


4 bit 4 bit 4 bit
4 bit
Counter Counter Counter
Counter
1 3 4
2 e
e e
n n n
Q3 Q7 Q11
Pre-and Pre-and Pre-and

clk
EXPECTED OUTCOMES
ADVANTAGES
Counters are very well used for business
purposes, like in retail shops, for calculating the
ingoing and outgoing of customers.

Now it is important issue due to:


 High device density
 High operating frequency
THANK YOU...!

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