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Metalization Process

This document discusses metallization in VLSI devices. It covers topics like multi-level metallization to allow for finer connections between devices on lower levels and thicker connections on upper levels. It also discusses issues like speed (RC delay), intensity (electromigration and breakdown), stability, and voltage drop. The document outlines technologies like silicide contacts, salicide layers, damascene processes, and chemical mechanical polishing that are used to address these issues.

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sowbarniga soundararajan
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833 views24 pages

Metalization Process

This document discusses metallization in VLSI devices. It covers topics like multi-level metallization to allow for finer connections between devices on lower levels and thicker connections on upper levels. It also discusses issues like speed (RC delay), intensity (electromigration and breakdown), stability, and voltage drop. The document outlines technologies like silicide contacts, salicide layers, damascene processes, and chemical mechanical polishing that are used to address these issues.

Uploaded by

sowbarniga soundararajan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPT, PDF, TXT or read online on Scribd
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Metallization: Contact to devices,

interconnections between devices and to external

Signal (V or I) intensity and speed (frequency response, delay)


Issues in VLSI Metallization
 Speed: switching speed, RC delay
 Intensity: electromigration (I), electric breakdown (V)
 Stability: contact interface, stable I-V characteristics
 Voltage drop: IR drop reduces voltage on transistor
 Area: connection wires have to be narrow as device
density increases
Multi-level Metallization

Lower levels: fine


connections to individual
devices

Upper levels:
thicker/wider common
connections
Multi-level metal connections
Pit Formation of Al Contact with Si

High solubility of
Si in Al (~1%)
Al spikes
Silicide Contacts
Phase Diagram and Formation Sequence of Silicide
Salicide (Self-aligned silicide layer)
N-channel MOS with poly Si
gate

Ti deposition and annealing,


TiSi2 formation at source,
drain and gate

Etch away unreacted Ti

Apply dielectrics and final


metallization with Al
Multi-level Metallization
Plug Filling
Chemical Mechanical Polishing (CMP)
Damascene processes Dual damascene
Metal plugs in planar SiO2

Interlayer dielectric deposit

Trench patterning & RIE


for metal lines

Metal deposition

CMP Single barrier layer and metal deposition


steps, same metal for plugs and lines
Electromigration Effects
Void Pile-up

Bamboo-structured wire
Electromigration-resistant
Electron wind and field-driven atomic migration
Device Isolation

Triple diffusion p-well (tub)

2-sided diffusion n-well

Double-diffused epitaxial Epitaxy double-well


CMOS Technology

Simple CMOS layout


CMOS inverter
Twin-well CMOS process
Lateral Isolation

Trench isolation
Localized oxidation Oxidation isolation
isolation (LOCOS)
Simple MOS process
(a) Source & drain
p+ diffusion

(b) Wet oxidation


for field oxide

(c) Dry oxidation


for gate oxide

(d) Al metallization
for gate and
contacts to S & D
Poly-Si gate NMOS process
Field oxide growth
and opening etching

Gate oxide growth


and poly-Si deposit

Gate, source & drain


n+ diffusion

PSG CVD,
lithography and
metallization
General Process Integration
Considerations for ULSI
 In mask and process designs, tolerances for variations
in line width, junction depth and width, depletion zone width,
film thickness, mask-making and alignment
 Use self-aligned process if possible: e.g. source & drain
implantation, salicide process
 Step heights (vertical profile variation) must ensure a
positive focus margin (FM)
 Large process window and small sensitivity: tolerate
variation in equipment performance

 On-line monitoring of control parameters


Bonding & Packaging
Wafer with IC Chips

Thin film pads for


wire bonding
Plastic-encapsulated package

Back side of IC chip bond to a


metallized ceramic substrate

Au wires connecting
the IC and pins
Wire bonding process
Flip-chip bonding with Pb-Sn solder
ball in contact with a ceramic substrate

More interconnect pad


(>100) allowed

Shorter connection
length, less coupling

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