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Vasu DFT

DFT is a structured testing method used to detect manufacturing defects in chips after fabrication. Extra logic and signals are added to increase controllability and observability, allowing testing according to a predefined procedure. The circuit then has a normal mode and one or more test modes. DFT helps support various test environments and reduces test complexity and costs while allowing easier test vector generation. However, it also increases design complexity, impacts chip area/power/timing, and adds risks to the design schedule.

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1K views28 pages

Vasu DFT

DFT is a structured testing method used to detect manufacturing defects in chips after fabrication. Extra logic and signals are added to increase controllability and observability, allowing testing according to a predefined procedure. The circuit then has a normal mode and one or more test modes. DFT helps support various test environments and reduces test complexity and costs while allowing easier test vector generation. However, it also increases design complexity, impacts chip area/power/timing, and adds risks to the design schedule.

Uploaded by

senthilkumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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DFT is a structured way of testing to detect the

Manufacturing defects after Fabrication of


Chipset
Structured DFT

 Goal is to increase the Controllability and Observability of


a circuit
 Extra logic and signals are added to circuit so as to allow
the test according to some predefined procedure
 Circuit will have normal functional mode and one or more
Test Modes
Pros & Cons of DFT
Pros:
 Making it possible to support all test environment

 Manufacturing test

 Burn-in

 Life-cycles

 Board-level integration

 Engineering debug

 Customer return debug

 Yield enhancement & Failure Analysis

 Measurement of quality level deterministically

 Easier generation of necessary vectors

 Allowing cost-of-test to be reduced in all environments

 Reduces test complexity(and costs)

 Reduces tester time

 Reduces tester requirements(pins, memory depth, pin timing)


Pros & Cons of DFT
Cons:
 Adds work and complication to design methodology flow
 Negatively impacts chip design budgets such as

 Power

 Area

 Timing

 Package pin requirement

 Adds tasks & risk to design schedule

 Adding extra hardware, detects more defects and yield loss


will happen
 Defect---- A short to ground.
 Fault------Signal stuck at logic 0.
 Error------A=1, B=1, Output C=0; correct
output C=1.
DEFECT
FAULT
ERROR

Notice that the error is not permanent. As long as least one


input is 0, there is no error in the output.
Reason for Defect
Some typical defects in VLSI are:
 PROCESS DEFECTS: Missing contact window,
parasatic transistor, oxide breakdown, etc.
 MATERIAL DEFECTS: Surface Impurities, bulk
defects (cracks, crystal imperfections) etc.
 AGE DEFECTS: Di-electric breakdown,
electromigration, etc.
 PACKAGE DEFECTS: Contact Degradation, seal
leaks, etc.
Defects may occur during manufacture or during use of devices. Procedures for
diagnosing defects and finding their causes are known as Failure Mode Analysis
(FMA).
YIELD:
The percentage of acceptable parts
among all parts that are fabricated.
 Yield = Number of acceptable parts
Total number of parts fabricated

DEFECT PARTS PER MILLION(DPPM):


Faulty chips that passes the final test,
expressed as parts per million (ppm)
VERIFICATION:
It verifies the correctness of the design
performed by simulation methods
TESTING:
It verifies the correctness of the device
that detects the manufacturing defects.
 Functional Testing

 IDDQ Testing

 At Speed Testing
 Stuck At Faults
 Transistor Faults
 Bridging Fault
 IDDQ Fault
 Transition Fault
 Path Delay Fault
FAULT COVERAGE= NUMBER OF DETECTED FAULTS
TOTAL NUMBER OF FAULTS

TEST COVERAGE= NUMBER OF DETECTED FAULTS________________________


TOTAL NUMBER OF FAULTS-NO. OF UNDETECTED FAULTS
FUNCTIONAL vs. STRUCTURAL
X
1
0 1 D
0 0
0
D
1 D D

Detected pattern: 1 0 0 X

15
Vector

1010
1000
1101

0
0
1

PATTERN
BASIC SCAN PATTERN:
A pattern generated by Combinational ATPG, which contains
SCAN LOAD, FORCE ALL PI’S, MEASURE ALL PO’S, SCAN
UNLOAD.
FAST-SEQUENTIAL PATTERN:
A pattern generated by Fast-Sequential ATPG. These patterns
contain from 2 to 10 Clock cycles.
Each clock can contain a scan load, a force of all PI’s and a clock pulse.
The last clock cycle also contains a single measure of PO’s and a Single
Scan Unload
FULL-SEQUENTIAL PATTERN:
These pattern may be generated by Full-Sequential ATPG or
they may come from external source. They contain events that are
incompatible with the Basic Scan and Fast-Sequential Pattern. This can be
simulated only by a Fault Simulator
The main idea of Scan design is to obtain the
Controllability and Observability of Flipflops.
This is done by adding the Test Mode to the
Circuit. When the Circuit is in Test Mode all Flipflops
functionally form one or more Register. These are
called Scan Chain.
TYPES OF SCAN STYLES:
1. MUX Based
2. CLOCK Based
3. LSSD Based
 Controllability of circuit

The ability to set the pattern to the appropriate


logic values at desired location

 Observability of the circuit


The ability to observe the effect of
controllability
PI
PI

D s@1
0 D 0 0
D1 Q1 D2 Q2 D3
1 1 1 Q3
SI
X
RST

CLK

SE=1
SE=0
 To generate the Test Pattern the Comb. ATPG & Seq. ATPG works same.
 But in Seq. ATPG, if needs to initialize (Feed) the Flip flops. For this we
need some more patterns.
 To generate the patterns in Seq.ATPG first we will convert in to Virtual
Combinational circuit.
 In virtual Comb. Circuit it generates the Test Patterns to the Stuck-at-
faults.
 This means it removes (assume) the Flip flop and generate the patterns of
that circuit.
 This method is called TIME FRAME EXPANSION METHOD.
To generate Test Pattern, there are different type of
ATPG algorithms are used like Exhaust, Podem, Roth’s.
FULL SCAN PARTIAL SCAN

This scan will done for complete circuit This scan will be done for a part of the
circuit

Fault propagate to PO’s and then from Fault propagation till the next nearest flip-
backtracking to PI’s to generate Test flops and backtracks to few PI’s
pattern
Need more vectors to apply all PI’s Need less Vectors

Fault responses output from PO’s Fault response output from Scan out

More complexity to generate more Less complexity


vectors for bigger circuits.
CHECK POINT:
Primary inputs & fanouts branches of a
combinational circuit are called Check point.

THEOREM:
A Test pattern that detects all single stuck-at Faults
of the check point of a combinational circuit that
detects all single stuck-at Faults in that circuit.
ASIC FPGA
NRE involves cost for Design, Mask Since Hardware is already available, no
design and hence expensive non recurring expenses (NRE)

Longer “ Time To Market” Faster “ Time To Market”


Made for Specific application and hence Can be reprogrammed to suit another
cannot be reprogrammed to suit another application, so Reusable and Flexible.
application.
Full custom, every transistor and Standard array design and hence most
interconnect designed to serve the times hardware goes unused. Wastage is
purpose, hence no wastage. unavoidable
Because of NRE, ASIC based designs are Better suited for required number is less.
better if the required numbers are large

Faster than FPGA (GHz) Slower than ASIC (MHz)


To avoid set up time violations: Inserting the
buffers
To avoid hold time violations: Placing delay
cells/inverter pairs
LOC & LOS are the techniques used to detect the transition
Fault
EVENTS IN LOC:
1. Load scan chains SE=1
2. Force PI’s SE=0
3. Pulse a Clock (Launch) SE=0
4. Force PI’s SE=0
5. Measure PO’s SE=0
6. Pulse a Clock (Capture) SE=0
7. Unload Scan Chains SE=1
EVENTS IN LOS:
1. Int. Force PI’s SE=1
2. Load Scan Chains SE=1
3. Force PI’s SE=0
4. Measure PO’s SE=0
5. Pulse clock (Capture) SE=0
6. Unload Scan Chains SE=1

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