ASSIGNMENT 1

1. Why we need DFT? Advantage of DFT?

Need for DFT is the complexity of multimillion transistor based VLSI designs,
ensuring the reliability, dependability and testability of design is impossible without
systematic dft techniques. In volume production if bad parts are accidently delivered to a
customer often and exceed certain levels this can result in huge financial loses, catastrophic
failures and loss of reputation. By separating the non functional chips from the functional
chips at the manufacturing stage, resulting damages are prevented Automatic Test Pattern
Generation is much easier if proper dft techniques have been employed.
ADVANTAGES:

 Reduce test efforts.

 Reduce cost for test equipment.
 Shorten time-to-market.
 Increase product quality.

2. Difference between verification and test ?

VERIFICATION TESTING

It verifies the correctness of the design. It tests the correctness of manufactured device.
Done by simulation or formal methods, Two step process test generation and test
hardware emulation. application.
Performed only once. Applied to manufactured device.
Responsible for quality of design Responsible for quality of device.
Functional vectors are more. Test vectors are less
Functional coverage is less. Test coverage is more.

3. What is manufacturing Test and list down the goals?

Manufacturing tests are used to verify that every gate operates as expected.
Successful verification testing usually results in good chips. A successful verification
leads to the beginning of production. Fabricated chips are tested in the factory. This is
called manufacturing testing.
The purpose of manufacturing test is to discover any faults caused due to
manufacturing defects or errors.
Typical errors include:

 Layer to layer shorts.

 Discontinuous wires.
  Thin oxide shorts to substrate or well.
 Nodes shorted to power or ground
 Nodes shorted to each other.
 Inputs floating /output disconnected.

The following are the goals of testability:

 Maximization of test coverage

 Maximization of fault coverage
 Minimization of test time
 Minimize the test patterns
 Minimization of test generation effort
 Minimize hardware or software overhead needed for testing
 Make the system self testing as much as possible

4. What is Test Plan? What are requirements for Test plan?

A collection of all test specifications for a given area. The test plan contains a
high-level overview of what is tested and what is tested by others for the given feature
area.
Test plan is an executable document listing various scenarios to prove
the CUT will function as per the requirement specification and will not have any
unintended side effects.
1. Fault models
 Stuck at model
 Transition model
 Path delay
 Bridging delay model
 Small delay effect
 IDDQ
2. Compression logic
3. JTAG (or) ijag
4. BSCAN
5.MBIST
6. Number of DFT pins.

 Number of scan channel inputs

 Number of scan channel outputs
 Scan enable
 Reset
 EDT clock
 EDT update
 EDT bypass

5. Different types of faults?

 Stuck at fault
  Stuck at 0
 Stuck at 1
 Transistor fault
 Stuck open
 Stuck short
 Open and short fault
 Delay fault
 Path delay fault
 Gate delay fault
 Bridging fault
 Transition fault
 Small delay defect
 IDDQ
6. What are the different types of DFT methods?
 Ad-hoc design method
 Self test
 Logical self test
 Memory self test
 Structured design methods:
 Scan insertion
 Compression decompression
 Automatic test pattern generation(ATPG)
 Memory Built in self test (MBIST)
 Logic Built in self test (LBIST)
 Boundary scan
7. What are the cons of DFT?
Design for testing or design for testability (DFT) consists of IC design techniques
that add testability features to a hardware product design. The added features make it
easier to develop and apply manufacturing tests to the designed hardware.
DFT often is associated with design modifications that provide improved access
to internal circuit elements such that the local internal state can be controlled
(controllability) and/or observed (observability) more easily.
Design for testability (DFT) refers to those design techniques that make test
generation and test application cost effective.
1. What is difference between ASIC and FPGA?
ASIC (APPLICATION SPECIFICINTEGRATED FPGA(FIELD PROGRAMMABLE GATE
CIRCUIT) ARRAY)
Permanent circuitry. Once the application specific Reconfigurable circuit. FPGAs can be
circuit is taped-out into silicon, it cannot be changed. reconfigured with a different design. They
The circuit will work same for its complete operating even have capability to reconfigure a part
life. of chip while remaining areas of chip are
still working! This feature is widely used
in accelerated computing in data centres.
Same as for FPGA. Design is specified using HDL Design is specified generally using
such as Verilog, VHDL etc. hardware description languages (HDL)
such as VHDL or Verilog.
Very high entry-barrier in terms of cost, learning Easier entry-barrier. One can get started
curve, liaising with semiconductor foundry etc. with FPGA development for as low.
Starting ASIC development from scratch can cost
well into millions of dollars.
Suited for very high-volume mass production. Not suited for very high-volume mass
production.
Much more power efficient than FPGAs. Power Less energy efficient, requires more power
consumption of ASICs can be very minutely for same function which ASIC can achieve at
controlled and optimized. lower power.
ASIC fabricated using the same process node can Limited in operating frequency compared
run at much higher frequency than FPGAs since its to ASIC of similar process node. The
circuit is optimized for its specific function. routing and configurable logic eat up
timing margin in FPGAs.
Analog designs are not possible with FPGAs.
ASICs can have complete analog circuitry, for eg Although FPGAs may contain specific
Wi-Fi transceiver ,on the same die along with analog hardware such as PLLs, ADC etc,
microprocessor cores. This is the advantage which they are not much flexible to create for
FPGAs lack. example RF transceivers.
ASICs are definitely not suited for application areas FPGAs are highly suited for applications
where the design might need to be upgraded such as Radars, Cell Phone Base Stations
frequently or once-in-a-while. etc where the current design might need to
be upgraded to use better algorithm or to a
better design. In these applications, the
high-cost of FPGAs is not the deciding
factor. Instead, programmability is the
deciding factor.
It is not recommended to prototype a design using Preferred for prototyping and validating a
ASICs unless it has been absolutely validated. Once design or concept. Many ASICs are
the silicon has been taped out, almost nothing can prototyped using FPGAs themselves.
be done to fix a design bug (exceptions apply). Major processor manufacturers themselves
use FPGAs to validate their System-on-
Chips (SoCs). It is easier to make sure
design is working correctly as intended
using FPGA prototyping.
ASIC designers need to care for everything from FPGA designers generally do not need to
RTL down to reset tree, clock tree, physical layout care for back-end design. Everything is
and routing, process node, manufacturing handled by synthesis and routing tools
constraints (DFM), testing constraints (DFT) etc. which make sure the design works as
 Generally, each of the mentioned area is handled by described in the RTL code and meets timing.
different specialist person. So, designers can focus into getting the RTL
design done.

2. What is meaning of Fault and Defect?

 FAULT: A representation of a “defect” at the abstracted function level is called a
fault.
 DEFECT: A defect is an electronic system is the unintended difference between the
implemented hardware and its intended design.
 Defects occur either during manufacture or during the use of devices.
 Some typical defects in vlsi chips are:
 Process defects: Oxide breakdown, Parasitic transistors, missing contact
window, etc..
 Age defects: Electro migration, Dielectric breakdown, etc..
 Material defects: Crystal imperfection, Surface impurities, etc..
 Package defects: Contact degradation, seal leaks, etc

3. What is Yield? What is DPPM?

YIELD: Yield is defined as the function or percentage of acceptable parts among all
fabricated parts. The yield of a manufacturing process is defined as the percentage of
acceptable parts among all parts that are fabricated.

number of acceptable parts

Yield=
total number of parts fabricated
DPPM: DPPM is an acronym for Defective parts per million. DPPM is the total number
of defective parts produced for every 1 million parts. It is a common parameter to determine the
yield of a design.

 DPPM can be only truly measured when customers return defective parts.

4. DPPM should be lesser or more, which is better?

The lower the DPPM, the higher the quality of the product. For VLSI chips, while a
defect level of 500 ppm (parts per million) may be acceptable,10 ppm or lower represents high
quality.

5. Who all are the major DFT tool vendors and what all are the names of DFT tools(Vendor
wise)?

MENTOR SYNOPSIS CADENCE SYN TEST

ATPG FAST SCAN TETRAMAX ENCOUNTER DFT PRO
TEST
COMPRESSION TEST KOMPRESSDFT MAX DFT PRO
BOUNDARYSCAN BSD ARCHITECT TURBO BSD
(OR) JTAG
SCAN INSERTIONDFT ARCHITECTDFT COMPILER ENCOUNTER TURBO SCAN
TEST
MBIST MBIST
ARCHITECT
MENTOR Tessent scan: .mdt format
SYNOPSIS DFT compiler: .db format
CADENCE Genius (RC): .lib format
IJTAG : Boundary scan
Functionality is same only the file name is different.
6. How Test coverage plays role?
 Test coverage is percentage of detected fault from detectable fault in design .
 Detectable fault not contain the fault which are Tied, unused or redundant.
 If test coverage is less not able to identify the manufacturing defect.
So the product of the quality is reduced.

7. What is functional code coverage versus Structural Test coverage?

Functional Test coverage Structural test coverage

Attempts to validate that the design under Structural test makes no direct attempt to determine
test functions according to its functional if the overall functionality of the circuit is correct.
specification Instead, it tries to make sure that the circuit has been
assembled correctly from some low-level building
blocks as specified in a structural net list.

Functional testing focuses on testing all The idea is that if the net list is correct, and
possible functional states, given the structural testing has confirmed the correct
complexity of VLSI designs this is assembly of the circuit elements, then the circuit
almost impossible because of the infinite should be functioning correctly.
possible combinations.

Test vectors for functional testing focus One benefit of the Structural paradigm is that test
on the entire system as a black box, generation can focus on testing a limited number of
without giving any consideration to the relatively simple circuit elements rather than having
internal structure. to deal with an exponentially exploding multiplicity
of functional states and state transitions.

8. Why achieving good test coverage is important?

 Test Coverage is an important indicator of circuit quality and an essential part of
circuit maintenance.
 It helps in evaluating the effectiveness of testing by providing data on
different coverage items.
 It is a useful tool for finding untested parts of a circuit.
9. Explain FPGA design flow?
FPGA engineering process usually involves the following stages:

Architecture design. This stage involves analysis of the project requirements, problem
decomposition and functional simulation (if applicable). The output of this stage is a document
which describes the future device architecture, structural blocks, their functions and interfaces.
HDL design entry. The device is described in a formal hardware description language (HDL).
The most common HDLs are VHDL and Verilog.
Test environment design. This stage involves writing of test environments and behavioral
models (when applicable). They are later used to ensure that the HDL description of a device is
correct.
Behavioural simulation. This is an important stage that checks HDL correctness by comparing
outputs of the HDL model and the behavioural model (being put in the same conditions).
Synthesis. This stage involves conversion of an HDL description to a so-called netlist which is
basically a formally written digital circuit schematic. Synthesis is performed by a special software
called synthesizer. For an HDL code that is correctly written and simulated, synthesis shouldn't
be any problem. However, synthesis can reveal some problems and potential errors that can't be
found using behavioral simulation, so, an FPGA engineer should pay attention to warnings
produced by the synthesizer.
Implementation. A synthesizer-generated netlist is mapped onto particular device's internal
structure. The main phase of the implementation stage is place and route or layout, which
allocates FPGA resources (such as logic cells and connection wires). Then these configuration
data are written to a special file by a program called bit stream generator.
Timing analysis. During the timing analysis special software checks whether the implemented
design satisfies timing constraints (such as clock frequency) specified by the user
10. Explain ASIC design flow?

 
ASIC DESIGN FLOW
Specification: ‰

 Text description or system specification language

 Example: C, SystemC, SystemVerilog
RTL Description: ‰

 Automated conversion from system specification to RTL possible

 Example: Cadence C-to-Silicon Compiler ‰
 Most often designer manually converts to Verilog or VHDL 

Verification: ‰

 Generate test-benches and run simulations to verify functionality ‰

 Assertion based verification ‰
 Automated test-bench generation
RTL Synthesis: ‰

 Automated generation of generic gate description from RTL description ‰

 Logic optimization for speed and area ‰
 State machine decomposition, datapath optimization, power optimization ‰
 Modern tools integrate global place-and-route capabilities
Design For Testability:

 Insert various DFT features to perform device testing using Automated Test Equipment
(ATE) and system level tests ‰
 Scan enabled flip-flops and scan chains
 Automatic Test Pattern Generation (ATPG) tools generate test vectors to perform logic
and parametric testing ‰
 Built-in Self Test Logic: Based on LFSR (random-patterns) and MISR (signature)
(LBIST)
 Memory: Implements various memory testing (MBIST) ‰
 Boundary-Scan/JTAG Enables board/system level testing ‰
More on DFT and test insertion later
Floor planning /Placement/Routing: 

 Manually place major modules in the chip depending on connections with other modules
 Standard cell rows are defined next and the gates are placed ‰
 No routing channels between rows in newer technologies 
 Timing driven placement tries to minimize delay on critical paths 
 Routing ‰
 Route special nets
 Power, Ground ‰
 Clock tree synthesis/ routing;
 minimize skew, Insert buffers ‰
 Global and detailed routing of signal nets
TAPEOUT:

 When design passes logical verification, its ready for fabrication

 The tapeout design is in the form of GDSII file, which will be accepted by the foundry

11. Why achieving good test coverage is important?

The justification for ignoring untestable/undetectable faults is that any defect that occurs
at one of those fault locations will not cause the device to functionally fail.
For example,
if a stuck-at 1 defect occurred on a pin that is tied high by design, the part will not fail in
functional operation. Others would argue that fault coverage is more important because any
defect, even an untestable defect, is significant because it represents a problem in the
manufacturing of the device. 
12. Which scenario ASIC is preferred? Which scenarios FPGA is preferred?
ASIC: This scenario is used only in specified application.
Eg. Smart Television (snapdragon 8092), Laptops(INTEL I7 8th
generation),Mobile phones.(snapdragon 845,405,400,Media tek P22).
FPGA: This scenario is used in different application.
Eg. Microcontroller (8051) ,Microprocessor(8086).
13. ASIC consists of which all components? How all those can be tested using DFT?

 GATES
(AND, OR, NAND, NOR, EX-OR, EX-NOR,NOT)
It is tested using Stuck at, transition fault modelling.

 COMBINATIONAL CIRCUITS
(MUX)
It is tested using Stuck at and transition fault modelling.

 SEQUENTIAL CIRCUITS
 Latches It is tested
 D latch using Stuck at
 Flip Flops (D FLIP FLOP) and transition
 REGISTER fault
 SHIFT REGISTER modelling.
 Serial in, Serial out
 BIDI (Bidirectional input output port)
 BUFFER
 TRISTATE BUFFER
 CLOCK
(PLL, CLOCK DIVIDER,OCC)
14. DFT can be done in which all phases of ASIC flow?
 Scan insertion
 Compression decompression
 Memory Built in self test (MBIST)
 Logic Built in self test (LBIST)
 Automatic test pattern generation(ATPG)
 Boundary scan
 Simulation
 Post silicon

15. What is problem if we do not have DFT?

 Minimization of test coverage
 Minimization of fault coverage
 Maximization of test time
 Maximization the test patterns
 Maximize of test generation effort
 Maximize hardware or software overhead needed for testing