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Ec8252-Electronic Devices: Finfet

1. FinFET is a type of non-planar transistor that helps overcome limitations of planar CMOS technology as device sizes shrink. It has a thin silicon "fin" that forms the channel between the source and drain, wrapped by a conducting gate. 2. FinFET was developed in the late 1990s at UC Berkeley to address short channel effects like leakage in traditional planar MOSFETs as devices scaled down. It uses a double or triple gate design for better control of the channel. 3. Fabrication involves etching fins from silicon-on-insulator substrates, then growing thin gate oxides and depositing conducting gates around the fins to enable better electrostatic control than planar gates. This suppresses short

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Jothibasu Marappan
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264 views51 pages

Ec8252-Electronic Devices: Finfet

1. FinFET is a type of non-planar transistor that helps overcome limitations of planar CMOS technology as device sizes shrink. It has a thin silicon "fin" that forms the channel between the source and drain, wrapped by a conducting gate. 2. FinFET was developed in the late 1990s at UC Berkeley to address short channel effects like leakage in traditional planar MOSFETs as devices scaled down. It uses a double or triple gate design for better control of the channel. 3. Fabrication involves etching fins from silicon-on-insulator substrates, then growing thin gate oxides and depositing conducting gates around the fins to enable better electrostatic control than planar gates. This suppresses short

Uploaded by

Jothibasu Marappan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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EC8252- ELECTRONIC DEVICES

FinFET

Jothibasu M
AP(Sr.Gr)/ECE
PSGiTech
LIMITATIONS OF PLANAR TECHNOLOGY
Silicon CMOS has emerged in Semiconductor industry and the demand for scaling
– better device density and performance

However, scaling has some physical as well as practical barriers .

Due to downscale of CMOS technology, arises physical limitations and need for
alternative devices like Dual gate MOSFET , FINFET, CNT FET

In case of MOSFET, Gate channel length reduces- (short channel effects)

 More leakage current


 Fluctuation of device characteristics
 Control over the channel current flow is lost
 Reduction of Threshold voltage =- Drain-Induced barrier lowering (DIBL).
 Harder to turn the transistor off
Annotated die photo of a Fairchild chip
INTRODUCTION TO FINFET
• The term “FINFET” describes a non-planar, double
gate transistor built on an SOI substrate, based on
the single gate transistor design.

• The important characteristics of FINFET is that the


conducting channel is wrapped by a thin Si “fin”,
which forms the body of the device.

• The thickness of the fin determines the


ffective channel length of the device.
HISTORY OF FINFET
• FINFET is a transistor design first developed by Chenming Hu
and his colleagues at the University of California at Berkeley,
which tries to overcome the worst types of SCE(Short Channel
Effect).

• Originally, FINFET was developed for use on Silicon-On-


Insulator(SOI).

• SOI FINFET with thick oxide on top of fin are called


“Double-Gate” and those with thin oxide on top as well as
on sides are called “Triple-Gate” FINFETs
ATTRIBUTES OF THE SHORT CHANNEL
EFFECT
1. Limitation imposed on the electron drift
characteristics in the channel.

2. Modification of threshold voltage (Short Channel


Effect(SCE))
REASON FOR EVOLUTION OF
FINFET
• For the double gate SOI MOSFETs, the gates
control the energy barrier b/w source and drain
effectively.

• Therefore, the Short Channel Effect(SCE) can be


suppressed without increasing the channel
impurity concentration.
FINFET
Effective channel width
(W)=(Tfin+(2*Hfin))

Effective channel length


(Leff)=(Lgate+(2*Lext))
Why the name FinFET?

These devices have been given the generic name


“FinFETS" because the source/drain region forms fins
on the silicon surface.

TERMINALS:
Gate , Source and Drain
GENERAL LAYOUT & MODE OF
OPERATION
• The basic electrical layout and mode of operation of a
FINFET does not differ from a traditional FET.

• There is one source and one drain contact as well as a gate


to control the current flow.

• In contrast to planar MOSFET, the channel b/w source and


drain is build as 3D bar on top of the Si substrate and are
called fin.
CONTINUED………
The gate electrode is then wrapped around the channel, so that
there can be formed several gate electrodes on each side which
leads to the reduction in the leakage currents and an enhanced
drive current.
“FINS”
• The fin is used to form the raised channel.

• As the channel is very thin the gate has a great control over
carriers within it, but, when the device is switched on, the
shape limits the current through it to a low level.

• The thickness of the fin (measured in the direction from


source to drain) determines the effective length of the device.
TYPES
Based on the semiconductor material used:
•N-FinFET
•P-FinFET

In addition to this they are categorized based on


number of fins as well
Symbol of FinFET
FABRICATION OF FINFET
• The heart of the FINFET is a thin Si fin, which serves as a
body of the MOSFET.

• A heavily doped poly Si film wraps around the fin and makes
the electrical contact to the vertical faces of the fin.

• A gap is etched through the poly Si film to separate the


source and drain.

The various steps in the fabrication of FINFETs are discussed


as follows.
CHEMICAL VAPOUR DEPOSITION(CVD)
• SiN and SiO layers are deposited on Si film to make a
hard mask or a cover layer.

• The cover layer will protect the Si fi


throughout the fabrication process.

• Then, a layer of SiO2 is developed by the process


of dry etching.
• The layer of SiO2 is used to relieve the stress.
ELECTRON BEAM LITHOGRAPHY
• The fine Si fin is patterned by EB Lithography with
100keV acceleration energy.

• The resist pattern is slightly ashed at 5W and 30


sec to reduce the Si fin width.

• Then using top SiO layer as a hard etching


mask, the SiO layer is etched.

• By this process, the silicon fin is patterned.


NEXT PROCESSES
• A thin layer of sacrificial layer of SiO2 is grown.

• Then, the sacrificial oxide is stripped completely to remove


etch damage.

• While the cover layer protects the Si fin, the amorphous


Si is completely removed from the side of the Si fin.

• The amorphous Si is in contact with the Si fin at its side


surfaces becomes the impurity diffusion source that forms
the transistor source and drain.
OXIDATION
• The gate oxidation should thin the Si fin width slightly.

• By oxidizing the Si surface, gate oxide as thin as 2.5nm is


grown.

• Because the area of Si fin inside the surface is too small, we


use dummy wafers to measure the oxide thickness.

• Hence the gate oxide is grown.


FORMATION OF POLY-Si GATE
• The boron doped Si is deposited at 475`C as the gate
material.

• Because the source and drain extension is already formed


and covered by thick SiO layer, no high temperature steps
are required after the gate deposition.

• The total parasitic resistance due to probing is about 3000.


HOW TO REDUCE COMPLEXITY OF
FABRICATION???

– Due to the complexity of fabrication process, the FINFET


design was proposed to have a delta structure, so that
after the reduction of vertical feature height, the gate
channel-Gate stacked structure is realized by a Quasi-
Planar technology.
EVALUATION OF FINFET

• Current performance is poor.

• Conducted only in high voltages


REASON FOR POOR PERFORMANCE:
• Large bits and holes in the Si fin and the
source drain areas.

• In fabrication, photo resist alone is not a


sufficient task.
PARASITIC CAPACITANCE
• It is also known as stray capacitance.

• In electrical circuits, Parasitic capacitance is an unavoidable


and usually wanted capacitance that exists b/w parts of an
electronic component or circuit simply because of their
proximity (relationship) to each other.

• Circuit elements such as inductors, diodes and transistors


have internal capacitance and derivate from the circuit
elements.
HOW TO AVOID PARASITIC
CAPACITANCE

• Additional process steps are required to induce impurities


(appropriate type) below the fin to provide a Punch-
Through Stop(PTS), ensuring there is no direct current path
b/w gate and source and are electrically controlled by gate
input.
CONFIGURATION
•The FinFET device consists of a thin silicon body, wrapped by gate
electrodes.

•The current flows parallel to the wafer plane, whereas the channel is
formed perpendicular to the plane of the wafer.

•Due to this reason, the device is termed quasi-planar.

•The independent control of the front and back gates of the FinFET is
achieved by etching away the gate electrode at the top of the channel.
Working
•The working principle of a FinFet is similar to that of a conventional MOSFET.

•The channel shows maximum conductance when there is no voltage on the gate
terminal.

•As the gate voltage changes from positive to negative, the conductivity of the
channel reduces.
•To increase current flow – make the fins taller
CHARACTERISTICS
OUTPUT CHARACTERISTICS
TRANSFER CHARACTERISTICS
ADVANTAGES
• Higher technological maturity than planar DG.

• Suppressed Short Channel Effect(SCE)

• Better in driving current

• More compact and Faster switching times

• Low cost, Lower gate resistance, High gain


DISADVANTAGES
• Harder to manufacture and design

• Reduced mobility for electrons

• Higher source and drain resistances

• Poor reliability
Thank You

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