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CSE 460 Lec 2 Review of Digital Electronics

This lecture discusses the basic digital logic gates like NOT, AND, OR, NAND, NOR, XOR and XNOR. It also describes logic blocks like multiplexer, decoder, encoder and priority encoder. Finally, it covers sequential circuit elements like D latch and D flip-flop. The D flip-flop can be constructed by cascading a positive level triggered D latch with a negative level triggered D latch. While level triggered elements are sensitive to the clock level, edge triggered elements like flip-flops change state only on the clock edge.

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83 views21 pages

CSE 460 Lec 2 Review of Digital Electronics

This lecture discusses the basic digital logic gates like NOT, AND, OR, NAND, NOR, XOR and XNOR. It also describes logic blocks like multiplexer, decoder, encoder and priority encoder. Finally, it covers sequential circuit elements like D latch and D flip-flop. The D flip-flop can be constructed by cascading a positive level triggered D latch with a negative level triggered D latch. While level triggered elements are sensitive to the clock level, edge triggered elements like flip-flops change state only on the clock edge.

Uploaded by

Shovon Bhowmick
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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CSE 460: VLSI Design

Lecture 2: Review of Digital Electronics - Logic Gates, Blocks and


Sequential Elements
Logic gates
• NOT
• AND
• OR
• NAND
• NOR
• XOR
• XNOR
NOT Gate
• The simplest form of a digital logic circuit is the
inverter or the NOT gate
• It consists of one input and one output and the input
can only be binary numbers namely; 0 and 1
the truth table for NOT Gate:
AND Gate
• The AND gate is a logic circuit that has two or more inputs and
a single output
• The operation of the gate is such that the output of the gate is
a binary 1 if and only if all inputs are binary 1
• Similarly, if any one or more inputs are binary 0, the output
will be binary 0.
OR Gate
• The OR gate is another basic logic gate
• Like the AND gate, it can have two or more inputs and a single
output
• The operation of OR gate is such that the output is a binary 1
if any one or all inputs are binary 1 and the output is binary 0
only when all the inputs are binary 0
NAND Gate
• The term NAND is a contraction of the expression
NOT-AND gate
• A NAND gate, is an AND gate followed by an inverter
• The algebraic output expression of the NAND gate is
Y = A.B
NOR Gate
• The term NOR is a contradiction of the expression
NOT-OR
• A NOR gate, is an OR gate followed by an inverter
• The algebraic output expression of the NOR gate is Y
=A+B
More than 2 inputs
XOR Gate
• The algebraic output expression of the Ex-OR gate is Y = A ⊕ B =
• Copies input to output if the other input is 0
– if A=0, X=B
– if B=0, X=A
• Copies inverted input to output if the other input is 1
– if A=1, X=B’
– if B=1, X=A’
XNOR Gate
• The algebraic output expression of the Ex-NOR gate is X =
• Copies inverted input to output if the other input is 0
– if A=0, X=B’
– if B=0, X=A’
• Copies input to output if the other input is 1
– if A=1, X=B
– if B=1, X=A
Logic Blocks
• Multiplexer
• Decoder
• Encoder
Multiplexer
• Multiple inputs, single output. Output is chosen by selector pin/s
Decoder
• Multiple inputs, multiple outputs.
• One hot output
Binary Encoder
• Encodes input from 2n inputs to an n-bit output
• Inputs have to be one hot
Priority Encoder
• Useful when inputs are not one hot (multiple input bits 1 at the same
time)
• Priority sequence associated with each encoder
• Basic difference is in its hardware implementation
• An additional output, z is defined as: z=0 whenever all the inputs are 0
• Example: A 4 input priority encoder with priority sequence: 3>2>1>0
Sequential Circuit Elements
• Latch
• Flip-flop (FF)
D Latch
• Level sensitive element (Positive level triggered/Negative level triggered)
• A positive level triggered D latch copies D to output Q, if Clock=1, else
preserves the previous output
• A negative level triggered D latch copies D to output Q, if Clock=0, else
preserves the previous output

A positive level
triggered D latch
D Flip-flop
• Edge sensitive element
• Two types: Positive edge triggered or Negative edge triggered
• Copies the input D to output Q only at the activating edge
– Sets Q=D at positive edge (rising edge) of the clock, retains the old value of Q at any
other time for positive edge triggered flip-flop
– Sets Q=D at negative edge (falling edge) of the clock, retains the old value of Q at any
other time for negative edge triggered flip-flop
Graphical Symbol

Rising and Falling edges on Positive edge Negative edge


a Clock pulse triggered FF triggered FF
Building a FF using D Latches
• By cascading a positive level triggered and a negative level triggered D
latches we can build a negative edge triggered FF
Level triggered vs. Edge triggered
• In level triggered elements, output is affected by the level of the clock
• In edge triggered elements, output is affected by the edge of the clock
End of Slides

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