CHIP INPUT

AND
CHIP OUTPUT
CIRCUITS
 CHIP I/O CIRCUITS

➢WHAT ARE THEY ?

➢WHY DO WE NEED THEM ?
 WHAT ARE CHIP I/O CIRCUITS ?

➢ Chip I/O circuits can be considered as protection

layers for internal circuits.
 WHY DO WE NEED THEM ?

➢ Any external hazards such as ➢ Also, some chips have to

electrostatic discharge (ESD) communicate with TTL or ECL
and noises should be filtered bipolar chips,
out before propagating to the ➢ and in such cases, the I/O
internal circuits for circuit must provide proper
protection. level shifting so that the
transmitted signal contents can
be correctly received or sent by
the CMOS chip.
 We will discuss..

➢ The design of :
➢ electrostatic discharge-damage protection circuits
➢ Input circuits
➢ On-chip clock generation and distribution
➢ Output circuits
 ESD PROTECTION

➢ As we know Electrostatic discharge is the sudden flow

of electricity between two electrically charged objects
caused by contact,electrical short or dielectric
breakdown.
➢ ESD can occur when the charges stored in machines or
the human body are discharged to the chip.
 DIFFERENT MODELS FOR ESD
TESTING

➢ The human body model (HBM)

➢ The machine model (MM)
➢ The charged device model (CDM)
THE HUMAN BODY
MODEL(HBM)

➢ Typical ESD events can

discharge thousands of
volts of electricity, which
can be damaging to
sensitive circuits.
 ➢ ESD can be
introduced to a
circuit through
interface
connectors that
are exposed to
the outside
world.

➢ When charged objects, such as humans, come into close contact with
interface connectors, ESD current can be discharged, which could
damage circuit.
 ➢ To prevent
damage to a
system, ESD
protection
diodes can be
placed close to
the interface
connector.

➢ As a result, when ESD is discharged,the ESD protection diode will

pass it to ground and protect the circuitry behind it.
 THE HUMAN BODY MODEL
(HBM)
➢ You set up the test by applying a
high-voltage supply in series with a
1-MΩ resistor and a 100-pF
capacitor.
➢ After the capacitor is fully charged, a
switch is used to remove it from the
supply.
➢ Apply it in series with a 1.5-kΩ
➢ DUT-DEVICE UNDER TEST resistor and the DUT.
 THE MACHINE MODEL(MM)

➢ You set up the test with

supply in series with resistor
and a 200-pF capacitor.
➢ After the capacitor fully
charges, a switch is used to
remove it from the supply.
➢ Apply it in series to the DUT.
➢ Machines become electrically charged after
turn-on and discharge into DUT after
making contact by internal dielectric
breakdown or electric short.
 THE CHARGED DEVICE
MODEL(CDM)

➢ The CDM testing is a simulation for

situations that often happen
inautomated-manufacturing
environments in which devices slide
down shipping tubes or test handlers.
➢ When an external ground touches the
DUT of the charged device, the stored
charge will be discharged from the
device to the outside ground.

➢ The CDM ESD testers electrically

charge the DUT and then discharge it
to ground, through probing.
ESD PROTECTION NETWORKS
Three common
structures used
in ESD
protection are
the series
resistance,
steering diodes,
and absorption
device.
The steering
diodes turn
on and direct
the ESD
pulse away
from the
sensitive
circuit
elements to
the
absorption
device.
The series
resistance
limits the input
or output
current
The absorption
device absorbs
the energy of the
ESD pulse, and
limits the voltage
level to prevent
damage.
INPUT CIRCUITS
 INPUT CIRCUITS
❏ TRANSMISSION GATE
❏ LEVEL SHIFTING CIRCUITS(FOR TTL TO COMMUNICATE WITH CMOS )
❏ INVERTER
❏ NON INVERTING TTL
❏ SCHMITT TRIGGER
TRANSMISSION GATE

❏ The incoming signal A is fed into

the transmission gate through
the protection network (PN)
❏ The enable signal is generated
on-chip and controls the gating
of the input signal as :
❏ X=A when E=0
❏ X = high-impedance state for
E=1
INVERTER AS LEVEL SHIFTER

❏ CMOS Typical values

❏ VIL = 0.3VDD = (0.3 X 5V) = 1.5V
❏ VIH = 0.7VDD = (0.7 X 5V) = 3.5V
❏ In TTL
❏ VOL= 0.8 V
❏ VOH=2.0 V
INVERTER AS LEVEL SHIFTER

❏ Input circuit can be designed to

receive TTL signals for CMOS
logic circuits by adjusting the
ratio of the channel widths in
pMOS and nMOS transistors in
the inverter, such that the
saturation voltage at which both
transistors operate in saturation
region is set at the midpoint
between 0.8 V and 2.0 V.
INVERTER AS LEVEL SHIFTER

VOLTAGE TRANSFER CHARECTERISTIC CURVE

NON INVERTING TTL LEVEL SHIFTING CIRCUIT
SCHMITT TRIGGER

❏ Figure shows an input

circuit with Schmitt
trigger PN and 70-kΩ
pull-down resistor.
❏ This circuit provides
negative-going logic
threshold voltage of 1 V
and positive-going logic
threshold voltage of 4 V,
for 5-V power supply.
 So far we’ve seen...
❏ What are I/O ckts
❏ Need of I/O ckts
❏ ESD
❏ Types of ESD testers [HBM , MM , CDM]
❏ ESD Protection networks
❏ I/O circuits :
❏ Transmission gate
❏ Level shifting circuits for TTL communicating with CMOS :
❏ Inverter
❏ Non Inverting TTL
❏ Schmitt Trigger

THNQ !!!